LH5268A SHARP | Alldatasheet
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Technical content
LH5268A CMOS 64K (8K × 8) Static RAM
FEATURES
- • 8,192 × 8 bit organization
- • Access time: 100 ns (MAX.)
- • Power consumption: Operating: 220 mW (MAX.) 55 mW (MAX.) (tRC , tWC = 1 µs) Standby: 220 µW (MAX.) Data retention: 3.0 µW (VCC = 3 V, TA = 25°C)
- • Fully-static operation
- • Three-state outputs
- • Single +5 V power supply
- • TTL compatible I/O
- • Packages: 28-pin, 600-mil DIP 28-pin, 300-mil SK-DIP 28-pin, 450-mil SOP DESC RIPTION The LH5268A is a static RAM organized as 8,192 × 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 8A2 A12 GND A11 A10 CE 19 27 WE VCC 12 17 I/O1 NC OE I/O2 I/O3 I/O7 I/O6 I/O5 I/O4 I/O8 CE 2 5268A-1 TOP VIEW28-PIN DIP 28-PIN SK-DIP 28-PIN SOP
Figure 1. Pin Connections for DIP, SK-DIP,
Figure 2. LH5268A Block Diagram
CE 1 CE 2 WE OE MODE I/O 1 - I/O8 SUPPL Y CURRENT NOTE H X X X Deselect High-Z Standby (I SB )1 X L X X Deselect High-Z Standby (I SB )1 L H L X Write D IN Operating (ICC )1 L H H L Read D OUT Operating (ICC ) L H H H Output disable High-Z Operating (I CC ) NOTE: 1. X = H or L ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RA TING UNIT NOTE Supply voltage V CC -0.3 to +7.0 V 1 Input voltage V IN -0.3 to VCC + 0.3 V 1,2 Operating temperature Topr 0 to +70 °C Storage temperature Tstg -65 to +150 °C NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. VIN (MIN.) = -3.0 V for pulse width ≤50 ns. RECOMMENDED OPERATING CONDITIONS (T A = 0 to +70°C) PARAMETER SYMBOL MIN. TYP . MAX. UNIT NOTE Supply voltage V CC 4.5 5.0 5.5 V Input voltage VIH 2.2 V CC + 0.3 V VIL -0.3 0.8 V 1 NOTE: 1. VIN (MIN.) = -3.0 V for pulse width ≤50 ns. DC CHAR ACTERISTICS (TA = 0 to +70°C, VCC = 5 V ±10%) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input leakage current ILI VIN = 0 to VCC -1 1 µA Output leakage current ILO CE 1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = 0 V to VCC -1 1 µA Operating current I CC CE 1 = VIL, VIN = VIL or VIH CE 2 = VIH, II/O = 0 mA tCYCLE = 100 ns 40 mACE 1 = 0.2 V, VIN = 0.2 V or VCC - 0.2 V CE 2 = VCC - 0.2 V, II/O = 0 mA tCYCLE = 1.0 µs 10 Standby current ISB1 CE 1 = VIH or CE 2 = VIL 3m A ISB CE2 ≤ 0.2 V or CE 1 ≥ VCC - 0.2 V 40 µA 1 Output voltage VOL IOL = 2.1 mA 0.4 V VOH IOH = -1.0 mA 2.4 V NOTE: CMOS 64K (8K × 8) Static RAM L H5268A
(1) READ CYCLE (TA = 0 to +70°C, VCC = 5 V ±10%) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time t RC 100 ns Address access time tAA 100 ns Chip enable access time (CE 1)t ACE1 100 ns (CE2)t ACE2 100 ns Output enable access time t OE 40 ns Output hold time t OH 10 ns Chip enable to output in Low-Z (CE 1)t LZ1 10 ns 1 (CE2)t LZ2 10 ns 1 Output enable to output in Low-Z tOLZ 5n s 1 Chip enable to output in High-Z (CE 1)t HZ1 03 0 n s 1 (CE2)t HZ2 03 0 n s 1 Output disable to output in High-Z tOHZ 02 0 n s 1 NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. (2) WRITE CYCLE (TA = 0 to +70°C, VCC = 5 V ±10%) PARAMETER S YMBOL MIN. MAX. UNIT NOTE Write cycle time t WC 100 ns Chip enable to end of write t CW 80 ns Address valid to end of write t AW 80 ns Address setup time t AS 0n s Write pulse width t WP 60 ns Write recovery time t WR 0n s Data valid to end of write t DW 40 ns Data hold time t DH 0n s Output active from end of write t OW 10 ns 1 WE to output in High-Z t WZ 03 0 n s1 OE to output in High-Z t OHZ 02 0 n s1 NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. AC TEST CONDITIONS PARAMETER MODE NOTE Input voltage amplitude 0.6 to 2.4 V Input rise/fall time 10 ns Timing reference level 1.5 V Output load conditions 1TTL + C L (100 pF) 1 NOTE: 1. Includes scope and jig capacitance. LH5268A CMOS 64K (8K × 8) Static RAM
- This parameter is sampled and not production tested.
during the data retention mode. Figure 3. Low Voltage Data Retention
Figure 4. Read Cycle
- The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP ).
- tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,
to the time when the writing is finished. AS is defined as the time from address change to writing start.
- tWR is defined as the time from writing finish to address change.
Figure 5. Write Cycle 1
- The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP ).
- tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,
to the time when the writing is finished. AS is defined as the time from address change to writing start.
- tWR is defined as the time from writing finish to address change.
- When I/O pins are in the output state, input signals with the opposite logic level must not be applied.
1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the
outputs will remain high-impedance.
1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the
outputs will remain high-impedance. Figure 6. Write Cycle 2
DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28DIP (DIP028-P-0600) 11 4 1528 28DIP-2 13.45 [0.530] 12.95 [0.510] 0.51 [0.020] MIN. 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] 0.30 [0.012] 0.20 [0.008] DETAIL 36.30 [1.429] 35.70 [1.406] 0° TO 15° 4.50 [0.177] 4.00 [0.157] 15.24 [0.600] TYP. 28-pin, 600-mil DIP 28DIP (DIP028-P-0300) DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 11 4 1528 28DIP-6 7.05 [0.278] 6.65 [0.262] 0.51 [0.02] MIN. 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. 0.56 [0.022] 0.36 [0.014] 0.35 [0.014] 0.15 [0.006] DETAIL 35.00 [1.378] 34.40 [1.354] 0° TO 15° 3.65 [0.144] 3.25 [0.128] 7.62 [0.300] TYP. 28-pin, 300-mil DIP CMOS 64K (8K × 8) Static RAM L H5268A
X Package LL Power 5268A-7 CMOS 64K (8K x 8) Static RAM Blank 28 pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil DIP (DIP028-P-0300) N 28-pin, 450-mil SOP (SOP028-P-0450) Example: LH5268AD-10LL (CMOS 64K (8K x 8) Static RAM, Low-Low-power standby, 100 ns, 28-pin, 300-mil DIP)) - ## Speed 10 100 Access Time (ns)
ORDERING INFORMATION
DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP (SOP028-P-0450) 12.40 [0.488] 11.60 [0.457] 8.80 [0.346] 8.40 [0.331] 10.60 [0.417] 18.20 [0.717] 17.80 [0.701] 0.15 [0.006] 1.025 [0.040] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.10 [0.004] 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 28 15 141 1.70 [0.067] 1.70 [0.067] 28SOP 28-pin, 450-mil SOP LH5268A CMOS 64K (8K × 8) Static RAM