LH52253 SHARP | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 7

Technical content

FEATURES The LH52253 offers an Output Enable (G) for use in Managing the Data Bus. Bus contention during Write « Fast Access Times: 15 */20/25/35 ns ee a! be easily avolded by using the G input in the 12253. * Standard 28-Pin, 300-mil DIP High-frequency design techniques should be em- e Space Saving 28-Pin, 300-mil SOJ ployed to obtain the best performance from these de- vices. Solid, low-impedance power and ground planes, e JEDEC Standard Pinouts with high-frequency decoupling capacitors, are recom- mended. Series termination of the inputs should be con- * Low Power Standby when Deselected sidered when transmission line effects occur. e TTLCompatible VO PIN CONNECTIONS e 5V+10% Supply i i 28-PIN DIP TOP VIEW e Fully Static Operation 20ND e Common VO for Low Pin Count NCC] te 2811 Veo A,L] 2 27 As FUNCTIONAL DESCRIPTION a3 apa The LH52253 is avery high-speed 256K-bit static RAM AC 4 250 Ay organized as 64K x 4. This RAM is fully static in operation. AgOIS 24D A, The Chip Enable (E) reduces power to the chip when E AC] 6 zat, Is Inactive (HIGH). The combination of E and W control aid 7 20 the mode of operation of the LH52253. AraC] 8 2iFI NO _ Write cycles occur when both E and Write Enable (W) Ast 9 200) NC are LOW. Data is transferred from the DQ pins to the AuCht0 190 Da, memory location specified by the 16 address lines. AC tev, When E Is LOW and W is HIGH, a stalic read of the Ech 17E0a, memory location specified by the address lines will occur. Gch3 161 0Q) Since the device is fully static in operation, new read Vss C14 sOW cycles can be performed by simply changing the address. An Automatic Power Down feature reduces the current ses consumption when Read and Write cycles extend beyond their minimum cycle times. Figure 1. Pin Connections for DIP and SOJ * Note: only the 15 ns access time part is Advance Information. 4-106 SHARP

Figure 2. LH52253 Block Diagram

ABSOLUTE MAXIMUM RATINGS * 7 [paramere rag T- Yb -A3-/0 [Oc Outputcurent® | e40ma [ Power Dissipation (Package Limi) | ow NOTES: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating for transient conditions only. Function operation of the device at these or any other conditions above those Indicated In the "Operating Range” of thls specification is not Imptied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Outputs should not be shorted for more than 30 saconds. No more than one output should be shorted at any time. OPERATING RANGES ; [svmeo. [parameter [| min | typ [max | unir_| | ta | Temperature,ambient | 0 | [| 70 | °C | | voc | Supplyvotage | 45 | | ss | VI [ Vu | Logioorinputvotage' |-05| | 08 | v | [vu | Logic" input votage | 22 | | voo+os | v | NOTE: 1. Negative undershoot of up to 3.0 Vis permitted once per cycle. DC ELECTRICAL CHARACTERISTICS [symso. | PARAMETER | TesTcoNpivions | win | tvp | max | unir_| eor_|cwonmacinen' | BREE IE Seo ||| | ma | or [owes acest [| [oe] oom RES [| | for anivone | SRERR GEM || [= fm [tu | inputteakage Curent | Veo=55V.vw=0viovec | -2 | | 2 | wa | | wo | VOLeckage Curent | Veo=55V.Vin=OVtoveo | -2 | | 2 | wa | [You | OutputHignVottage | ton=-40ma_ | 2 || Lvo. | Ouiputtowvotage [to-soma | | 1 leots dependent upon output loading and cycle rates. Specified values are with outputs open, operating at specified cycle timos. 2. Note: only the 15 ns access time part is Advance Information.

[input ise and Faltimes | Sms | 480 OHMS paps CAPACITANCE * 255 OHMS 90 pF [ene (InpuvOutput Capacitance) | pF __| = NOTES: . * INCLUDES JIG AND SCOPE CAPACITANCES 2259-2. 1, Capacitances are maximum values at 25°C measured at 1.0MHz 2 Sead anctisoed. “ Figure 3. Output Load Circuit AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) leo [ResdGcetiming «ds | [ao] Ts] fs | [ns | Kia address AccessTime |__| ts { | 2 | [2 | | 35 | ns | Hon [Output Holdtrom Address Orange] 3 | | 3 | | 3 | | 3 | | ns | Hee TE towtovaiddata | | te | | eo | fs P| 5 | os Haz [Etowto Oulputvcive® | 4 | [4 [ [4 { [4 } [ns | Mar [GtowtoVaidoata (| |e} || [rl | 15 | ns | Har | Stowtooutputacwve’® | 0} [of |o | [of | rs | Heo LEnighto Powerbowntime® |__| 20 | 2 [ [so | | 35 | ns | lwo [witeteietme SL ts | dT oT Ts Tf as | [os | lew Etowtoendotwae {12 | [is {[ [a { || | ns | Haw [Address Vaidtoendotwae | 12] [1s | | eo | [a | | ns | Hae addressseup | 0: || co | ~ | oc Tf co | ds | Man AddressHoldtomW@rign | o | | o| | of [oT] | os | Hw Wrusewan tt] | 2 | fs | | ao} | | How [input DataSewptime | 8 | | so] [ao] [se] |e | Hon inputDatatiotime | o | to | |o {Jo} [ns | rms [Wrigntoouputacne’® | «| [4 | [a [a | {ns | Hine | Whowto Ouputhighz’® | |e [ 17 {se | [10 [ns | 4. AC Electrical Characteristics specified at “AG Test Conditions" levels. 2. Active output to High-Z and High-Z to output active tasts specified for a +500 mV transition from steady state levels into the tast load. 3%. Gonantond but not tasted. 4, Note: only the 15 ns dcoess time part Is Advance {nformation.

ORDERING INFORMATION

~Yb-23-/0 LH52253 xX - Ht Device Type Package Speed 15° Ct Access Time (ns) D 28-pin, 300-mil DIP (DIP28-P-300) K 28-pin, 300-mil SOJ (SOJ28-P-300) CMOS 64K x 4 Static RAM * Only the 15 ns dccess time part is Advance Information. Example: LH52253K-25 (CMOS 64K x 4 Static RAM, 25 ns, 28-pin, 300-mil $OJ) soosauol