LH521028 SHARP | Alldatasheet
Document overview
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Technical content
LH521028 CMOS 64K × 18 Static RAM
FEATURES
- • Fast Access Times: 17/20/25/35 ns
- • Wide Word (18-Bits) for: – Improved Performance – Reduced Component Count – Nine-bit Byte for Parity
- • Transparent Address Latch
- • Reduced Loading on Address Bus
- • Low-Power Stand-by Mode when Deselected
- • TTL Compatible I/O
- • 5 V ± 10% Supply
- • 2 V Data Retention
- • JEDEC Standard Pinout
- • Package: 52-Pin PLCC FUNCTIONAL DESCRIPTION The LH521028 is a high-speed 1,179,648-bit CMOS SRAM organized as 64K × 18. A fast, efficient design is obtained with a CMOS periphery and a matrix con- structed with polysilicon load memory cells. The LH521028 is available in a compact 52-Pin PLCC, which along with the six pairs of supply terminals, provide for reliable operation. The control signals include Write Enable ( W), Chip Enable (E), High and Low Byte Select (S L and SH ), Output Enable (G) and Address Latch Enable (ALE). The wide word provides for reduced component count, improved density, reduced Address bus loading and improved per- formance. The wide word also allows for byte-parity with no additional RAM required. This RAM is fully static in operation. The Chip Enable E) control permits Read and Write operations when active (LOW) or places the RAM in a low-power standby mode when inactive (HIGH).The Byte-select controls, S H and SL, are also used to enable or disable Read and Write operations on the high and the low bytes. The Address Latches are transparent when ALE is HIGH (for applica- tions not requiring a latch), and are latched when ALE is LOW. The Address Latches and the wide word help to eliminate the need for external Address bus buffers and/or latches. Write cycles occur when Chip Enable ( E), SH and/or SL, and Write Enable (W) are LOW. The Byte-select signals can be used for Byte-write operations by disabling the other byte during the Write operation. Data is trans- ferred from the DQ pins to the memory location specified by the 16 address lines. The proper use of the Output Enable control ( G) can prevent bus contention. When E and either SH or SL are LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be performed by simply changing the address with ALE HIGH. PIN CONNECTIONS 521028-1D DQ 8 DQ 7 DQ 6 VCC VSS DQ 5 DQ 4 DQ 3 DQ 2 VSS VCC DQ 1 DQ 0 DQ 9 DQ 10 VCC VSS DQ 11 DQ 12 DQ 13 DQ 14 VSS VCC DQ 15 DQ 16 DQ 17 E SH SL VCC VSS W ALE G A15 A14 A13 VSS VCC A10 A11 A12 52-PIN PLCC TOP VIEW
Figure 1. Pin Connections for PLCC Package
Figure 2. LH521028 Block Diagram
ADDRESS E SH SL ALE G WD Q 0-DQ 8 DQ 9-DQ 17 MODE I CC Don’t Care HXXHXX High-Z High-Z Standby I SB Valid LLH HLH Active High-Z Read I CC1 Valid LHLHLH High-Z Active Read I CC1 Valid LLLHLH Active Active Read I CC1 Valid LLLHH H High-Z High-Z Read I CC1 Don’t Care LLLLLH Data Out Data Out Read I CC1 Valid LLH HXL Data In Don’t Care Write, low byte I CC1 Valid LHLHXL Don’t Care Data In Write, high byte I CC1 Valid LLLHXL Data In Data In Write, both bytes I CC1 Valid LHHHX L Don’t Care Don’t Care Write, inhibited ICC1 Don’t Care LLLLXL Data In Data In Write, both bytes I CC1 NOTE: X = Don’t Care, L = LOW, H = HIGH PIN DESCRIPTIONS PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL
1 V SS 14 DQ 13 27 VSS 40 DQ 4
2V CC 15 DQ 14 28 V CC 41 DQ 5
3 S L 16 VSS 29 A8 42 VSS
4 S H 17 VCC 30 A9 43 VCC
5 E 18 DQ 15 31 A10 44 DQ 6
6 A 0 19 DQ 16 32 A11 45 DQ 7
7 A 1 20 DQ 17 33 A12 46 DQ 8
8 DQ 9 21 A2 34 DQ 0 47 A13
9 DQ 10 22 A3 35 DQ 1 48 A14
10 V CC 23 A4 36 VCC 49 A15
11 V SS 24 A5 37 VSS 50 G
12 DQ 11 25 A6 38 DQ 2 51 ALE
13 DQ 12 26 A7 39 DQ 3 52 W
CMOS 64K × 18 Static RAM LH521028 4-213
V CC Positive Supply Voltage Terminals V SS Reference Terminals A 0 – A15 Address Bus Input The Address bus is decoded to select one 18-bit word out of the total 64K words for Read and Write operations. E Chip Enable Active LOW Input Chip Enable is used to enable the device for Read and Write operations. When HIGH, both Read and Write operations are disabled and the device is in a reduced power state. When LOW, a Read or Write operation is enabled. W Write Enable Active LOW Input Write Enable is used to select either Read or Write operations when the device is enabled. When Write Enable is HIGH and the device is Enabled, a Read operation is selected. When Write Enable is LOW and the device is enabled, a Write operation is selected. A Byte- write operation is available by using the Byte-select con- trols. S H, S L Select High Active LOW Inputs Select Low The Select High and Select Low signals, in conjunction with the Chip Enable and Write Enable signals, allow the selection of the individual bytes for Read and Write op- erations. When High, the Select signal will deselect its byte and prevent Read or Write operations. When the Select signal is LOW and Chip Enable is LOW, a Read or Write operation is performed at the location determined by the contents of the Address bus. When Chip Enable is HIGH, the Select signals are Don’t Care. Select Low ( S L) is assigned to DQ0 – DQ 8 and Select High (SH) is assigned to DQ9 – DQ17. ALE Address Latch Active High Input Enable The Address Latch Enable signal is used to control the Transparent latches on the Address bus. The Latches are transparent when HIGH and are latched when LOW. If not required, Address Latch Enable may be tied HIGH, leaving the Address bus in a transparent condition. DQ 0 – DQ17 Data Bus Input/Output DQ 0 – DQ8 comprise the Low byte, selected by SL, and DQ9 – DQ17 comprise the High Data byte, selected by SH. The Data Bus is in a high impedance input mode during Write operations and standby. The Data bus is in a low-impedance output mode during Read operations. G Output Enable Active LOW Input The Output Enable signal is used to control the output buffers on the Data Input/Output bus. When G is HIGH, all output buffers are forced to a high impedance condi- tion. When G is LOW, the output buffers will become active only during a Read operation (E and SH / S L are LOW, W is HIGH). LH521028 CMOS 64K × 18 Static RAM 4-214
ABSOLUTE MAXIMUM RATINGS 1 PARAMETER RATING VCC to VSS Potential –0.5 V to 7 V Input Voltage Range –0.5 V to V CC + 0.5 V DC Output Current 2 ± 40 mA Storage Temperature Range –65 oC to 150oC Power Dissipation (Package Limit) 2 W NOTES: 1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. OPERATING RANGES SYMBOL PARAMETER MIN TYP MAX UNIT TA T emperature, Ambient 07 0 oC VCC Supply Voltage 4.5 5.0 5.5 V VSS Supply Voltage 0 00V VIL Logic ‘0’ Input Voltage 1 –0.5 0.8 V VIH Logic ‘1’ Input Voltage 2.2 V CC + 0.5 V NOTE: 1. Negative undershoot of up to 3.0 V is permitted once per cycle. DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC1 Operating Current 1 tCYCLE = minimum 300 mA ISB1 Standby Current E ≥ VCC – 0.2 V VIN ≥ VCC – 0.2 V or VIN ≤ 0.2 V f = 0 4m A ISB2 Standby Current E ≥ VIH VIN = VIH or VIL 50 mA ILI Input Leakage Current VIN = 0 V to VCC –2 2 µA ILO I/O Leakage Current V IN = 0 V to VCC –2 2 µA VOH Output High Voltage I OH = –4.0 mA 2.4 V VOL Output Low Voltage I OL = 8.0 mA 0.4 V NOTE: 1. ICC is dependent upon output loading and cycle rates. Specified values are with outputs open. CMOS 64K × 18 Static RAM LH521028 4-215
- Capacitances are maximum values at 25oC measured at 1.0 MHz
with VBias = 0 V and VCC = 5.0 V.
- Guaranteed but not tested.
Figure 3. Output Load Circuit
AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) SYMBOL DESCRIPTION –17 –20 –25 –35 UNITS MIN MAX MIN MAX MIN MAX MIN MAX READ CYCLE tRC Read Cycle Timing 17 20 25 35 ns tAA Address Access Time 17 20 25 35 ns tASL Address Setup to Latch Enable 3333n s tAHL Address Hold from Latch Enable 4566n s tLEA Latch Enable to Data Valid 19 22 27 37 ns tLHM Latch Enable High Pulse Width 5566n s tOH Output Hold from Address Change 3555n s tLH Output Hold from Latch High 4777n s tEA E Low to Valid Data 17 20 25 35 ns tELZ E Low to Output Active 2,3 3333n s tEHZ E High to Output High-Z 2,3 10 10 12 20 ns tSA S Low to Valid Data 9 1 01 22 0 n s tSLZ S Low to Output Active 2,3 2233n s tSHZ S High to Output High-Z 2,3 10 10 12 20 ns tGA G Low to Valid Data 8 9 12 20 ns tGLZ G Low to Output Active 2,3 0000n s tGHZ G High to Output High-Z 2,3 8 8 10 20 ns tRCS Read Setup from W High 0000n s tRCH Read Hold from W Low 0000n s tPU E LOW to Power Up Time 3 0000n s tPD E HIGH to Power Down Time 3 17 20 25 35 ns tWA Access Time From Write Enable HIGH 20 25 28 35 ns WRITE CYCLE tWC Write Cycle Time 17 20 25 35 ns tEW E Low to End of Write 13 15 20 30 ns tSW S LOW to End of Write 13 15 20 30 ns tAW Address Valid to End of Write 13 15 20 30 ns tAS Address Setup to Start of Write 0000n s tAH Address Hold from End of Write 0000n s tASL Address Setup to Latch Enable 3333n s tAHL Address Hold from Latch Enable 4566n s tLHW Latch Hold from W High 0000n s tLHM Latch Enable HIGH Pulse Width 5566n s tWP W Pulse Width 13 15 20 30 ns tDW Input Data Setup Time 9 1 21 31 5 n s tDH Input Data Hold Time 0000n s tWHZ W Low to Output High-Z 2,3 8 8 10 14 ns tWLZ W High to Output Active 2,3 3333n s NOTES: 1. AC Electrical Characteristics specified at ‘AC Test Conditions’ levels. 2. Active output to High-Z and High-Z to output active tests specified for a ±500 mV transition from steady state levels into the test load. CLo ad = 5 pF . 3. Guaranteed but not tested. CMOS 64K × 18 Static RAM LH521028 4-217
Figure 6. Read Cycle No. 3
become active as early as tELZ , tSLZ or tGLZ . Figure 7. Read Cycle No. 4
read of the low byte of the memory location. DQ L(0-8) disabled and in a high-impedance mode. able in tSA following SL going LOW. before returning to a high-impedance condition. tSHZ following SL going HIGH. Figure 12. Byte Read (E is LOW and W is HIGH)
shows two write operations with unlatched addresses. W goes LOW while SL and SH remain HIGH. on the lower byte of memory location N. (4) Address N is changed to M. L(0-8) of memory location N+ 1. on the upper byte of address M. (7)W goes HIGH, ending the Write operation. Figure 13. Byte Write (E is LOW)
52-pin, Plastic Leaded Chip Carrier (PLCC52-P-750) LH521028 Device Type U Package - ## Speed 521028MD CMOS 64K x 18 Static RAM Example: LH521028U-25 (CMOS 64K x 18 Static RAM, 25 ns, 52-pin, Plastic Leaded Chip Carrier) Access Time (ns)
ORDERING INFORMATION
DIMENSIONS IN MM (INCHES) 52PLCC (PLCC52-P-750) 52PLCC 19.69 [0.775] 18.67 [0.735] 19.69 [0.775] 18.67 [0.735] 20.57 [0.810] 19.56 [0.770] 20.57 [0.810] 19.56 [0.770] 18.8 [0.740] 17.78 [0.700] 1.27 [0.050] TYP. 0.58 [0.023] 0.33 [0.013] 0.76 [0.030] 1.38 [0.015] 4.06 [0.160] 3.56 [0.140] 0.10 [0.004] 52-pin, 750-mil PLCC PACKAGE DIAGRAM CMOS 64K × 18 Static RAM LH521028 4-225