LH5168 SHARP | Alldatasheet

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SHARP CORP BLE D MM 8180798 0009701 849 mmSRPU L H51 68 CMOS 64K (8K x 8) Static Ram FEATURES DESCRIPTION att The LHS5168 is a static RAM organized as 8,192 x 8 © 8,192 x 8 bit organization bits. It is fabricated using silicon-gate CMOS process A imes: 80/100 ns (MAX. technology. © Access times: ns (MAX.) The LH5168H is designed for wide temperature @ Low-power consumption: range from -40 to +85°C. Operating: PIN CONNECTIONS 303 mW (MAX.) LH5168/D/N @ 80 ns 2aeN oP TOP VIEW 248 mW (MAX.) LH5168/D/N/T/TR: 28-PIN SOP @ 100 ns NL] 1¢ 28} Vec 275 mW (MAX.) LH5168H/HD/HN An 2 27 WE @ 100 ns a,C] 3 2sfce, . Aq 4 2p Standby: Acc] 5 24 Ay 5.5 pW (MAX.) LH5168/D/N/T/TR Ad 6 zbay 16.5 pW (MAX.) LH5168H/HD/HN As] 7 22[0E A.C] 8 21D Ae @ Fully-static operation Ad 9 20fce, AgC]10 192 v0, @ Three-state outputs vo, C11 180, vo,C]12 7DWw, @ Single +5 V power supply vo, 13 160s Gnot|r4 1sPw, e@ TTL compatible /O 168.1 . . Figure 1. Pin Connections for DIP, SK-DIP, e Pin compatible to 64K bit EPROM and SOP Packages @ Wide temp. range available LH5168: -10 to +70°C LH5168H: -40 to +85°C @ Packages: 28-pin, 600-mil DIP 28-pin, 300-mil SK-DIP 28-pin, 450-mil SOP 28-pin, 8 x 13 mm? TSOP (Type !)

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Figure 2. Pin Connections for TSOP Packages

Figure 3. LH5168 Block Diagram

SHARP CORP BLE D MM 6180798 0009704 5538 MESRPJ CMOS 64K (8K x 8) Static RAM LH5168 TRUTH TABLE [| Hot x | x | x J Deselect “[ “High-z | Standby (Isa) [4 [| xf x |x| Deselect | High-z | Standby (Isa) [oe wf x Wite Pin Operating (lec) |] Lot [TT Output disable | High-Z Operating (lec) |_| NOTE: 1. XeHork ABSOLUTE MAXIMUM RATINGS [sacs [omen So | we Supply voltage 0310470 | O3to+70 | v | 1 |

20.510 Voc +05 | -03t0Vec+03 | Vf 1 |

i |__toto+70 | -totoso_ [oT 2 | ati atu Te Oomatnownvenne | oe [eee le Storage temperature | Tstg_ | -S5t0+150 | séwoviso | co | | NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. LH616a/01N 3. LHS16HHDIHN RECOMMENDED OPERATING CONDITIONS (Note 1) | sewwo | a | em ee | | _eananeren | [wn te [wax | win, Tre Tmax. | Supply vottage | Voc | 45 | 50 | 55 | a Te Input voltage Ls 3 [ve [os | foe | os | os Tv} NOTE: 1. Taw -10 to 470°C (LHS168/D/N), Ta = -40 to +85°C (LH5168H/HD/HN). DC CHARACTERISTICS ' (Vcc = 5 V + 10%) [__PaRAmereR [ symeo. | ConpiTions | MIN. | max. [unr | NOTE _| Input leakage current | tu | Vin = 010 Voc ee | CE = Visor CEz= Vi Output leakage ho of OE = Vix or WE = Vi. pA Wo = 0 to Veo CE = Vi. Vin = Vato Vin | tovcue = mA CEe= Vis, Outputs open | 80 ns CEs = Vi, Viv= Vi toVin | tovour = Operating current leo CE2 = Vin, Outputs open 700 ns | SH CE, mA CEs = Vu, Van = 02 Vito 7 Veo -0.2V tovaue = 10 CE2 = Vin, Outputs open hs lise] CEs = Visor CEz = Vi a ee Standby current ~_ CE2<0.2Vor tasvoo [| to | wa 2 CE CEseVec-02V [Tasasc | [30 | wa | 3 | Output voltage | vo [ks etmaA oa [Wow [OO ton=stma aa Pv NOTES: 1. Ta = -10 to 70°C (LH5168/D/N/T/TR), Ta = -40 to +85°C (LH5168H/HD/HN) 2. LHS16Q/D/NTTR 3. LHSTEBHIHDIHN SHARP 3-39

SHARP CORP BLE D MM 8180798 0009705 494 MSRP LH5168 CMOS 64K (8K x 8) Static RAM AC CHARACTERISTICS ' (1) READ CYCLE (Vcc = 5 V + 10%) (ree [oe ae a fr [| ns fn vax | _| [Readcyclo | tec | 0 | | tc | | ts | [Address accesstime [tw | | 80 || 100 Tons P| [erm Pe Pe fe ef} access time [ices | wer | [| ao | | mo [ons [| [Output enabie accesstime [te | | 4 | | 40 [ons [| [Oouputhodime | tw =| to TT to PT ns TO Chip enableto | (ey | ux | to | | to | [ons [ 2 | output intowZ cea | ue | io | | to | [ons | 2 | fegemeene Tee ff [fT Low-Z z Chip enabioto | Ey | wx | 0 | 30 | o | 30 | ms | 2 | output inHigh-Z_ | (cea | wwe | o | 30 | o | 30 [ ms | 2 | lagers foe De Pe Te Te ToT | High-Z NOTES: 1. Ta =-10 to +70°C (LH5168/D/N/T/TR), Ta = ~40 to +85°C (LH5168H/HD/HN) 2. ative output to tigh-mpedance and highimpedance to output active tosis specified for a+500 mV transiton from steady state levels into the test load. CLoap = 5 pF. (2) WRITE CYCLE (Vcc = 5 V + 10%) Se ee [Write cyciotime | two | Sco] | too | | sO [Chip enable to endof wits | tw | 70 | | eo [ns [| [Address validto end ot write | ww | 70 | | a0 [| ns [| [Address seuptme | ots | oo | | Pts [ Write puise width | tw ||| Ts ST [Write recoveytime | wa | o | | o | [ns [| [Data validto endotwrte | tow | = 40 | | | Ts | [Datahoidtime | St ST || Ts ST | Ouiput active trom end otwrte | tow | to | | i | [ ns [ 4 | [WE tooupurinHigh:z | tw | | 0 | oo ns Ts [CE toouputinvighz | tow ~—| = | 20 | of ao ns | NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a +500 mV transition from steady state levels into the test load. CLoxo = 5 pF. AC TEST CONDITIONS [___Parameren [Move | [Input riseftalitime [tne a

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  1. This parameter is sampled and not production tested.

Figure 4. Low Voltage Data Retention

Figure 5. Read Cycle -

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  1. The writing occurs during the overlap (tye) of CE, «'LOW", CE, = "HIGH", and WE = -LOW"
  2. tow is defined as the time trom the last occuring transition, either GE, LOW transition or CE, HIGH transition,

to the time when the writing is finished.

  1. tas is defined as the time from address change to writing start.
  2. tyyq is defined as the time from writing finish to address change. __
  3. If CE, LOW transition or CE, HIGH transition occurs at the same time or after WE LOW transition, the

‘6. While the VO pins are in the output state, input signals with the opposite logic level must not be applied. Figure 6. Write Cycle 1

LH5168 CMOS 64K (8K x 8) Static RAM SHARP CORP BLE D M@®@ 8180798 0009709 O3T MMSRPJ hao Co | (NOTE 4) SN 77) = (WWMM HIM. eS If 7 uw MM UM, LMA WE y we Wi MILL. Door DDS V7 out PITTI reregerrrr rh be XX ton oy 2 (ome XXX OE = "Low" NOTES: — — 4, The writing occurs during the overlap (typ) of CE, ="LOW", CE, = "HIGH", and WE = “LOW”. 2. tow is defined as the time from the last occuring transition, either CE, LOW transition or CE, HIGH transition, to the time when the writing is finished. 3. tag is defined as the time from address change to writing start. 4. tyais defined as the time from writing finish to address change. _ 6. If CE, LOW transition or CE, HIGH transition ocours at the same time or after WE LOW transition, the output will remain high-impedance. — 6. if CE, HIGH transition or CE, LOW transition occurs at the same time or before WE HIGH transition, the ‘output will remain high-impedance. 7. While the V/O pins are in the output state, input signals with the opposite logic level must not be applied. cise Figure 7. Write Cycle 2

ORDERING INFORMATION

—tH5168 OX XH Device Type Operating Package Speed Temperature L200 peces in Blank 28 pin, 600-mil DIP (DIP 28-P-600) D 28-pin, 300-mil SK-DIP (SK-DIP28-P-300) N_ 28-pin, 450-mil SOP (SOP28-P-450) T_28-pin, 8 x 13 mm2 TSOP (Type 1) (TSOP28-P-0813) TR 28-pin, 8 x 13 mm2 TSOP (Type |) Reverse Bend Blank -10 to 70°C (TSOP28-P-0813) H -40 to +85°C CMOS 64K (8K x 8) Static RAM Example: LH5168D-10L (CMOS 64K (8K x 8) Static RAM, 100 ns, 28-pin, 300-mil SK-DIP) sve ee _

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