LH5164A SHARP | Alldatasheet
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Technical content
NOTE: Pin numbers apply to 28-pin DIP, SK-DIP, or SOP. Figure 3. LH5164A/AH Block Diagram
Supply voltage V CC -0.3 to +7.0 -0.3 to +7.0 V 1 Input voltage V IN -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 V 1, 2 Operating temperature Topr -10 to +70 -10 to +70 °C 3 -40 to +85 °C4 Storage temperature Tstg -55 to +150 -55 to +150 °C NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. VIN (MIN.) = -3.0 V for pulse width ≤50 ns. 3. LH5164A/AD/AN/AT 4. LH5164AH/AHD/AHN/AHT RECOMMENDED OPERATING CONDITIONS 1 PARAMETER SYMBOL 80 ns 100 ns UNIT NOTE Input voltage VIH 2.2 V CC + 0.3 2.2 V CC + 0.3 V VIL -0.3 0.8 -0.3 0.8 V 2 NOTES: 1. TA = -10 to +70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT). 2. VIN (MIN.) = -3.0 V for pulse width ≤50 ns. DC CHAR ACTERISTICS 1 (VCC = 5 V ±10%) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input leakage current ILI VIN = 0 to VCC -1.0 1.0 µA Output leakage current ILO CE 1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = 0 to VCC -1.0 1.0 µA Operating current I CC CE 1 = VIL, VIN = VIL or VIH CE 2 = VIH, Outputs open tCYCLE = 80 ns 55 mA CE 1 = VIL, VIN = VIL or VIH CE 2 = VIH, Outputs open tCYCLE = 100 ns mA 50 3 CE 1 = VIL, VIN = 0.2 V or VCC - 0.2 V CE 2 = VIH, Outputs open tCYCLE = 1.0 µs 10 Standby current I SB1 CE 1 = VIH or CE 2 = VIL 5m A CE 2 ≤ 0.2 V or CE 1 ≥ VCC - 0.2 V TA ≤ 70°C 1.0 µA 2, 3, 4 TA ≤ 85°C 3.0 µA 3, 4 Output voltage VOL IOL = 2.1 mA 0.4 V VOH IOH = -1 mA 2.4 V NOTES: 1. TA = -10 to 70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT) 2. LH5164A/AD/AN/AT 3. LH5164AH/AHD/AHN/AHT 4. CE 2 should be ≥ VCC – 0.2 V or ≤ 0.2 V when CE 1 ≥ VCC – 0.2 V CMOS 64K (8K × 8) Static RAM LH 5164A/AH
(1) READ CYCLE (VCC = 5 V ±10%) PARAMETER SYMBOL 80 ns 100 ns UNIT NOTE MIN. MAX. MIN. MAX. Read cycle time t RC 80 100 ns Address access time t AA 80 100 ns Chip enable access time (CE 1)t ACE1 80 100 ns (CE2)t ACE2 80 100 ns Output enable access time t OE 40 40 ns Output hold time t OH 10 10 ns Chip enable to output in Low-Z (CE 1)t LZ1 10 10 ns 1 (CE2)t LZ2 10 10 ns 1 Output enable to output in Low-Z tOLZ 5 5 ns 1 Chip enable to output in High-Z (CE 1)t HZ1 0 30 0 30 ns 1 (CE2)t HZ2 0 30 0 30 ns 1 Output disable to output in High-Z tOHZ 0 20 0 20 ns 1 (2) WRITE CYCLE (VCC = 5 V ±10%) PARAMETER SYMBOL 80 ns 100 ns UNIT NOTE MIN. MAX. MIN. MAX. Write cycle time t WC 80 100 ns Chip enable to end of write t CW 70 80 ns Address valid to end of write t AW 70 80 ns Address setup time t AS 00 n s Write pulse width t WP 60 60 ns Write recovery time t WR 00 n s Data valid to end of write t DW 40 40 ns Data hold time t DH 00 n s Output active from end of write t OW 10 10 ns 2 WE to output in High-Z t WZ 03 003 0 n s2 OE to output in High-Z t OHZ 02 002 0 n s2 NOTES: 1. TA = -10 to +70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT) 2. Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition from steady state levels into the test load. AC TEST CONDITIONS PARAMETER MODE NOTE Input voltage amplitude 0.6 to 2.4 V Input rise/fall time 10 ns Timing reference level 1.5 V Output load conditions 1TTL + C L (100 pF) 1 NOTE: 1. Includes scope and jig capacitance. LH5164A/AH CMOS 64K (8K × 8) Static RAM
CAPACITANCE 1 (TA = 25°C, f = 1 MHz) PARAMETER SYMBOL CONDI TIONS MIN. TYP . MAX. UNIT Input capacitance C IN VIN = 0 V 7 pF Input/output capacitance C I/O VI/O = 0 V 10 pF NOTE: 1. This parameter is sampled and not production tested. DATA RETENTION CHARACTERISTICS 1 PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Data retention voltage V CCDR CE 2 ≤ 0.2 V or CE 1 ≥ VCCDR - 0.2 V 2.0 5.5 V 2 Data retention current I CCDR VCCDR = 3 V, CE 2 ≤ 0.2 V or CE 1 ≥ VCCDR - 0.2 V TA = 25°C 0.2 µA 2, 3 TA = 40°C 0.4 µA 2, 3 0.6 µA 2, 3 VCCDR = 3 V, CE 2 ≤ 0.2 V or CE 1 ≥ VCCDR - 0.2 V TA = 25°C 0.2 µA 2, 4 TA = 70°C 0.6 µA 2, 4 1.5 µA 2, 4 Chip disable to data retention tCDR 0n s Recovery time t R tRC ns 5 NOTES: 1. TA = -10 to +70°C (LH5164A/AD/AN/AT), TA = -40 to +85°C (LH5164AH/AHD/AHN/AHT) 2. CE 2 should be ≥ VCCDR - 0.2 V or ≤ 0.2 V when CE 1 ≥ VCCDR – 0.2 V 3. LH5164A/AD/AN/AT 4. LH5164AH/AHD/AHN/AHT 5. t RC = Read cycle time CMOS 64K (8K × 8) Static RAM LH 5164A/AH
- The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP ).
- tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,
to the time when the writing is finished. AS is defined as the time from address change to writing start.
- tWR is defined as the time from writing finish to address change.
- If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the
outputs will remain high-impedance.
- While I/O pins are in the output state, input signals with the opposite logic level must not be applied.
Figure 6. Write Cycle 1
- The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP ).
- tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,
to the time when the writing is finished. AS is defined as the time from address change to writing start.
- tWR is defined as the time from writing finish to address change.
- If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the
outputs will remain high-impedance.
1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the
outputs will remain high-impedance.
- While I/O pins are in the output state, input signals with the opposite logic level must not be applied.
Figure 7. Write Cycle 2
DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28DIP (DIP028-P-0600) 11 4 1528 28DIP-2 13.45 [0.530] 12.95 [0.510] 0.51 [0.020] MIN. 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] 0.30 [0.012] 0.20 [0.008] DETAIL 36.30 [1.429] 35.70 [1.406] 0° TO 15° 4.50 [0.177] 4.00 [0.157] 15.24 [0.600] TYP. 28-pin, 600-mil DIP 28DIP (DIP028-P-0300) DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 11 4 1528 28DIP-6 7.05 [0.278] 6.65 [0.262] 0.51 [0.02] MIN. 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. 0.56 [0.022] 0.36 [0.014] 0.35 [0.014] 0.15 [0.006] DETAIL 35.00 [1.378] 34.40 [1.354] 0° TO 15° 3.65 [0.144] 3.25 [0.128] 7.62 [0.300] TYP. 28-pin, 300-mil SK-DIP CMOS 64K (8K × 8) Static RAM LH 5164A/AH
DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP (SOP028-P-0450) 12.40 [0.488] 11.60 [0.457] 8.80 [0.346] 8.40 [0.331] 10.60 [0.417] 18.20 [0.717] 17.80 [0.701] 0.15 [0.006] 1.025 [0.040] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.10 [0.004] 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 28 15 141 1.70 [0.067] 1.70 [0.067] 28SOP 28-pin, 450-mil SOP LH5164A/AH CMOS 64K (8K × 8) Static RAM
DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28TSOP (TSOP028-P-0813) 28TSOP 0.28 [0.011] 0.12 [0.005] 0.55 [0.022] TYP. 12.00 [0.472] 11.60 [0.457] 13.70 [0.539] 13.10 [0.516] 8.20 [0.323] 7.80 [0.307] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 12.60 [0.496] 12.20 [0.480] 0.20 [0.008] 0.10 [0.004] 0.20 [0.008] 0.90 [0.035] 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] 0 - 10° DETAIL 0.425 [0.017] 28-pin, 8 × 13 mm2 TSOP (Type I) 10 100 80 80 LH5164A Device Type X Package - ## Speed 5164A-7 CMOS 64K (8K x 8) Static RAM Blank 28 pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil SK-DIP (SK-DIP028-P-0300) N 28-pin, 450-mil SOP (SOP028-P-0450) T 28-pin, 8 x 13 mm
2 TSOP (Type I) (TSOP028-P-0813)
Example: LH5164AD-10L (CMOS 64K (8K x 8) Static RAM, 100 ns, Low-power standby, 28-pin, 300-mil SK-DIP) X Blank -10 to 70°C H -40 to +85°C Operating Temperature Access Time (ns) L Power Low-power standby
ORDERING INFORMATION
CMOS 64K (8K × 8) Static RAM LH 5164A/AH