LH51256L SHARP | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 7

Technical content

Figure 1. Pin Connections for DIP and

0.6 TIT 7] Be encurs eT

Figure 2. LH51256L Block Diagram

[Supply votage | Voc | Oawwo | v | 1 | [| mput vonage | Ww | Ostoe7o |v | | Operating temperature | Topr__| 4010485 | eo || [ Storage temperature | Tag | ssoviso | -c | ‘| NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (Ta = -40 to +85°C) [_—panaweren [seat [wa [we [wax [unt] | Supply voltage | Moo | 45 | 50 | 5s put votage [wa [22 [eso pow | os | | oe Tov DC CHARACTERISTICS (Vcc = 5 V + 10%, Ta = -40 to +85°C) ["_~Faraweren | swwsoi_[~conomons [ww [ We | wax | owt _| Fernmwmenes [| esas || | fomaimnaweres | wor | Sede | > |» | feemomn | | eae [| | [isos [Ev ta CE>Vcc-0.2V Standby current Ta = 0 to +60°C. HA CE 2 Vec-0.2V | rewwse | | fs fm Oupavorege | taste fo [Vor [ows -t0ma_ | 2a ~ AC CHARACTERISTICS {1) READ CYCLE (Vcc = 5 V + 10%, Ta = -40 to +85°C) [cease [ase Tey [ere | SYMBOL UNIT | NOTE fF rannren | enon a | Readcycietime | tec | 00 || tots | | Address access time | tw | Tt || 120 | ns | Chip enable accesstime | tace, =| | 100 || 120 | ns | | Output enabie access time | toe | | 50 | || ns | | Output hoidtime | tow | Ts TO ps | fs | | [OE Low to oupputintowz | toz | 5 [sf me |_| | CE High to outputinHighZ | tw | 0 | 30 | oo | 30 | ms | [OE High oouputintighz | toe | 0 | 90] 0 | 90 | a | 1]

(2) WRITE CYCLE (Vcc = 5 V + 10%, Ta = -40 to +85°C) oe SYMBOL UNIT | CEtowtoendofwrite {| tw | 9 | | too [ [ns | | [ Address validto end of wits | tw | 90 | | too | | ons || [Address sowptime | ws | 8 | | ST | ts [write recoverytime | twa | 15 | | 5 TT [write pulse with | ste =] 0 || sco || ts | [input data setuptime | tow | 30 | | of ns [input data hold time | tow | 10 | | tT Ts [WE High to ouput in High-z [tow | o | [ o [| ns | 4 [WE Low to outputinHigh-z | wz | 0 | a0 | o | 30 | ns | 1 | [CE righ to outpurintighz [to | o | 30 [ o [90 [ons | 1 | NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a +500 mV transition from steady state levels into the test load. CLoap = 5 pF. AC TEST CONDITIONS [_raramerer [Mone [input risenaitime | _—t0ns— fovmainccinaie | wanes edia Output load conditions (Includes scope and jig capacitance) CAPACITANCE ' (Ta = 25°C, f = 1MHz) [input capacitance | Cw | Mw-ov | | | 7 [inpuvioutput capacitance | Co | Wo-ov | [Tt |_| NOTE: 1. This parameter Is sampled and not production tested. DATA RETENTION CHARACTERISTICS (Ta = -40 TO +85°C) [Data retonton votage | Vocon | CE=Vocon-02v | 20] | |v |_| __Vecor = 3.0 V, CE 2 Vccpar - 0.2 V, pA Ta = 0 to +60°C, Vin = 0 to Vecor . eee) | fej | | CE 2 Vecor - 0.2 V, Ta = -40 to 485°C, HA Vin = 0 to Vecor [CE setuptime | toon | | TT ts [CEhodtime | twa | | tw | | | ts Tt NOTE: 1. trc = Read cycle time

Figure 3. Data Retention Characteristics

{NOTE 3) twa (NOTE 4) ve eS We Ww MLL, D, UUERERREEEEEEEEEEE or PITTI TTT TT rr rrr} ‘ow | ton NOTES: — — 1. The write pulse occurs during the overiap (twp) of CE = LOW and WE = LOW. 2. tow is defined as the time from CE LOW transition to the end of writing. 3. tag Is defined as the time from address change to the start of writing. 4. twa is defined as the time from the end of writing to the address change. 5. When the I/O pins are in the output state, input signals with the opposite logic level must not be applied.

i & WMA, MLM (NOTE 4) we NY MLL tw DS Pn T LELETTTT TTT TTT TT Ty tow ton AX oy ote (one YX NOTES: _ __ 1, The write pulse occurs during the overlap (twp) of CE = LOW and WE = LOW. 2. tew is defined as the time from CE LOW transition to the end of writing. 3. tag is defined as the time from address change to the start of writing. 4. twa is defined as the time from the end of writing to the address change. 5. When the VO pins are in the output state, input signals with the opposite logic level must not be applied. 6. lf CE LOW transition occurs at the same time or after WE LOW tansition, the output will remain high-impedance. 7. If CE HIGH transition occurs at the same time or prior to the WE HIGH transition, the output will remain high-impedance. sroseis Figure 6. Write Cycle 2 (OE Low)

ORDERING INFORMATION

LH51256 x - ## Device Type Package Speed |____ta Be Access Time (ns) Blank 28-pin, 600-mil DIP (DIP28-P-600) N 28-pin, 450-mil SOP (SOP28-P-450) CMOS 256K (32K x 8) Static RAM, Low-power standby Example: LH51256N-10L (CMOS 256K (32K x 8) Static RAM, 100 ns, 28-pin, 450-mil SOP) sraseu-7| SSSSSSSSSSSSSSSSSSSSSssSsSSSSSSSSSSSSSSSsSSSssSSssseee | SHARP 3-91