LH0080

LH0080 SHARP | Alldatasheet

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Z80 CPU Central Processing Unit LHO080 ES OE EE ET TT OT L H 0080 Z80 CPU Central Processing Unit @ Description Pin Connections The LHOO80 Z80 CPU (280 CPU for short be- LH0080/LH0080A/LH0080B/LHOO80E low) is a general-purpose 8-bit microprocessor LHOO80H/LHOO80AH fabricated using an N-channel silicon-gate process. A The LHOO80A Z80A, LHOO80B Z80B, LHOO80E Au fa Aw 780E CPU are the high speed version which can An [3g As operate at the 4MHz, 6MHz and 8MHz system As [38] Ax clock, respectively. Avg aq A> Features Aus Ae

1 CLOCK &] [33] As

1. 8-bit parallel processing microprocessor > A 2. N-channel silicon-gate process bE Ay 3. 158 instructions (The instruction of the 8080 Da Ae are included as a subset ; 8080A software com bi Nn patibility is maintained) ae Ea A. 4, 22 registers ec BAe 5. The capability of 3 modes maskable interrupt ». [3 GND and non-maskable interrupt D; [23 RFSH 6. On-chip dynamic memory refresh counter Do fi] AMI 7. Instruction fetch cycle : 1.6 #s(Z80), 1.0 4s p, fej RESET (Z80A), 0.67 ys (Z80B), 0.5 xs (Z80E) int 3 BUSRQ 8. Single +5V power supply and single phase ni & fa WATT clock HALT (i [23] BUSAK 9, All inputs and outputs fully TTL compatible aREG | Faw 10. 40-pin DIP (DIP40-P-600) RD : Tora @ [ai] RD 44-pin QFP (QFP44-P-1010A) 44-pin QF] (QFJ44-P-S650) LH0080M/LHOO80AM LH0080U/LHO080AU/LHO080BU Saagaas aaado [SL] 1121 fed fol fel fa fo} (= [fo fe] Ff Fea a fF NTH GND* ous ns Yi lA, NMI) fa Ais De ‘ FALT [3 Axe pa Fla. | MREQ As oa Ae | TORO [i Az I EA: RD TA ‘a BaAc WRG] [ia] Avo oct FIGND BUSAKE| Laas Pet EARFSH WAIT fa As D, Ls [ay M, BUSRO [Ar Petey RESET NCH As D [2] BUSRQ MAIHIO|S GASH) c)e OD eae fe | zpepet<ee<e Be a | BB eS BE — top view * The GND pins must be connected to the GND level. 284

Z80 CPU Central Processing Unit LHOO80 ig EE TT

Ordering Information

Product 730 CPU | Z80A CPU | Z80BCPU | Z80E CPU Packa Operating Clock frequency 2.5MHz 4MHz 6MHz 8MHz | ee temperature LH0080 LHoog0A | LHOO80B | LHOO80E 0T to +70T 40-pin DIP Model N LHOO8OH™ | LHOO80AH*| | =20T to +85T et No. LHOO3OM | LHOO80AM| ‘pin QFP | _0T to +60C LHOOs0U | LHOO80AU | LHOO8OBU 44-pin QF) | OT to +70T * Hi suffix is a wide temperature spec, packaged in 40.pin DIP. @ Block Diagram System Data Bus ree OOOMOGB Halt State (1) EEEEL Memory Request @-— Input/Output Request @-—| Read Ds Write @-—| 2 Bus Acknowledge -— é Machine Cycle 1 e-—| 4 Instruction lInstruction} Refresh @) a | K—] ALU a é Decoder Register Interrupt Request (16 > Non-Maskable Interrupt o— 5 Wait Q Bas Request o—| “y i [5: Address Bus Interface O-O—-© OQODDOWOIEHLIOISOOIINL Veo GND System SS (+5V) (OV) Clock ‘System Address Bus Pin numbers apply to 40-pin DIP. 285

Z80 CPU Central Processing Unit LHO080 EE EE EE TE TT TT @ Pin Description Signal 7) [ Function AovAus System address bus 3-state | Mi ° ‘Active “Low”. Indicates that the current machine cycle ___| is the OP code fetch cycle of an instruction execution. Active “Low”. Indicates that the address bus holds a MREQ Memory request 3-stateO | valid address for a memory read or memory write op- ee _ _ | eration. Active “Low”. Indicates that the lower 8 bits of the address bus holds a valid 1/0 address for an I/O read TORQ 1/0 request 3-stateO | or write operation. Also generated concurrently with MI during an interrupt acknowledge cycle to indicate an interrupt response. wD Active “Low”. Indicates that the CPU wants to read data from memory or an /O device, _ Active “Low”. indicates that the CPU data bus holds WR Memory write 3-state O valid data to be stored at the addressed memory or 1/0 ne Active “Low”. Indicates that the lower 7 bits of the sys- ne tem address bus can be used as a refresh address to the RESH Refresh ° system’s dynamic memories. Together with MREQ at “Low”. Active “Low”. Indicates that a Halt instruction is being HAUT Hatt state executed. While halted, the CPU executes NOPs to main: tain memory refresh, The Halt state is cleared with RE SET, NMI, or INT (when allowed), Active “Low”, Indicates to the CPU that the addressed Wart Wait memory or I/O devices are not ready for a data transfer. ‘The CPU continues to enter a wait state as long as this ee signal is active. Active “Low”. Generated by I/O devices. The CPU hon- — Maskable interrupt i INT ors a request at the end of the current instruction if the request interrupt enable flip-flop is enabled. Active “Low”, Has a higher priority than INT. Always _ Non-maskable recognized at the end of the current instruction, inde NMI interrupt request pendent of the status of the interrupt enable flip-flop. Automatically forces the 280 CPU to restart at location Active “Low”. Resets the interrupt enable flip-flop, the RESET Reset program counter interrupt vector register and the mem- ory refresh register, and sets the interrupt status to ee Mode 0, in order to initialize the CPU. Active “Low”. Has a higher priority than NMI. Always — recognized at the end of the current machine cycle. Acti BUSRQ Bus request vated to allow a bus master other than the CPU to con- trol the system bus, BUSAK | sus atoowieiee | Active “Low”. Indicates to the requesting device that the external circuitry can control the system bus. CLOCK [ System clock | SE |_ Inputs + 5V single-phase clock. 286

Z80 CPU Central Processing Unit LHO080 SS ST ET OT TT @ Absolute Maximum Ratings Parameter Symbol Ratings _ Unit | Note Input voltage Vin —0.3 to +7.0 v Output voltage =0.3 to +7.0 Operating temperature c 2 Storage temperature =65 to +150 Note 1: 40-pin DIP and 44-pin QF) Note 2: 44-pin QFP Note 3: 40-pin DIP with wide temperature spec. Standard Test Conditions The characteristics below apply for the follow- All ac parameters assume a load capacitance of ing standard test conditions, unless otherwise 100 pF. Add 10 ns delay for each 50 pF increase noted. All voltages are referenced to GND (OV). in load up to a maximum of 200 pF for the data Positive current flows into the referenced pin. bus and 100 pF for address and control lines. @ DC Characteristics (Vec=5V 5%, Ta=0 to +7008" 1 Parameter Symbol Conditions | MIN. | TYP. MAX. | Unit ~ Clock input low voltage Vue _ —__ | -0.3 045 1 V Clock input high voltage Vin _ _ Vec—0.6) Vec+0.3] Vi ~ Input low voltage Vu _ —0.3 08 Vv Input high voltage Vin 20 | | Vec | Vv Output low voltage Vor Toy = L.8mA, | | o4 [ Vv ~ Output high voltage Vou lou= = 250 vA ee ee | toad | [50 | ma sumpti tnoosoa | || 200 | ma = Current consumption lee tuoo80B || 200] ma = Input leakage current | ul | 0SVinSVcc i 10 BA 3-state output leakage Vem | Vour=0AV to Voc | 10 | pa current in float Note 1: Ta=0 to +60T for 44-pin QFP Ta=—20 to +85 for 40-pin DIP with wide temperature spec. ™@ Capacitance (f=1MHz, Ta=25T) _ Parameter ‘Symbol Conditions MIN. Unit Clock capacitance Ccvock | nmeasured pins returned | 3s Lee Input capacitance to ground | re es Output capacitance s a es : EY ce SPN FLD ee | 287

Z80 CPU Central Processing Unit LHOO80 EE EE EE EE ES EE ™@ AC Characteristics (Voc=5V +5%, Ta=0 to +70T%" ') 1_| Clock eycle time Te aoo%| | 250%) ess] fags" [ns 2_| Clock pulse width (High) | twcn[iso* | rn0*| ea) ns 3. [Clock pulse width (Low) |__| 180 [2000 | 110 [2000 | 65 [2000 | 55 [2000 | ns 5_| Clock rise time [re [so | so [ao PY to Ts 6 [Clock fo address valid delay | Tacriay | [ras | | mo} | 90 | | 80 | as 7_[ Addreess valid to MREQ | delay | TaA cwREQH | i25*| | 65% | 35% | 20%} ns & [Clock LMREQLaclay | Tacrawrean| | 100) | as| | 70, | 60 | ns 9 | Clock fto MREQTdelay | TéCr (MREQr)| 100 | (85 || 70 60 | ns 10_| MREQ pulse width (High) TwMREQh | 170*| [10% ___| 65" 45” ns 11_| MREQ pulse width (Low) _ | TwMREQi_| 360° 220° 135*| | 100"| | ns _12 [Clock 4 to MREQT delay Tactmrpen| | oo [fas | 70 [| 60 | os 13 | Clock 4 to RD 4 delay [ racrepy | [130] | 95 | | go | | 70} as 14 [Clock Pt RD Tdelay |“ TUCr RDN) | | too || a5 | To [| Go [as 15 [Data setup timetoclockt | —Tsdcr) | So] | asf [ 3o{ | 30] | ns

16 Taped) | of | of | of ot | as

17 tewaircp| 70 | | 70) | eof { 50] | os 18 | WAIT hold time after clock) | Tawarrcp | o| | oj) | ot | o| ns 19 [Clock Tto MI ddelay | Tacremay | {130 [| 100 80 70 | ns

20 TaCr (Mir) || 130 | | 100° _80 _70 | as

21 | Clock tto RFSH | delay | T4Cr (RFSHf) | 180 | 130 110 95 | ns ~ 22 | Clock tto RFSH tdelay ___| TaCr (RFSHr) 150 120[ [100 | | 85] os 23 | Clock ¢ to RD f delay Tact (RDr) [fof | se fro ff sof ns 24 | Clock 1to RD } delay j tacrepp | | too [fas fot ns Data Setup to clock 1 during | 26 | Address stable prior to FORQL | TAA GORA | 320% | iso*| [0% | 75%) ns 27 [Clock TORQ tdelay | Tacraoran| | sof | 7s { [ss | | 55 | ns 28 [Clock }to 1ORQt delay ‘| Tacraorar) | | so |_| ss | | 70 | ns 30 | Clock | WR | delay Tactwry | | 90] | ao) | 70] “as 31_| WR pulse width TwWR | 360* 220°| 135” 100" ns 32 [Clock Ito WRTdelay | ‘TaCr (Rr) |_| 100 wot | 7} | a | as 34 | Clock t to WRI delay | 65] | eo} 55 | os 35 [Data stable from WRT | ‘TowRr(D) | 120°[ | 60%] | 0%] | as*| as 36 [Clock }toHALTYors | TacratT)| | 300 | | soo |_| 260 |_| 225 | as 37 [| NMI pulse wigh ———*(|— Twn | 80] | sof [ot | go] | as 38 | BUSREQ setup time to cock? | TsBuSRaH| so[ | so] | sof | 40 | ns 39 | BUSREQ hold time after clock t [TaBUSRaICH)| 9 | | of | of [ o| | as 40 | Clock Tto BUSACK J delay | TaCr ausaxy |_| 120 |__| 100 90 80 | ns _ 41_| Clock }to BUSACK Tdelay | TACE(BUSAKr) |__| 110 | 100 90 80 | ns “42 | Clock tto data float delay _—|_‘TaCr (Dz) i= | 90 90 80 70 | ns Clock f to control output float | 4 delay (MREQ, IORG, RD, and WR) TdCr (CT2) | 110 80 L| | 60 | ns 44 | Clock fto address float delay _[ Tacr(a) | [tio | | 90) feof 70] as MREQT, IORQT, RD and WR A A ee ls

1 Rising edge, | Falling edge

Note 1: Ta=0 to +60T for 44-pin QFP. Ta=—20 to +85T for 40-pin DIP with wide temperature spec. 288

Z80 CPU Central Processing Unit LHO0080 EE EE ET OE ET TT 46 [RESET Ito clock t setup time |TsRESET (CH) 90 | | 6o | | eof [a5 [| ns 47 | RESET from clock! Thotd time [THRESET CH] oO | | of [0 of [as 48 | INT to clock t setup time TsINTECH | 80 | | 80] | 70 55) | ns 49 | INT from clock f hold time | ThINTr (Cr) _ of 0) 0 _o] | as 50 | MI} to TORQ} delay | TAME GORQH| 920°) 565*| __ | 365° 270* as 51_| Clockk | to IORQ t delay _TACF (ORQP) 110 85 60 | as 52 | Clock f to [ORQ t delay racrdorar)| |, too) | as | | 70 | 60 | as 53 [Clock $todata valid delay | Tact) | | 230 [Tso] [so Tf is | ns All ac parameters assume a load capacitance of 100 pF. Add 10 ps delay for each 50 pF increase in load up to a maximum of 200 +5V. pF for the data bus and 100 pF for address and control lines. *For clock periods other than the minimums shown in the table, Ontput pi : calculate parameters using the following expressions. put pin o- 100pF I 250 uA Footnotes to AC Characteristics No.] _ Symbol THOO8O | —SLHOUSOA THOO80B THOO80E “1 tec | twch Two C+ TC | TwCh+ Tw + TC+TIC | TwOht TwCl+ THC+ TIC TwCh+TwC14 TrC+ TIC 2] TwCh _| MAX. 200 us ' MAX. 200 ys MAX. 200 xs MAX. 200 4s 7 | TAA (MREQH| TwCh+TiC—75 TwCh+TiC—65, TwCh+ TiC —50 TwCh+TiC~45 TO TwMREQH | Twoh+TIC—30__|Tweh-rTIC= 20 | TwCh#T1C=20 | Twon+ T1C—20

11 TeC—40 TeC=30 TeC—30 TeC—25

26 TeC— 80 TeC=70 TeC=50

29| Tad (wry |TecC—210 tC 170 | P1410 TeC=120 atl twWR "| TeC—40 T= 30 THO em 25

38 Tw TIC= 14 | Tw} T= TAO Two THC 120

35| TaWRr (D) | TwCI+Trc—80 | TwCl+TrC—70 | TwCltTrC—55__| TwCl+ TrC—50 45| TdCTr(A) |TwCl+Trc—40 | TwCl+TrC—50__| Tw + TrC—50 TwCl+ TrC—45 “50 | Tamir dORQA | 2Tch+TwCh+ TC—80| 2TeC+TwCh+TIC—65 | 2PeC+TwCh+TiC— 50) 2TeC+TwCht TICS (5: AC Test Conditions : Vu=2.0V Vie =Vec—0.6V Von=2.0V FLOAT=+0.5 Va=0.8V — Vuc=0.45V Vo=0.8V ee GHARP Oe oe eee ee 289

280 CPU Central Processing Unit LH0080

CPU Timing (1) Instruction Opcode Fetch The Z80 CPU executes instructions by proceed- The CPU places the contents of the Program ing through a specific sequence of operations: Counter (PC) on the address bus at the start of the bd Memory read or write cycle (Fig. 1). Approximately one-half clock cycle Cc etevice read of wine later, MREQ goes active. When active, RD indicates interrupt acknowledge that the memory data can be enabled onto the CPU The basic clock period is referred to as a T time data bus, or cycle, and three or more T cycles make up a The CPU samples the WAIT input with the fall- machine cycle (M1, M2 or M3 for instance). ing edge of clock state T., During clock states T: Machine cycles can be extended either by the CPU and T, of an MI cycle dynamic RAM refresh can automatically inserting one or more Wait states or occur while the CPU starts decoding and executing by the insertion of one or more Wait states by the the instruction. When the Refresh Control signal user. becomes active, refreshing of dynamic memory can take place. Th Te Tw Ts Ts CLOCK i | KH Ao-As | A Adress TI | TT OF Refresh address _[) fea oll oe A He i : | Ce oH | wart [7 ara { ® @ | wi 4 ® DoD; CK GaldaanK RFSH Note: Tx-Wait cycle added when necessary for slow ancilliary devices. Fig. 1 Instruction opcode fetch (2) Memory Read or Write Cycles (3) Input or Output Cycles Fig. 2 shows the timing of memory read or write Fig. 3 shows the timing for an I/O read or I/O cycles other than_an opcode fetch (M1) cycle. write operation, The MREQ and RD signals function exactly as in During I/O operations, the CPU automatically in- the fetch cycle. In a memory write cycle, MREQ serts a single wait state (T.). This extra wait state also becomes active when the address bus is stable. allows sufficient time for an 1/O port to decode the ‘The WR line is active when the data bus is stable, address from the port address lines. so that it can be used directly as an R/W pulse to most semiconductor memories. ——_— SHARP 290

Z80 CPU Central Processing Unit LHOO80 EE EE EE TT TT Tr Te Tw Ts CLOCK \\ ‘ ke 6 fl | { ® MREQ | @ | Warr eee fj | @ - ( aD | 1 -—— Read operation TO | @ Hy cy a <<< CL sta @ _ ——a— Wk a j /- Write operation 8 a—| & (Por “~~ Data out > = Fig. 2. Memory read or write cycles 5: ——_— SHARP eee eee eee ee 291

2Z80 CPU Central Processing Unit LHO080 ee el Tz Tw" Tw Ts CLOCK \\ f \\ fe, Fe AeA [Walid power adress Tt eH TORQ | [| i H iF ia _ PET ofl ® || pw WAIT PS tt = i to [° “IA RD i rar 1/0 read operation Ke ES |] ‘ DoD; + cK 7 ko @ Valid data +a WR |_| @ 1/0 write operation. 8 <@ & faa Note : Tw=One wait cycle automatically inserted by CPU. Fig. 3 Input or output (4) Interrupt request/acknowledge cycle cle, IORQ becomes active (instead of MREQ) to indi The CPU samples the interrupt signal with the cate that the interrupting device can place an 8-bit rising edge of the last clock at the end of any in- vector on the data bus. The CPU automatically struction (Fig. 4). When an interrupt is accepted, a adds two wait states to this cycle. special M1 cycle is generated. During this M1 cy Th T Te Tw Tw Ts Tw CLOCK J \\ J i ew INT AorAas [Address [TT TT _ Ps e Tora yl f __ din Wait ee Sa A L}-@ 8 8 Dy-D; CK — Note1: Ti =Last state of previous instruction Note 2: Two wait cycles automatically inserted by CPU (*). Fig. 4 Interrupt request/acknowledge cycle 292

Z80 CPU Central Processing Unit LHO080 a EE EE EE ST aT (5) Non-maskable interrupt request cycle mal instruction fetch except that data put on the . bus by the memory is ignored. The CPU instead ex __NMI is sampled at the same time as the maskable ecutes a restart (RST) operation and jumps to the interrupt INT but hashigher priority and cannot be NMI service routine located at address 0066H disabled under software control. (Fig. 5). The subsequent timing is similar to that of a nor- Last T time] Ty T? Ts Ts Ts CLOCK ! | el | ©. iG bars {iitres _| {Bares aires [| wi a =| | Sp — 8) — | MREQ { ae te RD RFSH “Although NN is an asynchronous input, to guarantee its being recognized on the following machine cycle, NMI's falling edge must occur no later than rising edge of the clock cycle preceding Fig. 5 Non-maskable interrupt request operation (5: (6) Bus request/acknowledge cycle (7) Reset cycle = The CPU samples BUSREQ with the rising edge RESET must be active for at least three clock cy of the last clock period of any machine cycle (Fig. cles for the CPU to properly accept it. As long as 6). If BUSREQ is active, the CPU sets its address, RESET remains active, the address and data buses data, and MREQ, IORQ, RD, and WR lines to a float, and the control outputs are inactive. Once high-impedance state with the rising edge of the RESET goes inactive, three internal T cycles are next clock pulse. At that time, any external device consumed before the CPU resumes normal proces- can take control of these lines, usually to transfer sing operation. RESET clears the PC register, so data between memory and 1/O devices. the first opcode fetch will be location 0000 (Fig. 8). — SHARP eo 293

280 CPU Central Processing Unit LHO080

Te Tx Tx Tx qT. CLOCK | +e | — $ a4 BUSRQ XK t +o +e BUSAK | | +Or— +@ Ards a eee oe B+ 0 a MREQ —. Float RD.WR i 1H TORQ : i Ba ope RFSH | HALT Unchanged Note: T.=Last state of any M cycle. Tx=An arbitrary clock cycle used by requesting device. Fig.6 Z-bus request/acknowledge cycle M oc 2 1 Ta Tr Ty Ts Th qT) T CLOCK aa ® HALT 4 HALT instruction received ® Note: INT will also force a Halt exit. Fig. 7 Halt acknowledge cycle a a a ee ee GHAR ee 294

Z80 CPU Central Processing Unit LHOO80 A SE EE EY TS SS ST {m1 | tT Te CLOCK | —4@ art? RESET | @ slo Float | AoAis ———4 Float Do-D; B+< MI ] MREQ. RD. WR. TTT. 7 7, 7 iN TORQ. RFSH, BUSAK. HALT Fig.8 Reset cycle Tr Te T =— crock — LS LS LS Le [B: in ns = RESET ——\\ Fig. 9 Timing diagram when M1 cycle has no wait state 295

Z80 CPU Central Processing Unit LHOO080 EE ET TT <Reference> The RAM contents may be adversely affected by {2) A walt state in the M1 cycle resetting the CPU while it is in operation. Input a RESET signal to start sampling this sig- To prevent this, a RESET signal should be input nal at the clock rising in the M1 cycle’s Ts state. in the following timings. (See Fig. 10.) (1) No walt_state in the M1 cycle Input a RESET signal to start sampling this sig nal at the clock rising in the M1 cycle’s T: state. (See Fig. 9.) T T Tr Ts cLock a BRE a Fig. 10 Reset circuit and timing diagram when | Mi cycle has a wait state — SHARP 296

Z80 CPU Central Processing Unit LHO0080 EE ET TE ET @ CPU Registers ‘A Accumulator | ___F Flag Register {__HGeneral Purpose L General Purpose L’ General Purpose SP Stack pointer PC Program Counter 86 tits —— @ Architecture (1) CPU Registers (v) Refresh Register (R) The built-in re- (i) Program Counter (PC) The program fresh register provides user-transparent dynamic counter holds the 16 bits memory address of a cur- memory refresh. Its lower 7 bits are automatically rent instruction. The CPU fetches the contents incremented during each instruction fetch cycle. from memory address specified by the PC. While the CPU records a fetched instruction and The PC feeds the data to the address line, auto- executes the instruction, the refresh register data matically setting the PC value to +1. When a prog: are placed on the address bus by a REFRESH con- ram jump takes place, a new value is directly set to trol signal. the PC. (vi) Accumulator and Flag Register (A & F) (ii) Stack Pointer (SP) The stack pointer The CPU has also two independent 8-bit accu- holds the top 16-bit address of the stack with an mulators in combination with two 8-bit flag regis- = external RAM, An external file is based on LIFO ters. B= (Last-In, First-Out). The accumulators store an operand or the re- = The data are transferred between a CPU-speci sults of an 8-bit operation. The flag registers, on — fied register and the stack by a PUSH or POP in- the other hand, deal with the results of an 8-bit or struction. The last-pushed data are first popped 16-bit operation; for example, seeing if the result from the stack. is equal to 0 or not. (ii) index Register (IX & IY) — For index (vi) General-Purpose Registers There are mode addressing, there are independent index reg- several pairs of general-purpose registers. In each isters IX and 1Y, each of which holds 16-bit refer pair, they can be used separately or as a 16-bit ence address. paired register. The paired registers are BC, DE, In the index mode, the index registers are used to HL, as well as BC’ DE’ HL’. Either of these sets can designate the memory area for data input/output. work by an “Exchange” instruction at any time on With an INDEX ADDRESSING instruction, an a program. effective address comes by adding a one-byte dis (2) Arithmetic/Logical Unit (ALU) placement to the register content. This displace- ment is an integral signed two's complement num ‘An 8-bit arithmetic/logical operation instruction ber is executed by the ALU inside the CPU. The ALU (iv) Interrupt Register (I) The Z80 CPU has connects to each register through the internal bus indirect subroutine call mode for any memory area for data transfer between them, according to an interrupt. For this purpose, this register stores the upper 8 bits of memory address (3) Instruction Register, CPU Control | for vectored interrupt processing and the lower 8 Each instruction is read out of the memory, held ) bits for the interrupting device. in the instruction register, and decoded. The con- | 297

Z80 CPU Central Processing Unit LHO0080 EE OS OE SE EE ET SY A trol unit controls this action and gives control sig- vice places an instruction on the data bus. This is a nals necessary to read and write data from and to Restart instruction or a Call instruction, the registers. (i) Mode 1 Interrupt Operation. _ Mode 1 The control unit also makes ALU control signal operation is very similar to that for the NMI. The and other external control signals. principal difference is that the Mode 1 interrupt <Interrupts : General Operation? The Z80 CPU has a restart location of 0038H only. accepts two interrupt input signals: NMI and INT. (iii) Mode 2 Interrupt Operation. This in- The NMI is a non-maskable interrupt and has the terrupt mode has been designed to utilize most highest priority. INT is a lower priority interrupt effectively the capabilities of the 280 microp- and it requires that interrupts be enabled in soft- rocessor and its associated peripheral family. The ware in order to operate. interrupting peripheral device selects the starting address (16 bits) of the interrupt service routine. It (1) Non-Maskable interrupt (NMI) does this by placing an 8-bit vector on the data The non-maskable interrupt will be accepted at bus during the interrupt acknowledge cycle. The all times by the CPU. CPU forms a pointer using this byte as the lower After recognition of the NMI signal, the CPU 8-bits and the contents of the I register as the up- jumps to restart location O066H. per 8-bits. This points to an entry in a table of —_ addresses for interrupt service routines, The CPU (2) Maskable Interrupt (INT) then jumps to the routine at that address. The maskable interrupt, INT, has three prog. All the Z80 peripheral devices have the inter- rammable response modes available, rupt priority circuit with a daisy-chain configura- (i) Mode 0 Interrupt Operation. This tion. During an interrupt acknowledge cycle, vec mode is similar to the 8080A microprocessor in- tors are automatically fed. For more details, refer terrupt service procedures. The interrupting de to the Z80 PIO description. a Pointer “ tw Id] From application device I register contents To the beginning of service rotine Fig. 1 Mode 2 interrupt diagram ——— SHARP 298

Z80 CPU Central Processing Unit LHOO80 EE ET EE TT TT TT @ instruction Set Table 1 8-bit load group Mnemonic Flags No. of | No.of | No. of Comments operation [76 543 210| (Basic)| C | Z [rv] S | N |W | Bytes MCycles|T States] _tDr rer ol r| 40+ @,e@jejeleje/ i 1 eee LDr,n [2 00 r 110 alk ele “le 2,2)7 -~a > nr Reg. “ion dil) | rl) jor, Wo; 46+ @lelelejele| 1 [2 [7 | 0 B LDr, (X+d)) r—(X+d) 11 011 101] pp [ele 3 | 5 | 19 001 c ol r 10] 46+ | 010 D -~ ao ou E LDr, (Y+a)| r-(IY+d) | 11 111 101| FD | @ 3 5 19 100 H o1 r 10} 46 101 L -~a- ul A LD (HL), or 0 r| 70+le 1/2 |7 LD(X+@, 1] (X+der [11 ou ior] pp Te 3 [5 | 19 | 01 110 Fr 70 | — — —t + : -— as | - n= LD (IX+d), n| (IX+d)e-n 11 O11 101| DD e ee 4 5 19 00 110 110| 36 | -a- | | LD(Y+4),a d¥+den | 11 111 101} FD | @ ele 4 | 5 | 19 00 110 110] 36 -~ da -> | = nit 5= LD A, (BC) [A + (BC) ox Jeleleletefefi | 27) = LDA (DE) | AW (De) [00 o11 10 | 1A_[elelelefelef a fat 7 | LD A, (nn) A+ (nn) 00 111 010; 3A 3 13 “ao -ao- LD (BQ), A lefelefe/ it 2t7 LD(nm), A) (on) A [00 110 O10 32 @ 3] 4 [13 LDA,I Avl 11 101 101] ED $10 2 | 2 nooner tt tte | | 01 oll 111 | SF een Te Tomine PELL? |? | 01 000 111 | 47 eer ee ERT EPL 1 oo1 uit] 4F Notes ; r, r’ means any of the registers A, B,C, D, E, H, L, IFF the content of the interrupt enable flip-flop, (IFF) is copied into the P/V flag. Flags : C (carry), Z (zero), S (sign), P/V (parity/overflow), H (half carry), N (add/substract). : @=unchanged, O=reset, 1 =set, X=undefined. + set or reset according to the result of the operation. ee ee SHARP OO OOO eee eee 299

Z80 CPU Central Processing Unit LHO0080 EE TE EE OE TS ST Table 2 16-bit load group Mnemonic Symbolic |__OP code [HEX code No.of ] No.of | No.of Comments nemo operation [76 543 210| (Basic) | C |Z [Pv] S Bytes |M Cycles] T States meen LDdd,nn | ddan | 00 ddO 001) 01+ "|| ele rey | 3 | pameranees “1 = dd Reg. LD IX, on IX = an 11 011 101) DD 00 BC 00 100 001} 21 o. | DE — jf a sl 10 | HL LD IY, on Yeon 11 111 101] FD 4 14 il sP 00 100 001 | 21 “ao ee eo . LD HL, (an) | H = (nn+1)/ 00 101 010] 2A 3 | 5 | 16 jnn: 2-byte number. L + (nn) - ra Lower byte just con after opcode. LD dd, (nn) ddx = (nnt+1)) 11 101 101) ED ele 20 | Upper byte comes dd (nn) 01 ddl O11) 4B+ } next. -—-a0 - on maa 7 tt _ LD IX, (nn) [Xe = (an+1)! 11 O11 voi | DD ele 4 20 IX: = (an) | 00 101 010} 2A | -~ na | ~ ~ 9 4 _| LDIY, (nn) [Ye = (ant] 1) 111 101] FD ee 4 20 Ti (an) | 00 101 010; 2A -~ a] LD (nn), HL | (nn+1) =H] 00 100 010; 22 3] 5 (an) Lo} on > LD (nn), dd (nn+1) = ddw| 11 101 101] ED 4 20 (an) dds | O1 dadO O11) 43+ pares “a= LD (nn), IX (on+1)-1Xe | 11 O11 101} DD 4 20 (an) 1X. | 00 100 010} 22 -—1-a- -— 2 LD (nn), fY | (antijlye [11 111 101) FD 20 -_-a- “a _ LD SP,HL_| SP—HL | 11 111 001] F9 [e| 1 6 Lpsp,Ix | SP=ix [11 011 101] DD 2 10 1111) oo1| F9 LDsp,ly | Sp=ly |i 111 101] FD 2 11111 001] F9 (SP— Hage aa Reg. PUSH IX (P=2)-IX. | 11 O11 101] DD 2 15 00 BC (SP—1)-IXe | 11 100 101 | E5 ol DE PUSH IY (SP—2)1¥. | 11 111 101] FD 2 15 10 HL ee (GP=Ht¥u | 11 100 101 | ES ton AP POP aq qax + (SP+1)/ 11 qqd 001) Cr+ [*[°| 1 10 ga. + (SP) POP IX IXw-(SP+1) | 11 O11 101 2 14 POP IY Tye (SP+1)] 11 111 101] FD 2 Notes: dd is any of the register pairs BC, DE, HL, SP. qq is any of the register pairs AF, BC, DE, HL. (PAIR)«, (PAIR). refer to high order and low order eight bits of the register pair respectively, e.g, BCc=C, AFH=A. Flags: @ unchanged, 0=reset, 1 =set, X=undefined, $ =set or reset according to the result of the operation —— SHARP 300

Z80 CPU Central Processing Unit LHO080 EE EE TE ET TS Table 3 Exchange, block transfer, block search groups a _operation _|76 543 210] (Basic) Zz | H_| Bytes _[M Cycles|T States ° EX DE,HL | DE++HL | 11 101 011) EB elefelefe; i fi lal TEXAF.AP | AP=> AP [00001 000[ 08 [elejelefeje/ i |i [a4 | EXX BC, BC, | 11 011 001| D9 efit Register bank and DE|++|DE'| | | auxiliary register HL} \\HL} | bank exchange L (SP) | ee EX (SP), IX | 1Xw+*(SP+1) 11 011 101] DD. [| ele | ej) 2 | 6 | 23 EX (SP), IY Wee SP+i} 1 11 101] FD ele | ej; 2 | 6 | 23 | te SP) amet B LDI (DE) = (HL) | 11 101 101 | ED ejt 0! 2 | 4 | 16 | Load dL) into (DE), DE+DE+1 | 10 100 000) AO i i | increment the poin- HL = HL+1 ters and decrement BC + BC~1 | the byte counter (BO) LDIR (DE) = (HL) [11 101 101] ED [@|ejo of 2, 5 | 21 |Bc#o DE*DE+1 | 10 110 000, BO | | BL =~ HL+1 BC+ BC—1 | ee WBC=Oend) | [oT a [6 [irec=o LDD (DE) = (HL) | 11 101 101] ED | @ of 0) 2/4 | 16 DE*DE-1 | 10 101 000] A8 ® | ee BC + BC—1 LDDR (DE) = (HL) | 11 101 101] ED WBC#O DE*DE-1 | 10 111 000) B8 HL = HL~1 = BC + BC—1 _ 5: ie [wec=0 «| WE CPI A~ (HL) 11 101 101) ED }@) | ¢t 16 HL + HL+1) 10 100 001] Al QO [| pce se-1) 7 CPIR A—(Hl) | il 101 101) ED je] t|t 21 |1fBC#0 and HL -HL+1] 10 110 001) BI @'0 A#(HL) BC + BC—1 IfA= (HL or a If BC=0 or BC=0 end A= (HL) cPD A- (HL) 11 101 101) ED t rit} 2 4 16 HL = HL~1) 10 101 001| A9 ® | BC + BC=1 a CPDR A~ (HL) 11101 101) ED |@|ty)t 1) t) 2 5 21 | If BC#0 and HL += HL—1j 10 111 001] B9 @\\o | A#(HL) BC + BC—1J | __ Tf A= (HL) or | 2 | 4 | 16 | if BC=0 or BC=0 end i A= (HL) Note: @P/V flag is 0 if the result of BC=0, otherwise P/V=1 @2Z flag is 1 if A= (HL), otherwise Z=0 Flags: @ = unchanged 0 = set, 1 = reset t = set or reset according to the result of the operation 301

280 CPU Central Processing Unit LHO0080

Table 4 8-bit arithmetic and logical group Mnemonic | S¥mbolic [_OP code [HEX code Flags__ No. of | No.of | No.of Comment une _operation [76 543 210] Basic) | C | Z [pv| s [N Bytes |M Cycles) T States iments ADDAr | AwAtr [10 k +r] 80+/t|t]v{t]o italy, Reg -~ a 001 c ADDA,GL)| AT AFL) [tok mol ser [el sivisfolet a Tet 7) oy] 5 ADDA.(X+d | AWA+(X+A) 11 O11 101] DD | ¢ Vv 3 ou E | 10 k uo 86+ | 100 Hl —_a - 101 L ADDA.(Y+d | ATA+AY+A] 11 111 101] FD | ¢ v 3) 5 [19] yy A i 10 k 110) 86+ -~a- Mnemonic | _k ADC A, s At AtstC ‘types ut vit ADD 000 SUB s Aw Ass | Oo sig tvia late apc | 001 SBC A, s Aw Ans=C | eon reiti{v[t lilt) jm) je] jer] SUB | 010 "AND s IS ee op P[tlolil b 7 SBC | oul ORs jrasavs |or pltjojo| fi |i |i AND | 100 ORs insracton | Tofstet store) | | ho or | 0 crs fee Games aca KanSEOES xor | 101 ier feeeti joo + ¢} oorielt}vi[tjoit; i ja) 4) ce fa inci | curr foo toe} sot felt {vi[ slot +] a [3] at |s=rn (Hb, INC (IX+d) | (X+d)*- ] 11 011 101] DD | @ vitlo|t) 3 23 (IX+d), (IY +d) Inc d¥+¢) | (¥+a— Jil tii 101] FD Je vitioit} 3 23 | Mnemonic | ¢ -~4a- pec | 101 DEC m mem—1 | 4uypes Vv val ype] wee available 1 ys hy | mee based on 3 lle | fg | Xte arta the above INC 5 tle lbs instruction Note: V and P mean overflow and parity, respectively. w1:depends on s. Flags: @=unchanged 2: depends on m. O=reset 1=set X=undefined + =set or reset according to the result of the operation —[$— SHARP 302

Z80 CPU Central Processing Unit LH0080 EE OE EE OE EE TE TT Table 5 General purpose arithmetic and CPU control groups Mnemonic Symbolic | OP code | HEX code __ Flags No.of Comments an operation [76 543 210| (Basic) | C | Z [ev] S| N | H | Bytes M Cycles,T States DAA Decimal 00 100 111} 27 | ¢ a0 t t, 1 | 2 | 4 | Decimal adjust adjustment | | | accumulator. (add/subtract) | i i CPL ATA 00 101 111) 2F 1 L 4 Complement (one's complement). _ 01.000 100 | 44 |__| two's complement). ccr cHc oo mi ii| 3F | | X{ 1 | 1 | 4 | Complement carry flag. _ SCF CcH1 00 110 111] 37 ofa fa =act carry flag. “NOP ___|_Nooperation| 00 000 000| 00 e -ijil4 HALT | CPU halted | 01 110 110} 76 felefe/i fifa) _ol IFF — 0 110 ou] F3_[elelelelele| 1 | 1 | 4 | interrupt not enable Hf FF~1 juimoul[ re [eleleveleleol i [i 1 4 | tmerrupt enable IMO Set interrupt] 11 101 101 eee 2 2 | 8 | Set interrupt mode. mode 0 01 000 110) 46 | a Do mode 1 01 010 110) 56 or [wt mle Perl TT mode 2 o1 011 110 | 5E Note IFF indicates the interrupt enable flip-flop, CY indicates the carry flip-flop. Flags: @ unchanged, 0=reset, 1=set, X=undefined, } =set or reset according to the result of the operation Table 6 16-bit arithmetic group Wnomone | Soot Tea] MAT MH) Conca operation [76 543 210| (Basic) | C |Z [Pv] S | N | H | Bytes (M Cycles! T States = ADD HL, ss HL + HL 00 ssl 001} 09+ 0|x 1 3 ll 5: +ss eet _ss_ | Reg = tss+C OL ssi_ 010} 4A+ ol DE SBCHL,ss | HL-HL | 11 101 101| ED Vv 1/xX) 2 | 4 | 15 10 HL ADD IX, pp | IX+1X+pp] 11 O11 101) DD . o;x] 2] 4 | 15 ADDIY,rr | IY —1¥+rr| 11 11 101 eye] Lt Ly BC 00 rl 001 | 09+ o1 DE INcss | s~ssti [oo sso om [ ost felefelefefel i Tite) wo | x nee Poree ome eee eee te Tey nt & 00 100 O11 | 23 00 100 011 | 23 . i Reg. DEC ss ss+—ss—1 | 00 ssl O11 | OB+ 1] 1 6 |"00 BC DEC IX IX = IX—1]11 O11 101] DD I*| 2/2 |) 101 o DE _ __ 00 101 011| 2B 10 YY DEC IY y¥ —ly-1 | 11 111 101] FD | ee? tt ll SP . 00101 O11 | 2B | Note: ss is any of the register pairs BC, DE, HL, SP. | pp is any of the register pairs BC, DE, 1X, SP. rr is any of the register pairs BC, DE, IY, SP. | Flags : @ =unchanged, 0=reset, 1=set, X=undefinede, $ =set or reset according to the result of the operation 303

Table 7 Rotate and shift groups Venom | Svabole [OP cote [ikea] Flaws [ol MMO] Gana, operation [76 543 210] (Basic) | C |Z [Pv] S | N | H | Bytes |MCycies|T States ae RLCA HH 0 000 | 07 | a] Rotate left circular A accumulator. RLA C=} 00 o10 | 17 0/0 Rotate left A . accumulator. (ee Rotate right circular A accumulator. RRA [=9H) oo on | a if 1 Rotate right A accumulator, RLCr 11 001 011] CB 2 | 2 Rotate left circular i ook | 00+ register r. RUC (HL) | 11 001 011] CB 0 4 | 15 R | ook 110} 06+ 000 i RLC (IX+d) 11011101) DD tt o|0 23 001 c 11 001 011) CB 1, (HL), \\ | 010 D (ixt+a, |= 4 > | oll E RLC (IY +d) iio; rp | t]t 23°] tot L | 11 001 011) cB 1 A -~d- | oo k 10} 06+) | RLm (Cg =a-! P|tl}ojo fa Mnemonic | _k RLC | 000 RRC m =p P}tj)olo RRC | 001 a RL | 010 2 2 RR oul ren (Sg Pitjofo PTET EBT) a | Yoo m 2 |\\4 | jis 4 | 46 | (23 | SRA | 101 SLA m Pitlolol ly | le | les SRL | 111 SRA m p|tlolo m=r, (HL), (IX +d), (IY +d) skim ESS a- Pit}olo * depends on m. Rotate digit left and 11 101 101} ED right between the RLD AlEq Fa Ha GFA, | ol 101 111) 6F 5 accumulator and location (HL). A The content of the RRD jae Ee 11 101 101) ED 5 | 1g. | wpper half of the | Fit)| Ol 100 111) 67 accumulator is un- affected. Flags : @ =unchanged O=reset 1=set X =undefined 1 =set or reset according to the result of the operation ——— SHARP 304

Z80 CPU Central Processing Unit LHO0080 TS EE ES TE TS Table 8 Bit set, reset and test group Mnemon Symbolic | OP code [HEX code No.of ] No.of | No.of Comments __ Mnemonic | operation [76 543 210] (Basie) | C N Bytes [M Cyctes|T States _ BIT br int 11 001 011' CB jet ofi)2,2fsa) . Reg 7 orb | 40+ _ 300 - BIT b, (HL) | ZL» | 11 001 O11] cB fe] t 1] 273 112] oo C o1_b 10} 46+ 010 D BIT b, (Xa) | Z = (X-Fdp| 11 O11 101] DD x[X 5 120] on E | U1 001 O11 | CB | 100 H ~ @ i | 101 L orb 10| 46+ | tn ‘A BIT b,y+a)| Z—-yY+¥dp| 11 111 101) FD 4 | 5 | 20 | 1001 o1t| ce b_| bi Tews ol_b 110] 46+ 000 ° oo ao ooo —+ 001 1 SET b,r nel 11 001 011) CB 2) 218 j 010 2 SET b, (HL) | (HL 1 | 11 001 o11| CB 4) 15 | b00 ; a_b 110] 06+ | 101 5 SET b(X+a)) (Xd = 1/11 O11 101] DD 6 | 231 iy 6 : /11 001 011) CB | an ; |- a> ; | lab _10| 06+ i SET b(¥+a| @Y¥+dy = 1/11 111 101] FD @[ 4 [6 | 23 | Mnemonic | a 11 001 out | cB | ser [ou -~ a) | RES | 10 | 2%) 2%] 38 RES bm mao | 4 | 6 | 23 | (X+d), (Y+4) = 4.6 23_| “depends on m 5: Note : The notation ms indicates bit b (0 to 7) or location m, —_ Flags ; @ = unchanged O=reset 1=set X=undefined $ =set or reset according to the result of the operation 305

Z80 CPU Central Processing Unit LHO080 ES EE TS TT OT SOT Table 9 Jump group Mnemonic Symbolic OP code [HEXcode] Flags ———_—| No.of | No.of | No.of Comments mnemonie | operation |76 543 210] (Basic) | C |Z [Pv] S Bytes |M Cycles} T States JP oo PC=nn | 11 000 011! C3. Jelelele 3 | 3 | 10 — ao ce_| Condition ee 000 NZ IP ce, nn Weondition ce | 11 ec O10) C2+ 3 / 3 oor 2 010 NC istruePC#on,|— on on c al PE Te| &) = 101 | PE Re PC += PC+e] 00 O11 000 2 ~ 2 110 Pp ul M IR Ce 1C=1 00 111 000] 38 2] 3 | 12 PC + PCt+e] = 2 + _ NZ: non-zero

1 C=0 2] 2 | 7 | Z:2er0

continue C: carry IR NC, e 1 C=0 00 110 000 | 30 2 | 3 | 12 | PO: parity odd PCH PCte] = e2 + PE : parity even Wec=l 2 | 2 |] 7 | P:sign positive continue M: sign negative IR Ze iW Z=1 00 101 000 28 3 | 12 PC PCHe| = e2 + WZ=0 2; 2/7 continue _ JR NZ, e "Z=0 00 100 000 20 2 | 3 | 12 1fZ=1 2) 2/7 continue pq) | pc-wi [ii toi oor | eo lelefeleleje| i |i fa | JP (X) pC+Ix | 11 on 101) DD 2/2 11 101 001 | E9 JP (lY) pc=ly [ii 111 101| FD 2 | 2 11 101 001 | E9 DINZ, e If B - B—1| 00 010 000 2] 3 ] 13 BHO - 2 = PC = PC+1 | If B=0 272] 8 continue Note : e represents the extension in the relative addressing mode. e is a signed two's complement number in the range <~-126, 129> ¢ —2 in the opcode provides an effective address of pc+e as PC is incremented by 2 prior to the addition of e. e itself is obtained from opcode position. Flags : @ =unchanged O=reset 1=set X=undefined =set or reset according to the result of the operation 306

280 CPU Central Processing Unit LHOO080

Table 10 Call and return group Mnemonic | S¥mbolic [OP code [HEX coe Flags No.of | No.of | No.of Comments _ operation [76 543 210| (Basic) | C | Z [rv| S | N | H | Bytes IM Cycles\\T States CALL an | (SP—1)* PCs] 11 001 101] CD ele eje/ 3/5 | 17 ce | Condition (SP—2)- PG) = on 000 | Nz PC = nn - 2 > | 001 Z CALL ce, an | Meondition ce is) 11 ce 100] Ca+ 010 Nc aes io : otherwise same | — on Be 100 | PO as CALL an it 101 PE RET PC. = (SP) | 11 001 001] C9 l*| | ele} i | 3 | 10 0 P PCa = (SP+1)| | 7 111 M RET ce Ifeondition ce is 11 ce 000) CO+ efef/ ij 3iu false continue, — L otherwise same ' 1 1 5 r Pp _ as RET 000 | 00x RETI Return from | 11 101 10) ; ie] yet? | i | 001 081 interrupt 01 001 101] 4D 010 10% RETN Return from | 11 101 101| ED ee 2 4 oll 181 non-maskable| 01 000 101| 45 100 200 interrupt 101 28H RST p (P=)— Pe fd ot Mn] C7+ ele; i | 3 110 | 30" (SP-2) = PC | lll 380 PC = 0 PC. p | Flags : @ =unchanged O=reset 1=set X=undefined $ =set or reset according to the result of the operation . 307

Z80 CPU Central Processing Unit LHO0O80 ET EE SS Table 11 Input and output group Symbolic | OP code [HEX code] No. of | No.of | No.of . Mnemonic | operation [76 543 210] (Basic) | C Bytes [MCyekes|T States] ——COMMERES _ 7 -~ 1 | Acc An-Ats INT, (C) TO 11 101 101} ED [@ 0 1] 2 | 3 | 12 ol _r 000} 40+ INI (HL) fil 101 101) ED [Xx x|X x 16 |C— AvAr B+B-1 |10 100 010] A2 B- Ag-Aus HL = HL+1) | INIR (ity Jit i01 tor] ED |x]i|{x]x]}1ijx] 2] 5 | 2 : Reg, B+B-1 |10 110 010| B2 ® (ir B#0) 000 B HL + HL+1 2] 4) 16) oo C Repeat until lar B=0) o10 D IND (aly) [i ior ior) ED [xf t]x]{x}1;x] 2 [4 |] 16} jo H B+B-1 | 10 101 010] AA ® 101 L HL — HL—1) el A INDR (aly) Jil tor ioif ep [x]ilxtx]aifx] 2] 5 | a B+B-1 /10 111 010) BA lar B #0) -HL = HL~1 @® 2 4 16 Repeat until (ir B=0) B=0 OUT (n), A ae D3 ejee “le 2 | 3 [i [a ees _ _ Ace —* (A-BUS)y-15 ouT(,r | Ger 11 101 101, ED elelele I | 2] 3 7 for oor ant _ OUT! ©) fir io wr, ED |xft|x|{xfailx] 2] 4 C Ava B+B-1 | 10 100 011] A3 O| | HL — HL+1 OTIR ©) [iii iol eo [x]filx]x x] 2 | 5 | 21 |B AwAs B+B-1 | 10 110 011] B3 | la B#0) HL + HL+1 ® 2 4 16 Repeat until {Ir B=0) B=0 OUTD (+a) fir ior wil ep [x] t{x]x x[ 2 | 4 [16 - HL ~ HL=1 - _ _ OTDR (= (AL) [11 101 101] BD | X/1{x)x x} 2 | 5 | 21 B+B-1 | 10 111 O11] BB (B70) HL = HL-1 @ 2 4 16 Repeat until \\lk B=0) B=0 Note: If the result of B—! is zero the Z flag is set, otherwise it is reset. @Z flag is set upon instruction completion only. Flags : @=unchanged O=reset 1=set X=undefined 4 =set or reset according to the result of the operation 308