LD3811

LD3811 LDT | Alldatasheet

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Technical content

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 LD3811 Dot Matrix LCD Controller and Driver Ver. 1.1 / July. 2013 This document is a general product description and is subject to change without notice. LDT Inc. does NOT assume any responsibility for use of circuits described. LD3811 Dot Matrix LCD Controller and Driver

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 Overview LD3811 is 1/8 to 1/10 duty dot matrix LCD display controller/drivers that supports the display of characters, numbers, and symbols. In addition to generating dot matrix LCD drive signals based on data transferred serially from a microcontroller. Also LD3811 provides on-chip character display ROM and RAM to allow display systems to be implemented easily.

Features

• Controls and drives a 5 X 7, 5 X 8, or 5 X 9 dot matrix LCD.
• Supports accessory display segment drive (up to 60 segments)
• Display technique: 1/8 duty 1/4 bias drive (5 X 7 dots), 1/9 duty 1/4 bias drive (5 X 8 dots) 1/10 duty 1/4 bias drive (5 X 9 dots)
• Display digits: 12 digits X 1 line (5 X 7 dots), 11 digits X 1 line (5 X 8 or 5 X 9 dots)
• Display control memory CGROM: 240 characters (5 X 7, 5 X 8, or 5 X 9 dots) CGRAM: 16 characters (5 X 7, 5 X 8, or 5 X 9 dots) ADRAM: 12 X 5 bits DCRAM: 48 X 8 bits
• Instruction function : Display on/off control / Display shift function
• Provides a backup function based on low power modes.
• Serial data communication with the system controller.
• Independent LCD drive block power supply VLCD
• Provides a RES pin for LSI internal initialization
• RC oscillator circuit
• Pb free applied Package Dimensions

80 QFP unit: mm

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 Pin Assignments (Top View) LD3811 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 COM5 COM6 COM7 COM8 SEG60/COM9 SEG59/COM10 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG0 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 COM4 COM3 COM2 COM1 VDD VLCD VLCD1 VLCD2 VLCD3 VSS OSCO OSC1 RES CE CL DI PART NUMBER PACKAGE Ta LD3811 - QFP 80 QFP -40°C to 85 °C

ORDERING INFORMATION

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Allowable Operating Ranges at Ta = –40 to 85°C, VSS = 0 V SEG1 to SEG60, COM1 to COM10 SEG1 to SEG60 Parameter Symbol Conditions Ratings Unit Maximum supply voltage Output voltage Input voltage Output current Allowable power dissipation Storage temperature Operating temperature VDD max VDD VLCD max VLCD –0.3 to +7.0 V V V V V V V µA µA mW CE, CL, DI, RES VLCD1, VLCD2, VLCD3 OSCO OSCI COM1 to COM10 Ta = 85°C VIN1 VIN2 VIN3 VOUT1 VOUT2 IOUT1 IOUT2 Pd max Topr Tstg –0.3 to +11.0 –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VLCD + 0.3 –0.3 to VDD + 0.3 –0.3 to VLCD + 0.3 300 –40 to +85 200 –55 to +125 Parameter Symbol Conditions Ratings Min typ max Unit Supply voltage Input voltage Input high level voltage Input low level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Minimum reset pulse width VDD VDD VLCD VLCD VLCD1 VLCD1 VLCD2 VLCD2 VLCD3 VLCD3 VIH1 CE, CL, DI, RES 0.8 VDD 6.0 V VIH2 OSCI 0.7 VDD VDD V VIL1 CE, CL, DI, RES 0 0.2 VDD V VIL2 OSCI 0 0.3 VDD V ROSC OSCI, OSCO 33 k½ COSC OSCI, OSCO 220 pF fOSC OSC 150 300 600 kHz Tds CL, DI: Figure 2 160 ns Tdh CL, DI: Figure 2 160 ns tcp CE, CL: Figure 2 160 ns Tcs CE, CL: Figure 2 160 ns Tch CE, CL: Figure 2 160 ns tøH CL: Figure 2 160 ns tøL CL: Figure 2 160 ns tWRES RES: Figure 3 1 µs

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 Electrical Characteristics in the Allowable Operating Ranges Note *1: Excluding the bias voltage generation divider resistor built into the VLCD1, VLCD2, and VLCD3. (See figure 1.) Hysteresis VH CE, CL, DI, RES 0.1 VDD V Input high level current IIH CE, CL, DI, RES, OSCI: VI = 6.0 V 5.0 µA Input low level current IIL CE, CL, DI, RES, OSCI: VI = 0 V –5.0 µA Parameter Symbol Conditions Ratings Unit Min typ max Output high level voltage Output low level voltage Output middle level voltage*1 Oscillator frequency Current drain SEG1 to SEG60: IO = –20 µA VLCD – 0.6 V VOH1 VOH2 OM1 to COM10: IO = –100 µa VLCD – 0.6 V VOH3 OSCO: IO = –500 µA VDD – 1.0 V VOL1 SEG1 to SEG60: IO = 20 µa 0.6 V VOL2 COM1 to COM10: IO = 100 µA 10.6 V VOL3 OSCO: IO = 500 µA 1.0 V VMID1 SEG1 to SEG60: IO ±20 µA 2/4 VLCD – 0. 6 2/4 VLCD + 0.6 V fOSC OSCI, OSCO: ROSC = 33 k½ , COSC = 220 pF 210 300 390 kHz IDD1 VDD: power saving mode 5 µA IDD2 VDD: VDD = 6.0 V, output open, fOSC = 300 kHz 450 900 µA ILCD1 VLCD: power saving mode 5 µA ILCD2 VLCD: VLCD = 10.0 V, output open, fOSC = 300 kHz 200 400 µA

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

• When CL is stopped at the low level
• When CL is stopped at the high level Figure 2 Diagram SEG60/COM9 SEG59/COM10 SEG58 SEG1 COM1 COM8 VDD VLCD VLCD1 VLCD2 VLCD3 VSS VDD VLCD VLCD1 VLCD2 VLCD3 VSS RES

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 Pin Functions SEG1 to SEG58 SEG59/COM10 SEG60/COM9 Segment driver outputs. The SEG59/COM10 and SEG60/COM9 pins can be used as common driver outputs under the ―set display Technique‖instruction. Pin Pin No. LC75811E LD75811W Function Active I/O Handling when unused 1 to 58 79, 80 1 to 56 - O OPEN - O OPEN - O OPEN - I GND COM1 to COM8 68 to 61 66 to 59 Common driver outputs. Oscillator connections. An oscillator circuit is formed by connecting an external resistor and capacitor at these pins. Serial data transfer inputs. These pins are connected to the microcontroller. CE: Chip enable CL: Synchronization clock DI: Transfer data Reset signal input.

• When RES is low (VSS):
• Display off SEG1 to SEG58 = “L” (Vss) SEG59/COM10 and SEG60/COM9 = “L” (Vss) COM1 to COM8 = “L” (VSS).
• Serial data transfer is disabled.
• The OSCI/OSCO pin oscillator is stopped.
• When RES is high (VDD):
• Display on after a “display on/off control” (display on state setting) instruction is executed.
• Serial data transfers are enabled.
• The OSCI/OSCO pin oscillator operates. Used for applying the LCD drive 3/4 bias voltage externally. Used for applying the LCD drive 2/4 bias voltage externally. Used for applying the LCD drive 1/4 bias voltage externally. Logic block power supply connection. Provide a voltage of between 2.7 and 6.0 V. LCD driver block power supply connection. Provide a voltage of between 4.5 and 10.0 V. OSCI 76 74 OSCO 75 73 CE 78 76 CL 79 77 DI 80 78 RES 77 75 VLCD1 71 69 VLCD2 72 70 VLCD3 73 71 VDD 69 69 VLCD 70 68 VSS 74 72 Power supply connection. Connect to ground. - I OPEN - I OPEN - I OPEN H I L I - I I - - - - - - - - - GND GND

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

• When the DCRAM address loaded into AC is 00H. However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below. Note:*2. The DCRAM addresses are expressed in hexadecimal. Least significant bit Most significant bit Example: When the DCRAM address is 2EH. Note:*3. 5 X 7 dots ... 12-digit display 5X 7 dots 5 X 8 dots ... 12-digit display 4X 8 dots 5 X 9 dots ... 12-digit display 3X 9 dots Display digit 1 2 3 4 5 6 7 8 9 10 11 12 DCRAM address (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0A 0B Display digit 1 2 3 4 5 6 7 8 9 10 11 12 DCRAM address (hexadecimal) 01 02 03 04 05 06 07 08 09 0A 0B 0C Display digit 1 2 3 4 5 6 7 8 9 10 11 12 DCRAM address (hexadecimal) 2F 00 01 02 03 04 05 06 07 08 09 0A (Left shift) (Right shift) DCRAM address DA0 DA1 DA2 DA3 DA4 DA5 LSB MSB Hexadecimal Hexadecimal DA0 DA1 DA2 DA3 DA4 DA5 0 1 1 1 0 1 Block Functions
• AC (address counter) AC is a counter that provides the addresses used for DCRAM and ADRAM. The address is automatically modified internally, and the LCD display state is retained.
• DCRAM (data control RAM) DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 5 ´ 7, 5 ´ 8, or 5 ´ 9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of 48 ´ 8 bits, and can hold 48 characters. The table below lists the correspondence between the 6-bit DCRAM address loaded into AC and the display position on the LCD panel.

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

• ADRAM (Additional data RAM) ADRAM is RAM used to store the ADATA display data. ADRAM has a capacity of 12 ´ 5 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence between the 4-bit ADRAM address loaded into AC and the display position on the LCD panel.
• When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 12) Display digit 1 2 3 4 5 6 7 8 9 10 11 12 ADRAM address (hexadecimal) 0 1 2 3 4 5 6 7 8 9 A B However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 ADRAM address (hexadecimal) 1 2 3 4 5 6 7 8 9 A B 0 Display digit 1 2 3 4 5 6 7 8 9 10 11 12 ADRAM address (hexadecimal) B 0 1 2 3 4 5 6 7 8 9 A (Left shift) (Right shift) Note: *4. The ADRAM addresses are expressed in hexadecimal. Least significant bit Most significant bit ADRAM address RA0 RA1 RA2 RA3 Hexadecimal Example: When the ADRAM address is AH RA0 RA1 RA2 RA3 0 1 0 1 Note: *5. 5 ´ 7 dots ... 12-digit display 5 dots 5 ´ 8 dots ... 12-digit display 4 dots 5 ´ 9 dots ... 12-digit display 3 dots
• CGROM (Character generator ROM) CGROM is ROM used to generate the 240 kinds of 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns from the 8-bit character codes. CGROM has a capacity of 240 ´ 45 bits. When a character code is written to DCRAM, the character pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD corresponding to the DCRAM address loaded into AC.
• CGRAM (Character generator RAM) CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 x 45 bits.

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 Reset Function The LD3811 are reset when a low level is applied to the RES pin at power on and, in normal mode. On a reset the LD3811 create a display with all LCD panels turned off. However, after a reset applications must set the contents of DCRAM, ADRAM, and CGRAM before turning on display with a ―display on/off control‖ instruction since the contents of these memories are undefined. That is, applications must execute the following instructions.

• Set display technique
• DCRAM data write
• ADRAM data write (If ADRAM is used.)
• CGRAM data write (If CGRAM is used.)
• Set AC address After executing the above instructions, applications must turn on the display with a ―display on/off control‖ instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a ―display on/off control‖ instruction. (See the detailed instruction descriptions.) Serial Data Transfer Format
• When CL is stopped at the low level CE CL DI CCB address 8 bits Instruction data Up to 64 bits B0 B1 B2 B3 A0 A1 A2 A3
• When CL is stopped at the high level CE CL DI CCB address 8 bits Instruction data Up to 64 bits B0 B1 B2 B3 A0 A1 A2 A3
• CCB address: 47H
• D0 to D63: Instruction data The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time.

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 Instruction Table Notes:*6.The data format differs when the ―DCRAM data write‖ instruction is executed in the increment mode (IM = 1). (See detailed instruction descriptions .) *7.The data format differs when the ―ADRAM data write‖ instruction is executed in the increment mode (IM = 1). (See detailed instruction descriptions.) *8.The execution times listed here apply when fosc = 300 kHz. The execution times differ when the oscillator frequency fosc differs. Example: When fosc = 210 kHz 300 27 µs ´ ——= 39 µs 210 *9.When the power saving mode (BU = 1) is set, the execution time is 27 µs (when fosc = 300 kHz).

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 SEG60 SEG59 SEG59 SEG60/COM9 SEG59/COM10 Detailed Instruction Descriptions

• Set display technique ... <Sets the display technique> Code D56 D57 D58 D59 D60 D61 D62 D63 DT1 DT2 X X 0 0 0 1 DT1, DT2: Setting the display technique DT1 DT2 Display technique Output pins 0 0 1/8 duty, 1/4 bias drive 1 0 1/9 duty, 1/4 bias drive COM9 0 1 1/10 duty, 1/4 bias drive COM9 COM10 Note: *10. Sn (n = 59, 60): Segment outputs COMn (n = 9, 10): Common outputs
• Display on/off control ... <Turns the display on or off> Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 X X X X M A SC BU 0 0 1 0 M, A: Specifies the data to be turned on or off. Note: *11. MDATA, ADATA

5 X 7 dot matrix display 5 X 8 dot matrix display 5 X 9 dot matrix display

DG1 to DG12: Specifies the display digit For example, if DG1 to DG6 are 1, and DG7 to DG12 are 0, then display digits 1 to 6 will be turned on, and display digits 7 to 12 will be turned off (blanked Display digit 1 2 3 4 5 6 7 8 9 10 11 12 Display digit data DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 M A Display operating state 0 0 Both MDATA and ADATA are turned off (The display is forcibly turned off regardless of the DG1 to DG12 data.) 0 1 Only ADATA is turned on (The ADATA of display digits specified by the DG1 to DG12 data are turned on.) 1 0 Only MDATA is turned on (The MDATA of display digits specified by the DG1 to DG12 data are turned on.) 1 1 Both MDATA and ADATA are turned on (The MDATA and ADATA of display digits specified by the DG1 to DG12 data are turned on.)

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 Note: *12. When SC is 1, the SEG1 to SEG60 and COM1 to COM10 output pins are set to the VSS level, regardless of the M, A, an d DG1 to DG12 data. SC: Controls the common and segment output pins. SC Common and segment output pin states

0 Output of LCD drive waveforms

1 Fixed at the VSS level (all segments off)

BU: Controls the normal mode and power saving mode. BU Mode

0 Normal mode

1 (In this mode, the OSCI and OSCO pins oscillator is stopped, and the common and segment pins are set to the VSS l evel. In this mode, instructions other than the “display on/off control” instruction cannot be executed. Thus applications must set the LSI to normal mode before executing any of the other instructions.)

• Display shift ... <Shifts the display> M, A: Specifies the data to be shifted R/L: Shift direction specification
• Set AC address... <Specifies the DCRAM and ADRAM address for AC> DA0 to DA5: DCRAM address LSB MSB Least significant bit Most significant bit RA0 to RA3: ADRAM address This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC. LSB MSB Least significant bit Most significant bit Code D56 D57 D58 D59 D60 D61 D62 D63 M A R/L X 0 0 1 1 M A Shift operating state 0 0 Neither MDATA nor ADATA is shifted 0 1 Only ADATA is shifted 1 0 Only MDATA is shifted 1 1 Both MDATA and ADATA are shifted R/L Shift direction

0 Left shift

1 Right shift

D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 Code DA0 DA1 DA2 DA3 DA4 DA5 X X RA0 RA1 RA2 RA3 0 1 0 0 DA0 DA1 DA2 DA3 DA4 DA5 RA0 RA1 RA2 RA3

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

• DCRAM data write ... <Specifies the DCRAM address and stores data at that address> Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X IM X X X 0 1 0 1 DA0 to DA5: DCRAM address DA0 DA1 DA2 DA3 DA4 DA5 LSB MSB Least significant bit Most significant bit AC0 to AC7: DCRAM data (character code) AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 LSB MSB Least significant bit Most significant bit This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a 5 X 7, 5 X 8, or 5 X 9 dot matrix display data using CGROM or CGRAM. IM: Setting the method of writing data to DCRAM IM DCRAM data write method 0 Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.). 1 Increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.) Notes: *13.
• DCRAM data write method when IM = 0
• DCRAM data write method when IM = 1 (Instructions other than the ―DCRAM data write‖ instruction cannot be executed.)

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X IM X X X 0 1 0 1 SEG5m +1 (m is an integer 0 - 11) SEG5m + 2 SEG5m + 3 SEG5m + 4 SEG5m + 5 SEG5m+1 SEG5m+5 (m is an integer between 0 and 11) Code Code Code Code Data format at (1) (24 bits) Data format at (2) (8 bits) Data format at (3) (16 bits)

• ADRAM data write ... <Specifies the ADRAM address and stores data at that address> RA0 to RA3: ADRAM address D56 D57 D58 D59 D60 D61 D62 D63 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 0 X X X 0 1 0 1 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 AD1 AD2 AD3 AD4 AD5 X X X RA0 RA1 RA2 RA3 X X X X IM X X X 0 1 1 0 RA0 RA1 RA2 RA3 LSB MSB Least significant bit Most significant bit AD1 to AD5: ADATA display data In addition to the 5 X 7, 5 X 8, or 5 X 9 dot matrix display data (MDATA), this LSI supports direct display of the five accessory display segments provided in each digit as ADATA. This display function does not use CGROM or CGRAM. The figure below shows the correspondence between the data and the display. When ADn = 1 (where n is an integer between 1 and 5) the segment corresponding to that data will be turned on. Cod e ADATA Corresponding output pin AD1 AD2 AD3 AD4 AD5

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG56 SEG57 SEG58 COM10/SEG59 SCOM9/SEG60 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG56 SEG57 SEG58 COM10/SEG59 SCOM9/SEG60

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG56 SEG57 SEG58 COM10/SEG59 SEG56 SEG57 SEG58 COM10/SEG59 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG56 SEG57 SEG58 SEG56 SEG57 SEG58 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 Sample Correspondence between Instructions and the Display

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220 LD3811 Character Font (Standard)

Ver1.1 LD3811 Dot Matrix LCD Controller and Driver LDT Inc. WE bldg. 5F, 126-33 Han-dle 1ro, Seobuk-gu, Cheonan, Chungnam, korea, 331-220

PACKAGE INFORMATION

80 QFP Unit : mm