IMX2267C POWERINT | Alldatasheet
Document overview
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Technical content
www.power.com December 2024 Off-Line Zero Voltage Switching (ZVS) Flyback Switcher IC for Multi-Output Applications This Product is Covered by Patents and/or Pending Patent Applications. Product Highlights Highly Integrated, Compact Footprint
- Up to 3 independently regulated outputs using a single controller and transformer
- Eliminates post regulators
- Incorporates a multi-mode Quasi-Resonant Discontinuous Conduction Mode (DCM) and Continuous Conduction Mode (CCM) flyback controller, 650 V, 725 V, 750 V or 1700 V power switch, secondary-side control and synchronous rectification driver
- Integrated FluxLink™ feedback link eliminates optocouplers
- Zero voltage switching (ZVS) using advanced SR FET control with DCM only mode
- Excellent transient response: <±5% CV with 100% load step
- Outputs up to 200 V for CV and CC (LED drive) configurations EcoSmart™ – Energy Efficient
- PowiGaN™ technology enables >90% efficient power supplies
- Designs easily meet global energy efficiency regulations
- Proprietary switching algorithm ensures high efficiency across load
- Low dissipation allows PCB cooling – no heat sinks required Advanced Protection / Safety Features
- Primary sensed output OVP
- Open SR-FET gate detection
- Hysteretic thermal shutdown
- Input voltage monitor with accurate brown-in/brown-out and overvoltage protection
- Overload protection for each output
- LED short / open protection Full Safety and Regulatory Compliance 7
- Reinforced isolation
- Isolation voltage >4000 VAC
- 100% production HIPOT tested
- UL1577 isolation voltage 4000 VAC (max) and TUV (EN62368)
- Enables designs required to meet class A performance criteria for EN61000-4 suite of test standards, including EN61000-4-2, Green Package
- Halogen free and RoHS compliant
Applications
- High efficiency driver for monitors and TVs
- Ideal for designs that need to meet Energy Star 8, CEC, and 2021/2023 EU labeling requirements
- High efficiency multi-output power supplies for industrial, smart- meter and appliance applications
Figure 1. Typical Application with LED Driver. (IMX2353F (1700 V) does not Figure 2. Typical Application with Two Constant Voltages. Figure 3. Typical Application with Three Constant Voltages. Figure 4. Left - InnoMux2-EP in InSOP-24B Package. Middle - InnoMux2-EP in InSOP-T28D/B Package. Right - InnoMux2-EP in InSOP-T28G Package.
3.3 V uVCC
1 CV & 1 CC Output6
230 VAC ±15%1 85-265 VAC1 385 VDC (PFC Input)
650 V MOSFET
750 V PowiGaN
725 V MOSFET
1700 V PowiGaN
Table 1. InnoMux2-EP Controller Part Numbers.
- Continuous power using nominal primary current limit in a typical open frame application at +50 °C
ambient with adequate PCB thermal design to ensure package temperature <125 °C.
- InSOP-24B (C) exposed pad.
- InSOP-T28B (F) exposed pad.
- For information about other output voltage and current configurations or the addition of a 3.3 V 25 mA
uVCC output, please contact your local PI representative.
- Safety certification pending for IMX2353F.
Rev. D 12/24 InnoMux2-EP www.power.com Part No. Switch Rating Continuous Power Peak Power1 Output CV12 Maximum VLED VSENSE Voltage2 SR MOSFET Driver Dimming Interface2 Package IMX2267C 650 V 36 W1 57 W 1 CV, 1 CC 12 V 80 V 0.8 V No 2-Pin Filtered PWM/ Hybrid Dimming InSOP-24B IMX2268C 650 V 50 W1 80 W 1 CV, 1 CC 12 V 80 V 0.8 V No 2-Pin Filtered PWM/ Hybrid Dimming InSOP-24B IMX2278F 750 V 60 W1 94 W 1 CV, 1 CC 12 V 140 V 0.9 V Yes 2-Pin Filtered PWM/ Hybrid Dimming InSOP-T28B IMX2279F 750 V 70 W1 110 W 1 CV, 1 CC 12 V 150 V 1.0 V Yes 2-Pin Filtered PWM/ Hybrid Dimming InSOP-T28B IMX2270F 750 V 80 W1 130 W 1 CV, 1 CC 12 V 170 V 1.0 V Yes 2-Pin Filtered PWM/ Hybrid Dimming InSOP-T28B IMX2174F 725 V 15 W1 2 CV3 Yes InSOP-T28D IMX2175F 725 V 22 W1 2 CV3 Yes InSOP-T28D IMX2176F 725 V 27 W1 2 CV3 Yes InSOP-T28D IMX2177F 725 V 36 W1 2 CV3 Yes InSOP-T28D IMX2378F 750 V 55 W1 3 CV4 Yes InSOP-T28D IMX2379F 750 V 65 W1 3 CV4 Yes InSOP-T28D IMX2370F 750 V 75 W1 3 CV4 Yes InSOP-T28D IMX2353F 1700 V 100 W5 3 CV6 Yes InSOP-T28G Table 2. Configuration Options.
- These parameters can be configured to other values.
- Can be configured to 3 CV.
- Can be configured to 2 CV.
- Also available on 2 CV. See Feature Code Table.
Description
The InnoMux™2-EP IC dramatically improves power conversion efficiency. By independently regulating and protecting each output the InnoMux2-EP family eliminates multiple downstream conversion stages. InnoMux2-EP IC-based designs have low BOM count and small size. The family incorporates both primary and secondary-side controllers, with protection, sense elements and a safety-rated feedback mechanism (FluxLink) into a single IC. The InnoMux2-EP IC also includes an LED backlight controller that supports multi-mode dimming making it ideal for monitors, TVs and appliances with lighting or display requirements. The InnoMux2-EP IC contains enhanced features for maximizing conversion efficiency including quasi-resonant switching in DCM operation, accurate SR control and minimum-threshold-regulation for the LED driver.
Figure 5. InnoMux2-EP Primary Block Diagram.
connected between this and the GND pin. regulation of voltage to minimise MOSFET power dissipation. Gate driver for external selection MOSFET for the V CV1 output. power for the secondary-side controller during start-up. voltage regulation and protection. voltage for overvoltage protection.
1 ISENSE
2 GND
3 IDRIVE
4 VSENSE
5 CDR1
6 BPS
7 DIM2
8 DIM1
9 FWD
10 VCV1
11 VLED
Figure 8. InnoMux2-EP InSOP-24B 1CV+1LED Dual Dimming Pin Configuration Leave open. Should not be connected to any other pins. Leave open or connect to the SOURCE pin or BPP pin. reference for the primary BYPASS pin. Power switch Drain connection.
between this and the GND pin. regulation of voltage to minimise MOSFET power dissipation. Gate driver for external selection MOSFET for V CV1 output. Gate driver for external SR MOSFET. power for the secondary-side controller during start-up. voltage regulation and protection. voltage for overvoltage protection.
10 FWD
11 VCV1
13 VLED
Figure 9. InnoMux2-EP InSOP-T28B 1CV+1LED Dual Dimming with SR Pin Configuration (Bottom View). Leave open. Should not be connected to any other pins. Leave open or connect to SOURCE pin or BPP pin. Leave open. Should not be connected to any other pins. Power switch Drain connection.
connected to any other pins. Leave open. Should not be connected to any other pins. Gate driver for external selection MOSFET for V CV1 output. Connection for external bypass capacitor for the secondary IC supply. Gate driver for external SR MOSFET. power for the secondary-side controller during start-up. the controller on the secondary-side and for protection. 2CV configuration. Can be left open if not in use. the controller on the secondary-side and for protection.
13 VCVHV
12 VCV2/AS
8 FBHV
7 CDR2
3 FB2
1 FB1
Figure 10. InnoMux2-EP InSOP-T28D 3CV / 2CV Pin Configuration. Leave open. Should not be connected to any other pins. Leave open or connect to SOURCE pin or BPP pin. Leave open. Should not be connected to any other pins. reference for primary BYPASS pin. Power switch Drain connection.
output voltage of VCV1. Not used with internal feedback*. Leave open. Should not be connected to any other pins. Gate driver for external selection MOSFET for VCV1 output. Connection for external bypass capacitor for the secondary IC supply. Gate driver for external SR MOSFET. power for the secondary-side controller during start-up. the controller on the secondary-side and for protection. 2CV configuration. Can be left open if not in use. for the controller on the secondary-side and for protection. Figure 11. InnoMux2-EP InSOP-T28G 3CV Pin Configuration. Leave open. Should not be connected to any other pins. Leave open. Should not be connected to any other pins. reference for primary BYPASS pin.. Power switch drain connection.
Rev. D 12/24 InnoMux2-EP www.power.com InnoMux2-EP Functional Description The InnoMux2-EP combines a high-voltage power switch, along with both primary-side and secondary-side controllers in one device. The InnoMux2-EP architecture incorporates a novel inductive coupling feedback scheme using the package lead frame and bond wires to provide a safe, reliable, and low-cost means to accurately communi - cate power requests from the secondary controller to the primary controller. The primary controller on InnoMux2-EP is a quasi-resonant (QR) flyback controller to operate in continuous conduction mode (CCM) or discontinous conduction mode (DCM) with Zero voltage switching (ZVS) using advanced SR FET control. The controller uses a variable current control scheme. The primary consists of a jitter oscillator; a receiver circuit magnetically coupled to the secondary controller, a current limit controller, 5 V regulator on the PRIMARY BYPASS pin, audible noise reduction engine, bypass overvoltage detection circuit, a lossless input line sensing circuit, current limit selection circuitry, overvoltage protection, leading edge blanking, secondary output diode / SR MOSFET short protection circuit and a 650 V / 725 V / 750 V and 1700 V power switch. The secondary controller consists of a transmitter circuit that is magnetically coupled to the primary receiver, multi-output controller for regulating up to three outputs independently, 5 V regulator on the SECONDARY BYPASS pin, synchronous rectifier (SR) MOSFET driver, high-side MOSFET drivers, shunts to prevent individual outputs from rising in abnormal loading conditions, single string LED driver, timing functions and a host of integrated protection features. Figures 4, 5 and 6 show the functional block diagrams of the primary and secondary controllers with the most important features. Primary Controller The InnoMux2-EP IC has variable frequency CCM / CrM / DCM controller plus ZVS operation in DCM for enhanced efficiency and extended output power capability. For high-voltage input, the 1700 V InnoMUX2-EP (IMX2353F) has a variable frequency DCM only controller plus SR ZVS operation. This DCM ZVS operation achieves zero voltage switching on the primary switch using SR MOSFET. This reduces the capacitive turn on loss and improves efficiency. PRIMARY BYPASS Pin Regulator The PRIMARY BYPASS pin has an internal regulator that charges the PRIMARY BYPASS pin capacitor to V BPP by drawing current from the DRAIN pin whenever the power switch is off. The PRIMARY BYPASS pin is the internal supply voltage node. When the power switch is on, the device operates from the energy stored in the PRIMARY BYPASS pin capacitor. In addition, a shunt regulator clamps the PRIMARY BYPASS pin voltage to VSHUNT when current is provided to the PRIMARY BYPASS pin through an external resistor. This allows the InnoMux2-EP IC to be powered externally through a bias winding, decreasing the no-load consumption and enhancing low-standby-power operation. Primary Bypass ILIM Programming InnoMux2-EP ICs allow the user to adjust primary current limit (I LIM) settings through the selection of the PRIMARY BYPASS pin capacitor value. A ceramic capacitor can be used. There are 2 selectable capacitor sizes − 0.47 μF and 4.7 μF for setting standard and increased ILIM settings respectively. Primary Bypass Undervoltage Threshold The PRIMARY BYPASS pin undervoltage circuitry disables the power switch when the PRIMARY BYPASS pin voltage drops below ~4.5 V (= VBPP ‒ VBPP(H)) in steady-state operation. Once the PRIMARY BYPASS pin voltage falls below this threshold, it must rise to VBPP(SHUNT) to re-enable turn-on of the power switch. Primary Bypass Output Overvoltage Function The PRIMARY BYPASS pin has an OV protection feature with either a latching or an auto-reset response. A Zener diode in parallel with the resistor in series with the PRIMARY BYPASS pin capacitor is typically used to detect an overvoltage on the primary bias winding and activate the protection mechanism. In the event that the current into the PRIMARY BYPASS pin exceeds ISD, the device will latch-off or disable the power switch for a time t AR(OFF), after which time the controller will restart and attempt to return to regulation. Output OV protection is also included as an integrated feature on the secondary controller. Over-Temperature Protection The thermal shutdown circuitry senses the primary switch die temperature. The threshold is set to T SD with either a hysteretic or latch-off response. Hysteretic response: If the die temperature rises above the threshold, the power switch is disabled and remains disabled until the die temperature falls by TSD(H) at which point switching is re-enabled. A large amount of hysteresis is provided to prevent over-heating of the PCB due to a continuous fault condition. Latch-off response: If the die temperature rises above the threshold the power switch is disabled. The latching condition is reset by bringing the PRIMARY BYPASS pin below V BPP(RESET) or by going below the UNDER/OVER INPUT VOLTAGE pin UV(IUV-) threshold. Over-temperature protection is also included as an integrated feature on the secondary controller. Current Limit Operation The primary-side controller has a current limit threshold ramp that is inversely proportional to the time from the end of the previous primary switching cycle (i.e. from the time the primary switch turns off at the end of a switching cycle) to the next switching request.
the switching frequency (load) increases (Figure 12). continue to increase as load reduces. Figure 12. Normalized Primary Current vs. Switching Frequency. ~7 kHz with average frequency of ~100 kHz. the UNDER/OVER INPUT VOLTAGE pin UV(IUV-) threshold. In auto-restart, switching of the power MOSFET is disabled for t AR(OFF).
- Continuous secondary requests received at a rate that is above
the overload detection frequency (fOVL) for longer than 82 ms (tAR).
- No requests for switching cycles from the secondary for >t AR(SK).
controller will then restart. primary restarts after an auto-restart off-time. The auto-restart is reset as soon as an AC reset occurs. loads without extending the start-up time. and overvoltage sensing and protection. needed to clamp this pin voltage below 650 V. brown-in and below the overvoltage shutdown thresholds. at the beginning of the next switching cycle.
Rev. D 12/24 InnoMux2-EP www.power.com If no feedback signals are received during the auto-restart time (t AR), the primary goes into auto-restart mode. Under normal conditions, the secondary controller will power-up from the FORWARD pin or output voltage and take over control. From this point onwards the secondary controls switching. If the primary controller stops switching or does not respond to cycle requests from the secondary during normal operation (when the secondary has control), the handshake protocol is initiated to ensure that the secondary is ready to assume control once the primary begins to switch again. An additional handshake is also triggered if the secondary detects that the primary is providing more cycles than were requested. The most likely event that could require an additional handshake is when the primary stops switching as the result of a momentary line brown-out event. When the primary resumes operation, it will default to a start-up condition and attempt to detect handshake pulses from the secondary. If secondary does not detect that the primary responds to switching requests, or if the secondary detects that the primary is switching without cycle requests, the secondary controller will initiate a second handshake sequence. This provides additional protection against cross conduction of the SR FET while the primary is switching. This protection mode also prevents an output overvoltage condition in the event that the primary is reset while the secondary is still in control. Wait and Listen When the primary resumes switching after initial power-up recovery from an input line voltage fault (UV or OV) or an auto-restart event, it will assume control and require a successful handshake to relinquish control to the secondary controller. As an additional safety measure the primary will pause for an auto-restart on-time period, t AR (~82 ms), before switching. During this “wait” time, the primary will “listen” for secondary requests. If it sees two consecutive secondary requests, separated by ~30 μs, the primary will infer secondary control and begin switching in slave mode. If no pulses occur during the t AR “wait” period, the primary will begin switching under primary control until handshake pulses are received. Audible Noise Reduction Engine The InnoMux2-EP IC features an active audible noise reduction mode where by the controller (via a “frequency skipping” mode of operation) avoids the resonant band (where the mechanical structure of the power supply is most likely to resonate − increasing noise amplitude) between 7 kHz and 12 kHz – 142 μs and 83 μs. If a secondary controller switch request occurs within this time window from the last conduction cycle, the gate drive to the power switch is inhibited. The secondary controller includes an audible-noise-reduction engine. Frequency Soft-Start At start-up (before handshake) the primary controller is limited to a maximum switching frequency of f SW and 75% of the maximum programmed current limit at the switch-request frequency of 100 kHz. Secondary Controller The IC is powered by the 5 V (VBPS) regulator which is supplied by either an output or FORWARD pin. The SECONDARY BYPASS pin is connected to an external decoupling capacitor and fed internally from the regulator block. The FORWARD pin also connects to the detection block used for both handshaking and timing circuit to turn on and regulate the SR FET connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The FORWARD pin voltage is used to determine when to turn off the SR FET in discontinuous mode operation. In continuous conduction mode (CCM) the SR FET is turned off when a feedback pulse is sent to the primary to demand the next switching cycle, providing excellent synchronous operation, free of any overlap for the FET turn-off. The FORWARD detector also measures the FORWARD pin voltage during the primary on time, this feeds into the SR zero voltage switching control function. BPS Regulator The regulator limits the BPS pin to V BPS. The BP regulator can use VCV1 or VCV2/AS as its source. The source is automatically selected as follows:
- VCV1 is used if VCV1 pin > VBPS_VCV1, otherwise
- VCV2/AS is used if VCV2 pin > VBPS_VCV2 VCVHV/VLED can only be used as a source for BPS during start-up.During start-up, the FORWARD pin is also used as a source for BPS. This is provided to support start-up into heavy load and is not intended for continuous operation. The FORWARD pin needs to be a minimum of ≈8 V when the primary is on in order for this to function correctly. A 2.2 μF or 4.7 μF ceramic capacitor on the BPS pin is required. There are no stability requirements on the capacitor; the BPS regulator is unconditionally stable. BPS Regulator – Direct Power When VCV1 is 5 V (VCV5V_BPS) the BPS pin is automatically connected internally to the VCV1 pin, directly powering BPS instead of using the BPS linear regulator. This reduces power loss in the secondary controller and reduces standby power. This is automatically selected when VCV1 is VCV5V_BPS . High-Side MOSFET Drive The high-side selection MOSFETs are driven with a drive voltage that is 5 V above the given output using a capacitive drive approach. The capacitive drive approach benefits from easy level translation by use of a capacitor CDR capacitor-drive (CDR) . A regular refresh cycle to top up the charge on the CDR is needed when one of the switches has been on for a long time, as the charge on the CDR will otherwise slowly leak away. Refresh is also needed during start-up to allow the CDR to follow the output voltage when the output is being pulled up. The controller will perform refresh cycles when necessary by turning the selection MOSFET off and then back on.
forward voltage diode such as a Schottky diode should be used. and the capacitor will not be able to follow the output during start-up. well as to minimise energy required to drive the MOSFETs. voltage on the gate due to capacitive coupling. being turned off too early causing increased power loss. Figure 13. Synchronous Rectifier Driver Diagram. capacitance of less than 10 nF is recommended. on the SR gate due to capacitive coupling from the FORWARD pin. otherwise the controller will assume an SR FET is connected. that the VOR increases between V CV1 and VCV2 and between VCVHV/VLED. the same) reducing the output ripple for a given filter capacitance.
the secondary controller and this alone is sufficient to prevent lift. susceptible to peak charging or unintended energy delivery. been exceeded and it cannot maintain regulation. The thermal shutdown circuitry senses the secondary die temperature. The threshold is set to T SD(SEC). condition as hysteresis is not available. least 500 ns and FORWARD Pin voltage needs to be less than 100 V. Figure 16. DCM ZVS Mode Switching.
they remain disabled until DIM1 pin is above VADIM(ENABLE). DIM1 and DIM2 need to be high to enable the LEDs. described further in the Hybrid Dimming section. In this mode, the LED current is continuous (as in Analog Dimming). cycle to an analog current level. FPWMF(RANGE). Pulling DIM1 pin low disables the LEDs. DIM1 and DIM2 need to be high to enable the LEDs. further in the Hybrid Dimming section. by the duty cycle is adjusted. described in previous sections. go below 1% of ILED(MAX) (i.e. 10% analog and 10% PWM). Figure 19. InnoMux2-EP Dimming Modes.
the instant of turn-OFF of the primary switch. VCLM in Figure 20 is the combined clamp voltage including the spike. peak drain voltage well below 1700 V. (VOR) to main KP ≥ 1 for all input range conditions.
1700 V = VMAX(NON-REPETITIVE)
1360 V = VMAX(CONTINUOUS)
1000 VDC
Figure 20. Peak Drain Voltage for 1000 VDC Input Voltage.
Rev. D 12/24 InnoMux2-EP www.power.com Absolute Maximum Ratings 1,2 Notes: 1. All voltages referenced to SOURCE and secondary GROUND, TA = 25 °C. 2. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect product reliability. 3. Normally limited by internal circuitry. 4. 1/16” from case for 5 seconds. 7. Higher peak Drain current is allowed while Drain voltage is simultaneously less than 400 V. 8. Please refer to Figure 21 about maximum voltage and current combinations. Thermal Resistance Thermal Resistance: IMX2267 ‒ IMX2268 InSOP-24B IMX2278 ‒ IMX2270 InSOP-T28B IMX2174 ‒ IMX2177 InSOP-T28D IMX2378 ‒ IMX2370 InSOP-T28D IMX2353 InSOP-T28G Notes: 1. The case temperature is measured on the top of the package. 4. Highest thermal resistance corresponds to controllers with highest primary switch RDS(ON) and then reduces for controllers with lower RDS(ON) due to the larger device size. 5. The qJC is measured to the bottom of the package for exposed pad packages (InSOP-24B, InSOP-T28B) and to the top of the package for overmolded packages (InSOP-24D, InSOP-T28D, InSOP-T28G).
Rev. D 12/24 InnoMux2-EP www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Control Functions Start-Up Switching Frequency fSW TJ = 25 °C 23 25 27 kHz Jitter Modulation Frequency fM TJ = 25 °C fSW = 100 kHz 0.8 1.25 1.70 kHz Maximum On-Time tON(MAX) TJ = 25 °C 12.4 14.6 16.9 μs Minimum Primary Feedback Block-Out Timer tBLOCK tOFF(MIN) μs BPP Supply Current IS1 VBPP = VBPP + 0.1 V (MOSFET not Switching) TJ = 25 °C IMX2174 ‒ IMX2177, IMX2267 ‒ IMX2268 145 200 300 μAIMX2x78, IMX2x79, IMX2x70, IMX2353 145 266 425 IS2 VBPP = VBPP + 0.1 V (MOSFET Switching at fSREC) TJ = 25 °C IMX2174 0.44 0.58 0.83 mA IMX2175 0.59 0.79 1.10 IMX2176 0.77 1.02 1.38 IMX2177 0.90 1.20 1.73 IMX2267 0.77 1.03 1.38 IMX2268 0.90 1.20 1.75 IMX2x78 IMX2353 2.10 IMX2x79 2.95 IMX2x70 2.96 BPP Pin Charge Current ICH1 VBP = 0 V, TJ = 25 °C -1.75 -1.35 -0.88 mA ICH2 VBP = 4 V, TJ = 25 °C -5.98 -4.65 -3.32 BPP Pin Voltage VBPP TJ = 25 °C IMX2174 ‒ IMX2177 IMX2267 ‒ IMX2268 4.65 5 5.15 V IMX2x78, IMX2x79, IMX2x70, IMX2353 4.65 5 5.20 BPP Pin Voltage Hysteresis VBPP(H) TJ = 25 °C 0.39 V BPP Shunt Voltage VSHUNT IBPP = 2 mA 5.15 5.36 5.65 V BPP Power-Up Reset Threshold voltage VBPP(RESET) TJ = 25 °C 2.80 3.15 3.50 V UV/OV Pin Brown-In Threshold IUV+ TJ = 25 °C 23.6 25.8 28 μA UV/OV Pin Brown-Out Threshold IUV- TJ = 25 °C 20 23 24.5 μA Brown-Out Delay Time tUV- TJ = 25 °C 35 ms UV/OV Pin Line Overvoltage Threshold IOV+ TJ = 25 °C 106 115 118 μA UV/OV Pin Line Overvoltage Hysteresis IOV(H) TJ = 25 °C 7 μA
Rev. D 12/24 InnoMux2-EP www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Control Functions (cont.) UV/OV Pin Line Overvoltage Recovery Threshold IOV- TJ = 25 °C 100 μA Line Fault Protection UV/OV Pin Overvoltage Deglitch Filter tOV+ TJ = 25 °C 3 μs Circuit Protection Standard Current Limit (BPP) Capacitor = 0.47 μμF ILIMIT di/dt = 500 mA/μs TJ = 25 °C IMX2267C 1.84 2.0 2.16 A di/dt = 575 mA/μs TJ = 25 °C IMX2268C 2.08 2.3 2.52 di/dt = 650 mA/μs TJ = 25 °C IMX2278F 2.39 2.6 2.81 di/dt = 725 mA/μs TJ = 25 °C IMX2279F 2.63 2.9 3.19 di/dt = 848 mA/μs TJ = 25 °C IMX2270F 3.13 3.39 3.67 di/dt = 188 mA/μs TJ = 25 °C IMX2174F 0.697 0.750 0.803 di/dt = 288 mA/μs TJ = 25 °C IMX2175F 1.06 1.15 1.24 di/dt = 363 mA/μs TJ = 25 °C IMX2176F 1.33 1.45 1.57 di/dt = 400 mA/μs TJ = 25 °C IMX2177F 1.46 1.6 1.74 di/dt = 475 mA/μs TJ = 25 °C IMX2378F 1.77 1.9 2.03 di/dt = 550 mA/μs TJ = 25 °C IMX2379F 2.02 2.2 2.38 di/dt = 650 mA/μs TJ = 25 °C IMX2370F 2.35 2.6 2.85 di/dt = 475 mA/μs TJ = 25 °C IMX2353F 1.67 1.85 2.04 Increased Current Limit (BPP) Capacitor = 4.7 μμF ILIMIT+1 di/dt = 575 mA/μs TJ = 25 °C IMX2267C 2.10 2.3 2.50 A di/dt = 650 mA/μs TJ = 25 °C IMX2268C 2.39 2.6 2.81 di/dt = 728 mA/μs TJ = 25 °C IMX2278F 2.63 2.91 3.19 di/dt = 813 mA/μs TJ = 25 °C IMX2279F 2.97 3.25 3.53 di/dt = 950 mA/μs TJ = 25 °C IMX2270F 3.48 3.8 4.12 di/dt = 238 mA/μs TJ = 25 °C IMX2174F 0.86 0.95 1.04 di/dt = 350 mA/μs TJ = 25 °C IMX2175F 1.27 1.4 1.53 di/dt = 413 mA/μs TJ = 25 °C IMX2176F 1.51 1.65 1.79 di/dt = 463 mA/μs TJ = 25 °C IMX2177F 1.69 1.85 2.01 di/dt = 525 mA/μs TJ = 25 °C IMX2378F 1.92 2.1 2.28 di/dt = 613 mA/μs TJ = 25 °C IMX2379F 2.24 2.45 2.66
Rev. D 12/24 InnoMux2-EP www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Circuit Protection (cont.) Increased Current Limit (BPP) Capacitor = 4.7 μμF ILIMIT+1 di/dt = 725 mA/μs TJ = 25 °C IMX2370F 2.65 2.9 3.15 A di/dt = 475 mA/μs TJ = 25 °C IMX2353F 1.86 2.05 2.23 Overload Frequency fOVL TJ = 25 °C IMX2174 ‒ IMX2177 IMX2267 ‒ IMX2268 IMX2353 102 110 118 kHz IMX2x78, IMX2x79, IMX2x70 148 155 161 BYPASS Pin Latching Shutdown Threshold Current ISD TJ = 25 °C 6 7.5 11.3 mA Auto-Restart On-Time tAR TJ = 25 °C 75 82 89 ms Auto-Restart Trigger Skip Time tAR(SK) TJ = 25 °C See Note A 1.3 sec Auto-Restart Off-Time tAR(OFF) TJ = 25 °C 1.7 2 2.11 sec Short Auto-Restart Off-Time tAR(OFF)SH TJ = 25 °C 0.17 0.2 0.23 sec Output On-State Resistance RDS(ON) IMX2174 ID = ILIMIT+1 TJ = 25 °C 3.22 3.70 W TJ = 100 °C 4.99 5.74 IMX2175 ID = ILIMIT+1 TJ = 25 °C 1.95 2.24 TJ = 100 °C 3.02 3.47 IMX2176 ID = ILIMIT+1 TJ = 25 °C 1.34 1.54 TJ = 100 °C 2.08 2.39 IMX2177 ID = ILIMIT+1 TJ = 25 °C 1.20 1.38 TJ = 100 °C 1.86 2.14 IMX2267 ID = ILIMIT+1 TJ = 25 °C 1.02 1.17 TJ = 100 °C 1.58 1.82 IMX2268 ID = ILIMIT+1 TJ = 25 °C 0.86 0.99 TJ = 100 °C 1.34 1.55 IMX2x78 ID = ILIMIT+1 TJ = 25 °C 0.52 0.68 TJ = 100 °C 0.78 1.02 IMX2x79 ID = ILIMIT+1 TJ = 25 °C 0.35 0.44 TJ = 100 °C 0.49 0.62 IMX2x70 ID = ILIMIT+1 TJ = 25 °C 0.29 0.39 TJ = 100 °C 0.41 0.54 IMX2353 ID = ILIMIT+1 TJ = 25 °C 0.52 TBD TJ = 100 °C 0.73 TBD
Rev. D 12/24 InnoMux2-EP www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Output (cont.) Off-State Drain Leakage Current IDSS1 VBPP = VBPP + 0.1 V VDS = 80% Peak Drain Voltage TJ = 125 °C IMX2x6x IMX2x7x 200 μA IMX2353 200 IDSS2 VBPP = VBPP + 0.1 V VDS = 325 V TJ = 25 °C IMX2x6x IMX2x7x 15 IMX2353 15 Drain Supply Voltage 50 V Thermal Shutdown TSD See Note A 135 142 150 °C Thermal Shutdown Hysteresis TSD(H) 70 °C Secondary Maximum Secondary Frequency fSREQ TJ = 25 °C IMX2174 ‒ IMX2177 IMX2267 ‒ IMX2268 IMX2353 118 130 145 kHz IMX2x78, IMX2x79, IMX2x70 164 180 194 BPS Pin Current at No-Load ISNL TJ = 25 °C 3.2 mA BPS Pin Voltage VBPS 4.9 5.0 5.15 V BPS Pin Undervoltage Threshold VBPS(UVLO) 3.0 3.3 V BPS Pin Undervoltage Hysteresis VBPS(HYS) TJ = 25 °C 1.0 V Start-Up Ramp Time tSS(RAMP) 76 ms Minimum Off-Time tOFF(MIN) IMX2174 ‒ IMX2177 IMX2267 ‒ IMX2268 IMX2353 3.2 μs IMX2x78, IMX2x79, IMX2x70 2.5 BPS Direct Power VCV1 Range VCV5V(BPS) 4.65 5.0 5.45 V BPS Source Threshold VCV1 VBPS(VCV1) 7.4 7.9 9.3 V BPS Source Threshold VCV2/AS VBPS(VCV2) 5.3 5.5 5.8 V Minimum Voltage VCVHV/VLED VSTAYALIVE 6.55 8.0 9 V Threshold Shutdown TSD(SEC) See Note B 140 °C Recommended Output Voltage Range VCV1 Recommended Voltage Range VCV1 3 25 V VCV2 Recommended Voltage Range VCV2 5 25 V VCVHV Recommended Voltage Range VCVHV 9 53 V
Rev. D 12/24 InnoMux2-EP www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Recommended Output Voltage Range (cont.) VLED Recommended Voltage Range VLED 9 200 V Feedback FEEDBACK Pin Regulation Voltage VFB(REG) TJ = 25 °C 1.208 1.220 1.234 V Overvoltage Threshold VCV1, VCV2 VFB(OVP) TJ = 25 °C 112% of VFB(REG) V Overvoltage Threshold VCVHV VFB(OVP)VCVHV TJ = 25 °C 120% of VFB(REG) V Overvoltage Threshold VLED VFB(OVP)VLED TJ = 25 °C 116% of VFB(REG) V LV Shunt Threshold VLV(SHUNT) TJ = 25 °C 104% of VFB(REG) V Maximum LV Shunt Current ILV(SHUNT) 30 mA HV Shunt Threshold VHV(SHUNT) VCVHV 104% of VFB(REG) VLED 108% of VFB(REG) Maximum HV Shunt Current IHV(SHUNT) VCVHV 9 mA VLED < 50 V 8 mA VLED < 100 V 4.1 mA VLED < 150 V 3.3 mA VLED > 150 V 2.1 mA FEEDBACK Pin Short-Circuit VFB(OFF) TJ = 25 °C 48 mV Led Control Frequency Range PWM Dimming PWMF(RANGE) 90 1,000 Hz Frequency Range Filtered PWM Dimming FPWMF(RANGE) 90 30,000 HZ Minimum On-Time PWM Dimming tLED(ON)MIN 12 μs Minimum Off-Time PWM Dimming tLED(OFF)MIN Limits the maximum duty cycle before reach 100% 1 μs DIM1, DIM2 Pin Digital Input Thresholds VIL 0.8 V VIH 2.0 V DIM1 Pin Maximum Analog Dimming Voltage VADIM(MAX) 3.0 V DIM1 Pin Analog Dimming Enable Threshold VADIM(ENABLE) 100 120 mV
Rev. D 12/24 InnoMux2-EP www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Led Control (cont.) DIM1 Pin Analog Dimming Disable Threshold VADIM(DISABLE) 40 50 mV ISENSE Pin Voltage VISENSE DIM1 Pin = VADIM(MAX) (ADIM) DIM1 Pin = 100% Duty (FPWM) TJ = 25 °C 98 100 102 mV DIM1 Pin = 10% of VADIM(MAX) (ADIM) DIM1 Pin = 10% Duty (FPWM) TJ = 25 °C 8 10 12 mV IDRIVE Pin Saturation Detection VIDRIVE(SAT) TJ = 25 °C 85% of BPS V VSENSE Pin Short to VLED Pin Detection Threshold VSENSE(FAULT) TJ = 25 °C 97% of VLED V Selection MOSFET CDR1, CDR2 Pin Drive Voltage VCDR BPS V CDR1, CDR2 Pin Pull-Up Resistance TJ = 25 °C 4.75 5.4 5.8 W CDR1, CDR2 Pin Pull-Down Resistance TJ = 25 °C 4.75 5.4 6.5 W Refresh Pulse Width TREFRESH Note: Doubled during start-up 500 ns Synchronous Rectifier SR Pin Drive Voltage VSR BPS V SR FWD Pin Regulation Target VFWD(REG) -40 -85 mV SR Pin Pull-Up Speed ISR(PU) TJ = 25 °C CLOAD = 2 nF VFWD(REG) ‒ VFWD = +40 mV
10 V/μs
SR Pin Pull-Down Speed ISR(PD) TJ = 25 °C CLOAD = 2 nF VFWD(REG) ‒ VFWD = -30 mV -10 V/μs Rise Time tR TJ = 25 °C CLOAD = 2 nF 10-90% 50 ns Fall Time tF TJ = 25 °C CLOAD = 2 nF 10-90% 25 ns Output Pull-Up Resistance RPU TJ = 25 °C VBPS = 5.0 V ISR = 5 mA 6 7.9 9 W Output Pull-Down Resistance RPD TJ = 25 °C VBPS = 5.0 V ISR = 5 mA 6 7.8 9 W
Rev. D 12/24 InnoMux2-EP www.power.com NOTES: A. This parameter is derived from characterization. B. This parameter is guaranteed by design. C. To ensure correct current limit it is recommended that nominal 0.47 μF / 4.7 μF capacitors are used. In addition, the BPP capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization. Nominal BPP Pin Capacitor Value BPP Capacitor Minimum Value Tolerance Maximum 0.47 μF -60% +100% 4.7 μF -50% N/A Recommended to use at least 10 V / 0805 / X7R SMD MLCC.
Figure 21. Maximum Allowable Drain Current vs. Drain Voltage (PowiGaN Devices INN2x78F, INN2x79F, INN2x70F.
Rev. D 12/24 InnoMux2-EP www.power.com 0.50 Ref. 3.35 Ref.
5 Lead Tips
1.95 ± 0.05 6.77 ± 0.12 3.95 Max. 3.85 Ref. 0.45 Ref. 0.76 Ref. Seating Plane Seating Plane Standoff 0° – 8° Gauge Plane 0.29 Ref. 0.28 Ref. 0.25 0.20 Ref. 8.30 Max. 9.40 2X 0.10 C A 0.15 C
0.10 C B
13.63 7.90 Ref. 2.70 Ref. 0.15 C
0.25 M C A B
1.60 Max. Total Mounting Height 1.42 Ref. 7.43 ± 0.13 Detail A 0.10 C Coplanarity: 17 Leads
12 Lead Tips
0.30 0.20 0.15 0.00 0.30 0.18 0.81 0.51 1.45 1.25 Body Thickness 10.80 0.75 1 12 16X 24 13 A H C C 17X 3 4Pin #1 I.D. 2.71 2.59 PI-8105-122720 POD-InSOP-24B Rev D InSOP-24B (C Package) TOP VIEW SIDE VIEW BOTTOM VIEW END VIEW DETAIL A Notes: 1. Dimensioning and Tolerancing per ASME Y14.5M – 1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exculsive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include inter-lead flash or protrusions. 5. Controlling dimensions in millimeters. 6. Datums A & B to be determined at Datum H. 7. Exposed pad Min and Max dimensions include both size and positional tolerances. 8. Exposed pad hidden end-view shown for illustrative purposes to dimension creepage. 9. Creepage dimension includes package body side-contour dimensions as shown in Detail A.
10 Location of exposed metal tiebars: One at each
end of package as shown. Electrically connected to the exposed pad and wide lead.
Rev. D 12/24 InnoMux2-EP www.power.com NOTES: 1. Dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M–1994. 3. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 per side. 4. Dimensions noted are inclusive of plating thickness. 5. Does not include inter-lead flash or protrusions. 6. Datums A & B to be determined at Datum H. 7. This dimension is the nominal dimension between leadtips, not including plating, and not including metal protrusions. Metal-to-Metal distance (Creepage) is 3.20 mm minimum. 8. Exposed pad max dimensions include both size and positional tolerances. 9. Location of exposed metal tiebars: One at each end of package as shown. Electrically connected to the exposed pad and wide lead. PI-9730-031224 POD-inSOP-T28B Rev A POD-inSOP-T28B_A_032823 InSOP-T28B (F Package) 0.10 C H 18X0.30 0.20 A 4 5 0.48 Ref. All Four Corners
0.10 C A
9.40 4.07 Max. 8.25 Max. 4.07 Ref. 2.13 2.01 0.55 0.45 B 4 5Pin #1 I.D. 3.35 Ref. 0.38 Ref. 0.15 C 0.15 C 13.43
6 Lead Tips
14 Lead Tips
10.80 0.63 9 2X 1.315 Ref. Detail A 0.30 0.18
20 Leads
0.53 Ref. 0.15 0.00 Standoff 0.83 0.53 0° – 8° Gauge Plane Seating Plane 0.25 Body Thickness Coplanarity: 20 Leads Seating Plane 2.01 1.81 2.16 Total Max. Mounting Height C TOP VIEW BOTTOM VIEW DETAIL A SIDE VIEW END VIEW
Rev. D 12/24 InnoMux2-EP www.power.com TOP VIEW BOTTOM VIEW DETAIL A NOTES: 1. Dimensioning and Tolerancing per ASME Y14.5M – 1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include inter-lead flash or protrusions. 5. Controlling dimensions in millimeters. 6. Datums A & B to be determined at Datum H. 7. This dimension is the nominal dimension between leadtips, not including plating, and not including metal protrusions. Metal-to-Metal distance (Creepage) is 3.20 mm minimum. PI-9406-031224 POD-inSOP-T28D Rev B POD-inSOP-T28D_B_032623 InSOP-T28D (F Package) SIDE VIEW END VIEW B A 3 4 3 4 H 0° – 8° Gauge Plane Seating Plane 0.10 C Pin #1 I.D. 18X 3.35 Ref. 0.38 Ref. 0.48 Ref. All Four Corners 0.15 C 0.15 C 0.30 0.20 14 14 11 15 15 19 281928 13.43 9.40 0.25 2.13 2.01 0.55 0.45 0.53 Ref. 0.25 0.10 Standoff 0.83 0.53 10.80 0.63 Body Thickness Coplanarity: 20 Leads Seating Plane 1.315 Ref. Detail A 2.01 1.81 2.26 Total 0.30 0.18 Max. Mounting Height C
Rev. D 12/24 InnoMux2-EP www.power.com TOP VIEW BOTTOM VIEW DETAIL A SIDE VIEW END VIEW NOTES: 1. Dimensioning and Tolerancing per ASME Y14.5M – 1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include inter-lead flash or protrusions. 5. Controlling dimensions in millimeters. 6. Datums A & B to be determined at Datum H. 7. This dimension is the nominal dimension between leadtips, not including plating, and not including metal protrusions. Metal-to-Metal distance (Creepage) is 4.95 mm minimum. PI-9731-042123 POD-inSOP-T28G Rev C POD-inSOP-T28G_C_040423 InSOP-T28G Seating Plane Pin #1 I.D. 17X 5.10 Ref. 0.38 Ref. 0.48 Ref. All Four Corners 0.15 C 0.15 C 0.10 C 0.30 0.20 14 14 11 15 15 18 281828 13.43 9.40 0.25 H 1.01 0.89 0.55 0.45 0.53 Ref. 0.25 0.10 Standoff 0.83 0.53 10.80 0.63 3 4 3 4 A B Body Thickness Coplanarity: 19 Leads Seating Plane 1.315 Ref. Detail A 2.01 1.81 2.26 Total 0.30 0.18
19 Leads
Max. Mounting Height C Gauge Plane 0° – 8°
Rev. D 12/24 InnoMux2-EP www.power.com IMX2066C M5J156N 2413 H411 PI-8617a-032824 InSOP-24B PACKAGE MARKING A B C D E A. Power Integrations Registered Trademark B. Assembly Date Code (last two digits of year followed by 2-digit work week) C. Product Identification (Part #/Package Type) D. Lot Identification Code E. Test Sublot and Feature Code
Rev. D 12/24 InnoMux2-EP www.power.com PI-9756a-032824 InSOP-T28B InSOP-T28D A. Power Integrations Registered Trademark B. Assembly Date Code (last two digits of year (YY) followed by 2-digit work week (WW) C. Product Identification (Part #/Package Type) D. Lot Identification Code E. Pin 1 Indicator F. Supply Chain Flow (Foundry / Assembly Location (X)) and Feature Code PACKAGE MARKING A E B C D F IMX2370F 4D842A1 2413
1 Hxxx
Rev. D 12/24 InnoMux2-EP www.power.com PI-9750a-080524 InSOP-T28G A B C D IMX2353F %%4D842A1 A. Power Integrations Registered Trademark B. Assembly Date Code (last two digits of year (YY) followed by 2-digit work week (WW)) C. Product Identification (Part #/Package Type) D. Lot Identification Code E. Pin 1 Indicator E PACKAGE MARKING 2210 A H051
Rev. D 12/24 InnoMux2-EP www.power.com ESD and Latch-Up Table Test Conditions Results Latch-up at 125 °C JESD78D > ±100 mA or > 1.5 × VMAX on all pins Human Body Model ESD ANSI/ESDA/JEDEC JS-001-2014 > ±2000 V on all pins Charge Device Model ESD ANSI/ESDA/JEDEC JS-002-2014 > ±500 V on all pins Part Number MSL Rating IMX2267C 3 IMX2268C 3 IMX2278F 3 IMX2279F 3 IMX2270F 3 IMX2174F 3 IMX2175F 3 IMX2176F 3 IMX2177F 3 IMX2378F 3 IMX2379F 3 IMX2370F 3 IMX2353F 3 Part Ordering Information
- InnoMux2 Family
- InnoMux2-EP Series Number
- Package Identifier C InSOP-24B F InSOP-T28B F InSOP-T28D F InSOP-T28G
- Tape & Reel and Other Options TL Tape & Reel, 2 k pcs per reel InSOP-24B, 1.8 k pcs per reel InSOP-T28B, InSOP-T28D and InSOP-T28GIMX 2065 C - TL Feature Code Table IMX2353F Only Feature Code H415 H417 Output Configurations 2 CV 3 CV Feedback Resistors External External ILIM Selectable YES YES Primary Fault Response Auto-Restart Auto-Restart Secondary Fault Response Auto-Restart Auto-Restart Auto-Restart VOUT(AR) = 90% of VOUT(NOM) VOUT(AR) = 90% of VOUT(NOM) Over Power Protection NO All 3 Ouputs
B Production release. Power table on page 2 has been updated to include O/P power for PFC input and Table 2 to include option features. 06/24 C Added IMX2353F 1700 V part. 10/24 D Added H Code H417 and updated power output 1700 V PN. 12/24 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at https://www.power.com/company/intellectual-property-licensing/. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC, HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2023, Power Integrations, Inc. World Headquarters
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