IMX2065C

IMX2065C POWERINT | Alldatasheet

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Technical content

Figure 3. InnoMux2-BL Primary Block Diagram. Table 2. Configuration Options.

Connection to IML204DG driver for the analog dimming reference. Should be connected to REF pin on the IML204DG IC. be connected to EN pin on the IML204DG IC. Connection to IML204DG to observe the current source drain voltage. connected to VSENSE pin on the IML204DG IC. Gate driver for external selection MOSFET for V CV1 output. Connection for external bypass capacitor for the secondary IC supply. Gate driver for external SR MOSFET. power for the secondary-side controller during start-up. voltage regulation and protection. voltage regulation and protection. Leave open. Should not be connected to any other pins. Leave open or connect to SOURCE pin or BPP pin. reference for primary BYPASS pin. Power switch drain connection.

11 VLED

10 VCV1

9 FWD

7 DIM1

6 BPS

5 CDR1

4 VSENSE

3 ENOUT

2 GND

1 REFOUT

Figure 6. InnoMux2-BL InSOP-24D 1CV+4LED Single Dimming with SR Pin

connected between this and the GND pin. regulation of voltage to minimize MOSFET power dissipation. Gate driver for external selection MOSFET for V CV1 output. Connection for external bypass capacitor for the secondary IC supply. Gate driver for external SR MOSFET. power for the secondary-side controller during start-up. voltage regulation and protection. voltage regulation and protection. Leave open. Should not be connected to any other pins. Leave open or connect to SOURCE pin or BPP pin. reference for primary BYPASS pin. Power switch drain connection.

3 IDRIVE

1 ISENSE

Figure 7. InnoMux2-BL InSOP-24D 1CV+1LED Single Dimming with SR Pin

Rev. C 09/24 InnoMux2-BL www.power.com InnoMux2-BL Functional Description The InnoMux2-BL IC combines a high-voltage power switch, along with both primary-side and secondary-side controllers in one device. The InnoMux2-BL architecture incorporates a novel inductive coupling feedback scheme using the package lead frame and bond wires to provide a safe, reliable, and low-cost means to accurately communi - cate power requests from the secondary controller to the primary controller. The primary controller on InnoMux2-BL IC is a quasi-resonant (QR) flyback controller that has the ability to operate in continuous conduction mode (CCM). The controller uses a variable current control scheme. The primary consists of a jitter oscillator; a receiver circuit magnetically coupled to the secondary controller, a current limit controller, 5 V regulator on the PRIMARY BYPASS pin, audible noise reduction engine, bypass overvoltage detection circuit, a lossless input line sensing circuit, current limit selection circuitry, overvoltage protection, leading edge blanking, secondary output diode / SR MOSFET short protection circuit and a 650 V power switch. The secondary controller consists of a transmitter circuit that is magnetically coupled to the primary receiver, multi-output controller for regulating up to three outputs independently, 5 V regulator on the SECONDARY BYPASS pin, synchronous rectifier (SR) MOSFET driver, high-side MOSFET drivers, shunts to prevent individual outputs from rising in abnormal loading conditions, single string LED driver, timing functions and a host of integrated protection features. Figures 3, 4 and 5 show the functional block diagrams of the primary and secondary controllers with the most important features. Primary Controller InnoMux2-BL IC has variable frequency CCM / CrM / DCM controller plus ZVS operation in DCM for enhanced efficiency and extended output power capability. PRIMARY BYPASS Pin Regulator The PRIMARY BYPASS pin has an internal regulator that charges the PRIMARY BYPASS pin capacitor to V BPP by drawing current from the DRAIN pin whenever the power switch is off. The PRIMARY BYPASS pin is the internal supply voltage node. When the power switch is on, the device operates from the energy stored in the PRIMARY BYPASS pin capacitor. In addition, a shunt regulator clamps the PRIMARY BYPASS pin voltage to VSHUNT when current is provided to the PRIMARY BYPASS pin through an external resistor. This allows the InnoMux2-BL IC to be powered externally through a bias winding, decreasing the no-load consumption and enhancing low-standby-power operation. Primary Bypass ILIM Programming InnoMux2-BL ICs allow the user to adjust primary current limit (I LIM) settings through the selection of the PRIMARY BYPASS pin capacitor value. A ceramic capacitor can be used. There are 2 selectable capacitor sizes − 0.47 μF and 4.7 μF for setting standard and increased ILIM settings respectively. Primary Bypass Undervoltage Threshold The PRIMARY BYPASS pin undervoltage circuitry disables the power switch when the PRIMARY BYPASS pin voltage drops below ~4.5 V (= VBPP ‒ VBPP(H)) in steady-state operation. Once the PRIMARY BYPASS pin voltage falls below this threshold, it must rise to VBPP(SHUNT) to re-enable turn-on of the power switch. Primary Bypass Output Overvoltage Function The PRIMARY BYPASS pin has an OV protection feature with either a latching or an auto-reset response. A Zener diode in parallel with the resistor in series with the PRIMARY BYPASS pin capacitor is typically used to detect an overvoltage on the primary bias winding and activate the protection mechanism. In the event that the current into the PRIMARY BYPASS pin exceeds ISD, the device will latch-off or disable the power switch for a time t AR(OFF), after which time the controller will restart and attempt to return to regulation. Output OV protection is also included as an integrated feature on the secondary controller. Over-Temperature Protection The thermal shutdown circuitry senses the primary switch die temperature. The threshold is set to T SD with either a hysteretic or latch-off response. Hysteretic response: If the die temperature rises above the threshold, the power switch is disabled and remains disabled until the die temperature falls by TSD(H) at which point switching is re-enabled. A large amount of hysteresis is provided to prevent over-heating of the PCB due to a continuous fault condition. Latch-off response: If the die temperature rises above the threshold the power switch is disabled. The latching condition is reset by bringing the PRIMARY BYPASS pin below V BPP(RESET) or by going below the UNDER/OVER INPUT VOLTAGE pin UV(IUV-) threshold. Over-temperature protection is also included as an integrated feature on the secondary controller. Current Limit Operation The primary-side controller has a current limit threshold ramp that is inversely proportional to the time from the end of the previous primary switching cycle (i.e. from the time the primary switch turns off at the end of a switching cycle) to the next switching request.

the switching frequency (load) increases (Figure 6). continue to increase as load reduces. Figure 8. Normalized Primary Current vs. Switching Frequency. ~7 kHz with average frequency of ~100 kHz. below the UNDER/OVER INPUT VOLTAGE pin UV(IUV-) threshold. In auto-restart, switching of the power MOSFET is disabled for t AR(OFF).

1. Continuous secondary requests received at a rate that is above

the overload detection frequency (fOVL) for longer than 82 ms (tAR).

1. No requests for switching cycles from the secondary for >t AR(SK).

controller will then restart. primary restarts after an auto-restart off-time. The auto-restart is reset as soon as an AC reset occurs. loads without extending the start-up time. and overvoltage sensing and protection. OVER INPUT VOLTAGE pin to primary GND. brown-in and below the overvoltage shutdown thresholds. at the beginning of the next switching cycle.

Rev. C 09/24 InnoMux2-BL www.power.com If no feedback signals are received during the auto-restart time (t AR), the primary goes into auto-restart mode. Under normal conditions, the secondary controller will power-up from the FORWARD pin or output voltage and take over control. From this point onwards the secondary controls switching. If the primary controller stops switching or does not respond to cycle requests from the secondary during normal operation (when the secondary has control), the handshake protocol is initiated to ensure that the secondary is ready to assume control once the primary begins to switch again. An additional handshake is also triggered if the secondary detects that the primary is providing more cycles than were requested. The most likely event that could require an additional handshake is when the primary stops switching as the result of a momentary line brown-out event. When the primary resumes operation, it will default to a start-up condition and attempt to detect handshake pulses from the secondary. If secondary does not detect that the primary responds to switching requests, or if the secondary detects that the primary is switching without cycle requests, the secondary controller will initiate a second handshake sequence. This provides additional protection against cross conduction of the SR FET while the primary is switching. This protection mode also prevents an output overvoltage condition in the event that the primary is reset while the secondary is still in control. Wait and Listen When the primary resumes switching after initial power-up recovery from an input line voltage fault (UV or OV) or an auto-restart event, it will assume control and require a successful handshake to relinquish control to the secondary controller. As an additional safety measure the primary will pause for an auto-restart on-time period, t AR (~82 ms), before switching. During this “wait” time, the primary will “listen” for secondary requests. If it sees two consecutive secondary requests, separated by ~30 μs, the primary will infer secondary control and begin switching in slave mode. If no pulses occur during the t AR “wait” period, the primary will begin switching under primary control until handshake pulses are received. Audible Noise Reduction Engine The InnoMux2-BL IC features an active audible noise reduction mode where by the controller (via a “frequency skipping” mode of opera - tion) avoids the resonant band (where the mechanical structure of the power supply is most likely to resonate − increasing noise amplitude) between 7 kHz and 12 kHz – 142 μs and 83 μs. If a secondary controller switch request occurs within this time window from the last conduction cycle, the gate drive to the power switch is inhibited. The secondary controller includes an audible-noise-reduction engine. Frequency Soft-Start At start-up (before handshake) the primary controller is limited to a maximum switching frequency of f SW and 75% of the maximum programmed current limit at the switch-request frequency of 100 kHz. Secondary Controller The IC is powered by the 5 V (VBPS) regulator which is supplied by either an output or FORWARD pin. The SECONDARY BYPASS pin is connected to an external decoupling capacitor and fed internally from the regulator block. The FORWARD pin also connects to the detection block used for both handshaking and timing circuit to turn on and regulate the SR FET connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The FORWARD pin voltage is used to determine when to turn off the SR FET in discontinuous mode operation. In continuous conduction mode (CCM) the SR FET is turned off when a feedback pulse is sent to the primary to demand the next switching cycle, providing excellent synchronous operation, free of any overlap for the FET turn-off. The FORWARD detector also measures the FORWARD pin voltage during the primary on time, this feeds into the SR zero voltage switching control function. BPS Regulator The regulator limits the BPS pin to V BPS. The source is automatically selected as follows:

• VCV1 is used if VCV1 pin > VBPS_VCV1, otherwise
• VLED is used. VLED can only be used as a source for BPS during start-up. During start-up, the FORWARD pin is also used as a source for BPS. This is provided to support start-up into heavy load and is not intended for continuous operation. The FORWARD pin needs to be a minimum of ≈8 V when the primary is on in order for this to function correctly. A 2.2 μF or 4.7 μF ceramic capacitor on the BPS pin is required. There are no stability requirements on the capacitor; the BPS regulator is unconditionally stable. BPS Regulator – Direct Power When VCV1 is 5 V (VCV5V_BPS) the BPS pin is automatically connected internally to the VCV1 pin, directly powering BPS instead of using the BPS linear regulator. This reduces power loss in the secondary controller and reduces standby power. This is automatically selected when VCV1 is VCV5V_BPS . High-Side MOSFET Drive The high-side selection MOSFETs are driven with a drive voltage that is 5 V above the given output using a capacitive drive approach. The capacitive drive approach benefits from easy level translation by use of a capacitor CDR Capacitor-Drive (CDR) . A regular refresh cycle to top up the charge on the CDR is needed when one of the switches has been on for a long time, as the charge on the CDR will otherwise slowly leak away. Refresh is also needed during start-up to allow the CDR to follow the output voltage when the output is being pulled up. The controller will perform refresh cycles when necessary by turning the selection MOSFET off and then back on.

forward voltage diode such as a Schottky diode should be used. and the capacitor will not be able to follow the output during start-up. well as to minimise energy required to drive the MOSFETs. gate due to capacitive coupling. too early causing increased power loss. Figure 9. Synchronous Rectifier Driver Diagram. capacitance of less than 10 nF is recommended. on the SR gate due to capacitive coupling from the FORWARD pin. otherwise the controller will assume an SR FET is connected. the primary and initiate auto-restart. by turning on the selection MOSFET in series with the CV1 output. energy delivery to the LED output. The InnoMux2-BL IC has enhanced features for audible noise reduction. dent on the relative loading of the outputs. the same) reducing the output ripple for a given filter capacitance.

the secondary controller and this alone is sufficent to prevent lift. turned on when the sensed voltage exceeds V HV(SHUNT). The VCV1 and VLED outputs have a maximum power protection feature. and it cannot maintain regulation. limit that has a configurable level. will auto restart or latch-off. Table 3. Power Limit Options. The thermal shutdown circuitry senses the secondary die temperature. The threshold is set to T SD(SEC). condition as hysteresis is not available. continuous conduction mode (CCM). least 500 ns and FORWARD pin voltage needs to be less than 100 V. quasi-resonant switching is used. Figure 12. DCM ZVS Mode Switching. on. The InnoMux2-BL IC has an option to only allow DCM switching. recommended to enable this feature. controller by regulating the output voltage driving the LED strings (VLED). described in the IML204DG data sheet.

Rev. C 09/24 InnoMux2-BL www.power.com Absolute Maximum Ratings 1,2 Notes: 1. All voltages referenced to SOURCE and Secondary GROUND, TA = 25 °C. 2. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect product reliability. 3. Normally limited by internal circuitry. 4. 1/16” from case for 5 seconds. Thermal Resistance Thermal Resistance: IMX2065C IMX2066C Notes: 1. The case temperature is measured on the top of the package.

Rev. C 09/24 InnoMux2-BL www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Control Functions Start-Up Switching Frequency fSW TJ = 25 °C 23 25 27 kHz Jitter Modulation Frequency fM TJ = 25 °C fSW = 100 kHz 0.8 1.25 1.70 kHz Maximum On-Time tON(MAX) TJ = 25 °C 12.4 14.6 16.9 μs Minimum Primary Feedback Block-Out Timer tBLOCK tOFF(MIN) μs BPP Supply Current IS1 VBPP = VBPP + 0.1 V (MOSFET not Switching) TJ = 25 °C 145 200 300 μA IS2 VBPP = VBPP + 0.1 V (MOSFET Switching at fOSC) TJ = 25 °C IMX2065 0.65 1.03 mA IMX2066 0.86 1.21 BPP Pin Charge Current ICH1 VBP = 0 V, TJ = 25 °C -1.75 -1.35 -0.88 mA ICH2 VBP = 4 V, TJ = 25 °C -5.98 -4.65 -3.32 BPP Pin Voltage VBPP TJ = 25 °C VBP = 0 V 4.65 4.90 5.15 V BPP Pin Voltage Hysteresis VBPP(H) TJ = 25 °C 0.39 V BPP Shunt Voltage VSHUNT IBPP = 2 mA 5.15 5.36 5.65 V BPP Power-Up Reset Threshold voltage VBPP(RESET) TJ = 25 °C 2.80 3.15 3.50 V UV/OV Pin Brown-In Threshold IUV+ TJ = 25 °C 23.6 25.8 28 μA UV/OV Pin Brown-Out Threshold IUV- TJ = 25 °C 20.0 23 24.5 μA Brown-Out Delay Time tUV- TJ = 25 °C 35 ms UV/OV Pin Line Overvoltage Threshold IOV+ TJ = 25 °C 106 115 118 μA UV/OV Pin Line Overvoltage Hysteresis IOV(H) TJ = 25 °C 7 μA UV/OV Pin Line Overvoltage Recovery Threshold IOV- TJ = 25 °C 100 μA Line Fault Protection UV/OV Pin Overvoltage Deglitch Filter tOV+ TJ = 25 °C 3 μs

Rev. C 09/24 InnoMux2-BL www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Circuit Protection Standard Current Limit (BPP) Capacitor = 0.47 μμF ILIMIT di/dt = 238 mA/μs TJ = 25 °C IMX2065 0.88 0.95 1.02 A di/dt = 313 mA/μs TJ = 25 °C IMX2066 1.16 1.25 1.34 Increased Current Limit (BPP) Capacitor = 4.7 μμF ILIMIT+1 di/dt = 288 mA/μs TJ = 25 °C IMX2065 1.05 1.15 1.25 A di/dt = 363 mA/μs TJ = 25 °C IMX2066 1.32 1.45 1.58 Overload Frequency fOVL TJ = 25 °C 102 110 118 kHz BYPASS Pin Latching Shutdown Threshold Current ISD TJ = 25 °C 6 7.5 11.3 mA Auto-Restart On-Time tAR TJ = 25 °C 75 82 89 ms Auto-Restart Trigger Skip Time tAR(SK) TJ = 25 °C See Note A 1.3 sec Auto-Restart Off-Time tAR(OFF) TJ = 25 °C 1.7 2 2.11 sec Short Auto-Restart Off-Time tAR(OFF)SH TJ = 25 °C See Note B 0.17 0.2 0.23 sec Output On-State Resistance RDS(ON) IMX2065 ID = ILIMIT+1 TJ = 25 °C 1.95 2.24 W TJ = 100 °C 3.02 3.47 IMX2066 ID = ILIMIT+1 TJ = 25 °C 1.30 1.50 TJ = 100 °C 2.02 2.32 Off-State Drain Leakage Current IDSS1 VBPP = VBPP + 0.1 V VDS = 80% Peak Drain Voltage TJ = 125 °C 200 μA IDSS2 VBPP = VBPP + 0.1 V VDS = 325 V TJ = 25 °C Drain Supply Voltage 50 V Thermal Shutdown TSD See Note A 135 142 150 °C Thermal Shutdown Hysteresis TSD(H) 70 °C

Rev. C 09/24 InnoMux2-BL www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Secondary Maximum Secondary Frequency fSREQ TJ = 25 °C 118 130 145 kHz BPS Pin Current at No-Load ISNL TJ = 25 °C 3.2 mA BPS Pin Voltage VBPS 4.9 5.0 5.15 V BPS Pin Undervoltage Threshold VBPS(UVLO) 3.0 3.3 V BPS Pin Undervoltage Hysteresis VBPS(HYS) TJ = 25 °C 1.0 V Start-Up Ramp Time tSS(RAMP) 76 ms Minimum Off-Time tOFF(MIN) 3.2 μs BPS Direct Power VCV1 Range VCV5V(BPS) 4.65 5.0 5.45 V BPS Source Threshold VCV1 VBPS(VCV1) 7.4 7.9 9.3 V Minimum Voltage VLED VSTAYALIVE 6.55 8.0 9 V Threshold Shutdown TSD(SEC) See Note B 140 °C Recommended Output Voltage Range VCV1 Recommended Voltage Range VCV1 5 25 V VLED Recommended Voltage Range VLED 9 150 V Feedback FEEDBACK Pin Regulation Voltage VFB(REG) TJ = 25 °C 1.208 1.220 1.234 V Overvoltage Threshold VCV1 VFB(OVP) TJ = 25 °C 112% of VFB(REG) V Overvoltage Threshold VLED VFB(OVP)VLED TJ = 25 °C 116% of VFB(REG) V LV Shunt Threshold VLV(SHUNT) TJ = 25 °C 104% of VFB(REG) V

Rev. C 09/24 InnoMux2-BL www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Feedback (cont.) Maximum LV Shunt Current ILV(SHUNT) 20 30 mA HV Shunt Threshold VHV(SHUNT) VLED 108% of VFB(REG) Maximum HV Shunt Current IHV(SHUNT) VLED < 50 V 8 mA VLED < 100 V 4.1 mA VLED < 150 V 3.3 mA VLED > 150 V 2.1 mA Led Control Frequency Range PWM Dimming PWMF(RANGE) 90 30,000 Hz Frequency Range Filtered PWM Dimming FPWMF(RANGE) 90 30,000 HZ Minimum On-Time PWM Dimming tLED(ON)MIN 5 μs Frequency Range PWM Dimming PWMF(RANGE) H411 variant only 90 1,000 Hz Frequency Range Filtered PWM Dimming FPWMF(RANGE) H411 variant only 90 30,000 Hz Minimum On-Time PWM Dimming tLED(ON)MIN H411 variant only 12 μs Minimum Off-Time PWM Dimming tLED(OFF)MIN Limits the maximum duty cycle before reach 100% 1 μs DIM1 Pin Digital Input Thresholds VIL 0.8 V VIH 2.0 V DIM1 Pin Maximum Analog Dimming Voltage VADIM(MAX) 3.0 V DIM1 Pin Analog Dimming Enable Threshold VADIM(ENABLE) 100 120 mV DIM1 Pin Analog Dimming Disable Threshold VADIM(DISABLE) 40 50 mV VSENSE Pin Short to VLED Pin Detection Threshold VSENSE(FAULT) TJ = 25 °C 97% of VLED V ISENSE Pin Voltage VSENSE DIM1 Pin = VADIM(MAX) (ADIM) DIM1 Pin = 100% Duty (FPWM) TJ = 25 °C 98 100 102 mV DIM1 Pin = 10% of VADIM(MAX) (ADIM) DIM1 Pin = 10% Duty (FPWM) TJ = 25 °C 8 10 12 IDRIVE Pin Saturation Detection VIDRIVE(SAT) TJ = 25 °C 85% of BPS V

Rev. C 09/24 InnoMux2-BL www.power.com Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Selection MOSFET CDR1 Pin Drive Voltage VCDR BPS V CDR1 Pin Pull-Up Resistance TJ = 25 °C 4.75 5.4 5.8 W CDR1 Pin Pull-Down Resistance TJ = 25 °C 4.75 5.4 6.5 W Refresh Pulse Width TREFRESH Note: Doubled during start-up 500 ns Synchronous Rectifier 1 SR Pin Drive Voltage VSR BPS V SR FWD Pin Regulation Target VFWD(REG) -40 -85 mV SR Pin Pull-Up Speed ISR(PU) TJ = 25 °C CLOAD = 2 nF VFWD(REG) - VFWD = +40 mV

10 V/μs

SR Pin Pull-Down Speed ISR(PD) TJ = 25 °C CLOAD = 2 nF VFWD(REG) - VFWD = -30 mV -10 V/μs Rise Time tR TJ = 25 °C CLOAD = 2nF 10-90% 50 ns Fall Time tF TJ = 25 °C CLOAD = 2nF 10-90% 25 ns Output Pull-Up Resistance RPU TJ = 25 °C VBPS = 5.0 V ISR = 5 mA 6 7.9 9 W Output Pull-Down Resistance RPD TJ = 25 °C VBPS = 5.0 V ISR = 5 mA 6 7.8 9 W NOTES: A. This parameter is derived from characterization. B. This parameter is guaranteed by design. C. To ensure correct current limit it is recommended that nominal 0.47 μF / 4.7 μF capacitors are used. In addition, the BPP capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization. Nominal BPP Pin Capacitor Value BPP Capacitor Minimum Value Tolerance Maximum 0.47 μF -60% +100% 4.7 μF -50% N/A Recommended to use at least 10 V / 0805 / X7R SMD MLCC.

Rev. C 09/24 InnoMux2-BL www.power.com

5 Lead Tips

12 Lead Tips

Pin #1 I.D. 16X Ref. Seating Plane Coplanarity: 17 LeadsBody Thickness Seating Plane C Standoff Gauge Plane 3.35 [0.132] Ref. 9.40 [0.370] 0.15 [0.006] C 0.10 [0.004] C 0.15 [0.006] C 0.10 [0.004] C A 0.75 [0.030] 0.25 [0.010] M C A B 0.10 [0.004] C B 0.81 0.032 0.51 0.020 0.25 0.010 0.10 0.004 1.45 0.057 1.25 0.049 0.30 0.012 0.18 0.007 1.32 [0.052] Ref. Detail A 17X 0.30 0.012 0.20 0.008 2.71 0.107 2.59 0.102 3 4 242X 13 3 4 H C A TOP VIEW BOTTOM VIEW SIDE VIEW END VIEW PCB PAD LAYOUT DETAIL A 0° – 8° 1.60 [0.063] Max. Total Mounting Height Notes: 1. Dimensioning and Tolerancing per ASME Y14.5M – 1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 [0.007] per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include inter-lead flash or protrusions. 5. Controlling dimensions in millimeters [inches]. 6. Datums A & B to be determined at Datum H. PI-8106-052620 POD-inSOP-24D Rev C POD-inSOP-24D_C_052920 InSOP-24D 4.80 [0.189] 7.50 [0.295] 8.25 [0.325] 6.75 [0.266] 12.72 [0.501] 0.75 [0.030] 0.41 [0.016] 1.58 [0.062] 1.58 [0.062] 2.81 [0.111] 8.25 [0.325]

Rev. C 09/24 InnoMux2-BL www.power.com PI-8727r-110923 InSOP-24D A. Power Integrations Registered Trademark B. Assembly Date Code (last two digits of year followed by 2-digit work week) C. Product Identification (Part #/Package Type) D. Lot Identification Code E. Test Sublot and Feature Code PACKAGE MARKING A B E C D IMX2065C 01M6J542A 1738

1 H401

Rev. C 09/24 InnoMux2-BL www.power.com ESD and Latch-Up Table Test Conditions Results Latch-up at 125 °C JESD78D > ±100 mA or > 1.5 × VMAX on all pins Human Body Model ESD ANSI/ESDA/JEDEC JS-001-2014 > ±2000 V on all pins Charge Device Model ESD ANSI/ESDA/JEDEC JS-002-2014 > ±500 V on all pins MSL Table Part Number MSL Rating IMX2065C 3 IMX2066C 3 Feature Code Option Part Number Feature Code Feature IMX2065C H411 1 CV and 1 CC Output IMX2066C H411 1 CV and 1 CC output Part Ordering Information

• InnoMux2 Family
• InnoMux2-BL Series Number
• Package Identifier C InSOP-24D
• Feature Code
• Tape & Reel and Other Options TL Tape & Reel, 2 k pcs per reel.IMX 2065 C - H411 - TL

B Production release. 03/24 C Figure description update on page 6. 09/24 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at https://www.power.com/company/intellectual-property-licensing/. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC, HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2023, Power Integrations, Inc. World Headquarters

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