IMX111U

IMX101J POWER-INTEGRATIONS | Alldatasheet

Document overview

• PDF pages: 22

Technical content

www.power.com November 2020

2 Constant Voltage and 4 Channel Dimming

LED Backlight CC Controller This Product is Covered by Patents and/or Pending Patent Applications. Product Highlights CV and 4-Channel LED Backlight Controller

• Eliminates buck and LED backlight boost converters
• On e or two constant voltage outputs
• In dependently regulated outputs with instantaneous transient response ±5% CV on 0%-100%-0% load step
• Typ ical output voltages
• On e CV mode: 5 V to 22 V
• Tw o CV mode: 5 V and 12 V to 22 V
• 1- 4 string LED backlight
• 3% m atching accuracy for LED strings
• An alog, PWM, sequenced PWM and filtered PWM operation
• Up t o 100 V string voltage / up to 960 mA total string current
• Up t o 2:1 LED string voltage range Advanced Protection / Safety Features
• Individual overload protection for all outputs
• St ring imbalanced / short / open protection
• Ou tput overvoltage set for auto-restart Convenient Packages
• 28-Lead HSOP for single-sided wave soldered PCBs or small 28-Lead Q FN (5x5 mm Body) for compact multilayer designs

Applications

• ENERGY STAR 8, CEC, and 2021/2023 EU labeling for monitors and T Vs

Figure 1. Ty pical Schematic. Table 1. In noMux Controller Part Numbers. Figure 2. Left – I ght – InnoMux in HSOP-28, Wave Solder Process.

Description

When paired with InnoSwitch3-MX, InnoMux dramatically improves the system ef ficiency of mo nitors an d TV s by eli minating th e bo ost an d buc k converter stages using a single-stage flyback topology. This enables very high system efficiency up to 91%, on a small PCB footprint. The LED backlight control offers excellent minimum threshold regulation as well as analog and several PWM dimming options. The sequenced PWM dimming option further improves visual performance and stabilizes power demand. Extensive protection features are provided.

Figure 5. InnoMux QFN-28 Controller Pin Configuration. LED current regulation channel 1. LED current regulation channel 2. LED current regulation channel 3. LED current regulation channel 4. Current setting for LED string current. Output to control capacitor. SR signal from InnoSwitch3-MX. FW comparator signal from InnoSwitch3-MX. ACK signal from InnoSwitch3-MX. REQ output to InnoSwitch3-MX. Set power limit for VLED/VCV2. Set power limit for VCV1/VCV2. Selection MOSFET gate driver for CV2. BP/VDD regulator output. Also supplies InnoSwitch3-MX. Selection MOSFET gate driver for CV1. Output voltage connection for CV1 selection MOSFET drive. Feedback input for VCV1 output voltage. Feedback input for VCV2 output voltage. Feedback input for VLED output voltage. Output voltage connection for BP regulator. LED enable/digital PWM input.

8 CTRL

12 FWC

13 ACK

14 REQ 22

1 ICC1

2 ICC2

Figure 6. InnoMux HSOP-28 Controller Pin Configuration. LED current regulation channel 3. LED current regulation channel 4. Current setting for LED string current. Output to control capacitor. SR signal from InnoSwitch3-MX. All grounds must connect to secondary ground. FW comparator signal from InnoSwitch3-MX. ACK signal from InnoSwitch3-MX. REQ output to InnoSwitch3-MX. Set power limit for VLED/VCV2. Set power limit for VCV1/VCV2. Selection MOSFET gate drive for CV2. BP/VDD regulator output. Also supplies InnoSwitch3-MX. Selection MOSFET gate drive for CV1. Output voltage connection for CV1 selection MOSFET drive. Feedback input for VCV1 output voltage. Feedback input for VCV2 output voltage. Feedback input for VLED output voltage. Output voltage connection for BP regulator. LED enable/digital PWM input. LED current regulation channel 1. LED current regulation channel 2.

Rev. D 11/20 InnoMux www.power.com InnoMux Functional Description When paired with the InnoSwitch3-MX, the InnoMux combines dual constant voltage output regulation with a four string constant current LED backlight controller. The InnoMux controller consists of a multi-output controller for regulating the three outputs independently, a BP Regulator for supply - ing both the InnoMux as well as the paired InnoSwitch3-MX second- ary controller, High-Side MOSFET Drivers for directing the energy from the transformer to the appropriate output, Shunts to prevent individual outputs from rising in abnormal loading conditions, Current Sources to drive up to four LED backlight strings, and Readers to determine the value of application configuration resistors. Block Diagram BP Regulator The regulator regulates the BP pin to V BP(REG). The BP regulator will use VCV2 as its primary source. During start-up, the regulator will use VLED as long as VCV2 is too low (below VCV2(MIN)). It is possible to connect an unregulated supply to V CV2 to power the controller in single CV applications. For the controller to function properly, the application designer must make sure that V CV2 remains above VCV2(MIN) in all operating conditions after start-up. A ceramic capacitor on the BP in is recommended. There are no stability requirements on the capacitor; the BP regulator is uncondi- tionally stable. Multi Output Control The multi output control regulates each of the two CV outputs and the LED output independently by requesting pulses from the primary based on the FB pin voltages for the three outputs. The transformer energy is then directed to the output that needs the energy on a cycle by cycle basis by turning on the appropriate selection MOSFET in series with either the CV1 or the CV2 output. The transformer shall be designed such that the VOR is increasing from VCV1 to VCV2 to VLED, this guarantees that the current through the VLED diode is negligible when the selection MOSFET for either VCV1 or VCV2 is turned on; only disabling both MOSFETs will direct the energy delivery to the LED output. Due to the restriction in VOR, the maximum suggested LED output voltage range is about 2:1. A larger range will yield a less optimized design, as the VOR of the CV outputs gets very low. This is further explained in the applications section. The controller uses a variable frequency control scheme. The CV outputs can run in continuous conduction mode (CCM) during high load. The V LED output will always run discontinuous conduction mode (DCM) to prevent high reverse recovery losses in the high voltage silicon diode for the V LED output. High-Side MOSFET Drive The high side selection MOSFETs are driven with a drive voltage 5 V above VCV1 for GDR1 and 5V above VCV2 for GDR2 using a capacitive drive approach. The capacitive drive approach benefits from easy level translation by u se of capacitor CDR. A regular refresh cycle to top up the charge on CDR is needed when one of the switches has been on for a long time, as the charge on CDR will otherwise slowly leak away. Refresh is also needed during start-up to allow C DR to follow the output voltage when the output is being pulled up. The controller will perform refresh cycles when necessary by turning the selection MOSFET off and then back on. The default refresh time is T RESFRESH , which is doubled to 2 TRESFRESH during start-up. The longer the refresh time the better but the MOSFET needs to be turned back on before the end of the primary on time. Once the CV outputs are in regulation the refresh time is reduced to T RESFRESH . Because the output is no longer changing the refresh is only needed to top up C DR and by reducing the refresh time the risk of the primary on time finishing before the refresh is reduced. The optimal capacitor value for C DR depends on the gate charge of the selection MOSFET. The selection MOSFET on-level gate voltage is determined by V BP (CDR/(CG + CDR), so it is essential that the gate charge (at 5 V gate voltage) is much smaller than the charge in the C DR cap. A typical value for the C DR capacitor is 100nF. For higher CDR capacitor values, the refresh time might be insufficient and the c apacitor will not be able to follow the output during start-up. It is therefore important to select low gate-charge devices for the selection MOSFETs to minimise the required C DR capacitor value as well as to minimise energy consumption for driving the MOSFETs. Shunts The LV shunt is designed to limit the voltage lift on the V CV1 output. Voltage lift on the VCV1 output will typically occur due to the lower VOR of the 5 V output. At turn-on of the 5 V selection MOSFET after delivery of a pulse to one of the other outputs, a small amount of energy is delivered to the CV1 output from the higher idle ring voltage. The LV shunt is turned on when the FB1 voltage exceeds V LVSHUNT. In practical applications it is unlikely for the CV1 output to lift; CV1 output lift typically only occurs when the CV1 output is completely unloaded while the other outputs are running at high output load. The HV shunt is used to limit the voltage on the V LED rail to the maximum allowed voltage in case of peak-charging of the V LED output when the LED output is not loaded. This peak charging is predomi- nantly caused by leakage in the transformer; the V LED output typically has lowest leakage and thus will receive a small amount of energy from switching cycles that are destined for V CV1 or VCV2. The HV shunt is turned on when the FB3 voltage exceeds V HV(SHUNT). In case of application problems with overvoltage on V LED, it is possible to implement an additional Zener diode clamp with a small series resistor to dissipate the excess power as the range between V FB3(REG) and VFB3(OVP) is sufficiently large. N ote that the VCV2 output does not need a shunt as this output is not susceptible to peak charging or unintended energy delivery.

Rev. D 11/20 InnoMux www.power.com LED Current Control Operation Current sources control the current into the ICC pins. The maximum current for each current source is I ICC(MAX). The desired (full-scale) current for each of the current sources can be set by a single external current sense resistor R LED (which is connected to the IS pin). The design of the current sources guarantees that the current in each of the strings is tightly balanced. Current sources can be paralleled (ganged together) when only one or two strings are used. This will increase the maximum allowed string current. The current sources accommodate PWM dimming, analog dimming and hybrid dimming. Hybrid dimming is a combination of analog and PWM dimming. Dimming is further described in Led Dimming section. Output Voltage Regulation for V LED Output InnoMux keeps the voltage drop over the current sources as low as possible to maintain optimum system efficiency. The output voltage f or driving the LED string(s) (VLED) is therefore regulated based on the minimum required voltage drop over the four current sources. The low voltage drop over the current sources is maintained for any LED current by changing the V LED output voltage set point. When the LEDs are on, the voltage on the C CTRL capacitor is used as set point for the VLED output voltage. The voltage on the capacitor is increased when the voltage drop over anyone of the current sources is less than the target value. Vice versa, the voltage on the cap is reduced when the voltage on all current sources is too high. The regulation loop is subject to stability criteria and the capacitor has to be chosen accordingly; the optimal capacitor value depends on: T he ratio of the LED rail output capacitance (C VLED) to the available current for increasing the V LED rail voltage; T he FB3 voltage divider ratio (FB3RATIO=VLED/VFB3). The minimum capacitance value for the C CTRL capacitor is given by the following formulae; both conditions have to be met: C 0.2I 0.3G m FB3RATIOC C4 Gc FB3RATIO CTRL LED CTRL(UP) VLED CTRL CTRL(DOWN) # ## The first formula guarantees that the maximum dV/dt on the VLED voltage rail is larger than the dV/dt on the CCTRL capacitor. The second formula makes sure that the reduction in voltage on the C CTRL capacitor is smaller than the measured voltage error on the V LED rail For typical designs, 220 nF is a good starting point. Low Current Clamps Low-current clamps on each of the I CC outputs are designed to prevent over voltage conditions on the ICC pins when the LEDs are turned off. The maximum current for these clamps is I CCHV(CLAMP). These clamps will limit the voltage on the ICC pins below V HV(CLAMP) in LED off conditions, even when the nominal LED string voltage (V F) is about 100 V. InnoSwitch3-MX Interface The InnoMux to InnoSwitch3-MX interface is a four-wire interface. The REQ signal indicates a request from the InnoMux controller for a new pulse. Upon reception, InnoSwitch3-MX will then communicate this request to the primary side controller over the integrated flux-link. (Note that the InnoSwitch3-MX will delay the request to the p rimary when in DCM to achieve QR mode switching.) The REQ s ignal is also used to communicate timing for specific events d uring start-up as well as error conditions to the InnoSwitch3-MX. For this reason, REQ is a multi-level signal. The levels are shown in the table below. REQ Pin Voltage Level Condition REQ < 0.25 VREF Initial level at power-up. No pulse requested by InnoMux. InnoSwitch3-MX secondary on stand-by / in primary control mode. InnoSwitch3-MX secondary will start handshake and obtain control when the first pulse is requested. 0.25 VREF < REQ < 0.5 VREF InnoMux indicates measurement window to InnoSwitch3-MX for idle ring frequency measurement. This is a one-off event during stat-up. 0.5 VREF < REQ < VREF No pulse requested by InnoMux. VREF < REQ < 2VREF Pulse requested by InnoMux. InnoMux will retain the REQ level until the pulse request has been acknowl- edged (pulse on ACK pin) by Inno- Switch3-MX and a rising edge is observed on the SR pin. REQ > 2V REF Output overvoltage indication by InnoMux. InnoSwitch3-MX secondary will signal the primary to latch-off. The ACK signal indicates that a pulse request has been made by InnoSwitch3-MX secondary to the primary controller (via the flux li nk). The rising edge of the SR signal (driven by InnoSwitch3-MX) is used byInnoMux to assess when the transformer starts delivering energy to the secondary. The PCB trace connecting the REQ pins deserves specific attention d uring layout; it is a high-impedance multi-level analog signal and is sensitive to noise pick-up and layout impedance. Readers The (pin-) readers determine the presence and value of the resistors/ capacitors connected to the PLIM and ADIM inputs. These readers are active only directly after start-up and will not update until the next power-up.

Rev. D 11/20 InnoMux www.power.com Hybrid Dimming PWM dimming is supported during analog dimming by applying a PWM signal (D-PWM) with desired duty cycle to the DPWM pin. The allowed PWM frequency range is PWM F(RANGE). The LEDs are turned off by pulling the DPWM pin low. Normal PWM is active by default. Sequenced PWM is available as a custom option. (The R PWM(SEL) resistor is not available in this mode.) Pulling the DPWM pin low longer than the minimum PWM period will turn off the LED regulator, which will reduce chip current consump- tion in a ‘screen-off’ mode. Reducing the ADIM voltage down to 0 V to turn the LEDs off is not allowed for disabling the LEDs. Figure 11 (page 12) shows the typical connections in this mode for the DPWM, APWM and external LED current reference (V ADIM) signals. PWM Dimming In PWM dimming, the LED current sources switch rapidly between the set reference current and off, following the digital state of the PWM input. Two PWM dimming modes are available; normal and sequenced PWM. In PWM dimming, the ADIM/LPF pull-up resistor value selects between normal or sequenced PWM dimming. In hybrid dimming, the selection between normal and sequenced PWM has been preset and cannot be changed by application components. Normal PWM Dimming Mode During normal PWM mode dimming, all strings will turn on and off in phase. Sequenced PWM Dimming Mode In sequenced PWM mode, the on-periods of the four LED strings are sequenced in time by applying an equal phase shift to each of the strings. The sequenced PWM mode is designed to improve visual performance as well as reduce transient loading on the power supply which will reduce audible noise. Dependent on the LED configuration, t he PWM phase shift between channels should be 90°, 120° or 180°. The allowed LED configurations for sequenced PWM diming are s hown in Table 2.

Figure 10. P WM Timing Diagram for Two, Three and Four Channel Sequenced

Figure 11. C onnection Diagrams for Dimming Options. ADIM voltage will allow for analog dimming.

The CV1, CV2 and VLED outputs have a maximum power protection. been exceeded and it simply cannot keep the output in regulation. includes an average frequency limit that has a user selectable level. setting levels for each output are available. ill auto restart or latch-off. physically capable of delivering. is no CV2 output then no capacitors are needed. Table 3. C V1 and VLED Power Limit Selection. Table 4. C chosen as TPLIM. This defines the capacitor value for a given resistor. detected on the respective FB pins for the three outputs. open-circuit or short-circuit will also be disabled. affected string will be disabled. a latch-off request to the InnoSwitch3-MX. When a f ault i s fl agged, t he c ontroller w ill e ither a uto-restart o r l atch-off. will persist until the mains input power is cycled.

Rev. D 11/20 InnoMux www.power.com Absolute Maximum Ratings 1,2 GDR1, GDR2 Pin Voltage ICC1, ICC2, ICC3, ICC4 Pin Voltage All Other Pins Storage Temperatue Notes: 1. All voltages referenced to Secondary GROUND, T A = 25 °C. 2. Maximum ratings specified may be applied one at a time without c ausing permanent damage to the product. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect product reliability. N ormally limited by internal circuitry. Thermal Resistance Thermal Resistance: HSOP-28 Package Notes: Thermocouple attached to ground lead shoulder, near to edge of plastic body. connected by filled vias). connected by filled vias). Parameter Symbol Conditions All Voltages Referenced to GROUND / 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Pin Description and Parameters BP Pin Internal voltage supply for InnoMux and supply for InnoSwitch3-MX BP Voltage Regulation VBP(REG) 4.75 5.0 5.25 V BP Current IBP Full load excludes current consumption by InnoSwitch3-MX and selection MOSFET Drivers 18 mA BPUV 4.4 V Standby Supply Current ISBP(STANDBY) 6 mA VCV1 Pin (See Note B) Input voltage for CV1 selection MOSFET drive VCV1 VCV1 output voltage range 3 22 V VCV2 Pin (See Note B) Input voltage for VDD regulator and for CV2 selection MOSFET drive VCV2 VCV2 output voltage range 3 22 V VCV2(MIN) Minimum VCV2 voltage for BP regulator Standby 25 °C 5.8 V Full Load (30 mA) 8.0 VLED Pin VLED VLED output voltage range 20 100 V VSTAYALIVE Minimum VLED voltage that will always be maintained by the controller 15 V Gate Drive Pins Refresh Pulse Width TREFRESH TREFRESH is doubled during start-up See Note D 500 ns GDR1 The GDR1 pin drives the CV1 selection MOSFET

Rev. D 11/20 InnoMux www.power.com Parameter Symbol Conditions All Voltages Referenced to GROUND / 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Gate Drive Pins (cont.) GDR1 Output Drive Voltage VDR1 VCV1 + VBPREG (GDR1 High) VCV1 (GDR1 Low) GDR1 Resistance RDR1 TJ = 125 °C See Note C 30 35 Ω G DR2 The DR2 pin drives the CV2 selection MOSFET GDR2 Output Drive Voltage V DR2 VCV2 + VBPREG (GDR2 High) VCV2 (GDR2 Low) VCV2+VBPREG (high) / VCV2 (low) V GDR2 Resistance RDR2 TJ = 125 °C See Note C 30 35 Ω F B/IS Pins FB1 FB input for VCV1 output voltage FB1 Regulation Voltage VFB1(REG) VREF LV Shunt Threshold VLV(SHUNT) 108% of VREF V ICCLV(SHUNT) See Note D 17 20 mA FB1 Overvoltage VFB1(OVP) 112% of VREF V FB2 FB input for VCV2 output voltage FB2 Regulation Voltage VFB2(REG) VREF V FB2 Overvoltage VFB2(OVP) 112% of VREF V FB3 FB input for VLED output voltage High-Voltage Shunt Threshold V HV(SHUNT) 108% of VREF V ICCHV(SHUNT) See Note D 8.5 10 mA FB3 Overvoltage VFB3(OVP) 120% of VREF V

Rev. D 11/20 InnoMux www.power.com Parameter Symbol Conditions All Voltages Referenced to GROUND / 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units InnoSwitch3-MX Interface Pins REQ Pulse request output Should be connected to the InnoSwitch3-MX REQ input ACK Acknowledge from InnoSwitch3-MX that a request has been issued to the primary-side. Should be connected to the InnoSwitch3-MX ACK output FWC Forward comparator output from InnoSwitch3-MX. Should be connected to the InnoSwitch3-MX FWC output SR SR output from InnoSwitch3-MX. Should be connected to the InnoSwitch3-MX SR output LED Regulation Pins CTRL Pin Output to CTRL capacitor Maximum Current ICTRL(POS) ICTRL(NEG) 10 µA ICTRL(STARTUP) 0.125 × ICTRL A Regulator Gm (UP) GmCTRL(UP) 0 V < VICC(ERROR) < 0.3 V 0.825 × ICTRL A/V Regulator (DOWN) GcCTRL(DOWN) -0.3 V < VICC(ERROR) < 0 V 41.25µ × ICTRL C/V ICC Pins Regulator 1-4 ICC Voltage Protection Limit VICC(OV) 8 9 V Minimum ICC Current ICC(MIN) Per channel 5 mA Maximum ICC Current IICC(MAX) Per channel 240 mA ICC Channel Matching (See Note A) ∆100 mA 100 mA Current per string, measured in analog dimming. Equal voltage on all ICC pins. T J = 25 °C ±3 % ∆5 mA 5 mA Current per string, measured in analog dimming. Equal voltage on all ICC pins. TJ = 25 °C ±3 % ICC Clamp Voltage VICC(CLAMP) 60 65 V Maximum ICC Clamp Current I CCHV(CLAMP) 4 µA LED Control Pins LED-EN/DPWM and PWM/APWM Pins V IL LED-EN/DPWM and PWM/APWM input from system microcontroller 0 V / 5 V, 3.3 V compliant 1.5 V VIH 2.3 PWM/APWM/DPWM Frequency PWM F(RANGE) Frequency range 100 27,000 Hz PWMD(RANGE) Duty cycle range is Minimum on-time 3 µs 2 1 00 % ADIM/PWM Selection Voltage V ADIM(SEL) 2.4 2.5 V

Rev. D 11/20 InnoMux www.power.com Parameter Symbol Conditions All Voltages Referenced to GROUND / 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units LED Control Pins (cont.) ADIM/LPF Maximum Voltage VADIM Analog dimming mode: 2% to 100% 2% brightness for VADIM = 0.03 V 100% brightness for VADIM = VIS(REF) Note: Minimum output current level is ICC(MIN) Current Source IPWM(LPF) TJ = 25 °C 19.6 20.0 20.4 µA PWM Mode Selection Voltage V PWM(SEL) VADIM(SEL) < VADIM < VPWM(SEL) = Normal PWM VADIM > VPWM(SEL) = Sequenced PWM 3.8 3.9 V IS Pin Reference Voltage V IS(REF) TJ = 25 °C 1.47 1.50 1.53 V Current Source IPWM(SEL) Only enabled during start-up -20 µA IS Pin Current Gain IS(RATIO) IS(RATIO) = ILED/IS ILED = 100 µA TJ = 25 °C IS = 156 µA VADIM ≈ 0.72 V 629 642 655 Other Parameters PLIM Pins Maximum power setting for VCV1, VCV2 and VLED PLIM Pin RC Time Constant T PLIM External RC on PLIM pins 100 250 µs Reference Voltage VREF TJ = 25 °C 1.194 1.218 1.242 V OTL Protection TPROT 130 142 °C OTL Hysteresis THYST 67 °C OTL Shut Down TSD 150 °C NOTES: A. The mismatch is calculated using the following formula: II 100% AVG MAXM IN ! # #= -D ^h B. V_CV2 must be greater than or equal to V_CV1. C. This parameter is derived from characterization. D. This parameter is guaranteed by design.

Rev. D 11/20 InnoMux www.power.com NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M – 1994. 2. Unilateral tolerance zone for coplanarity applies to the exposed pad as well as the terminals. 3. Terminal width dimension apples to the metallized terminal and is measured between 0.15 and 0.25 mm from the terminal tip. 4. Dimensions in millimeters. TOP VIEW BOTTOM VIEW SIDE VIEW Seating Plane 0.05 C 0.05 C // 0.05 C 0.08 C

0.10 M C A B

0.05 M C

0.80 0.70 3.40 0.05 0.00 0.20 Ref. 0.25 28X

0.05 M C A B

5.00 0.50 0.45 0.35 28X 3.40 5.00 Pin #1 ID (Laser Marked) Pin #1 ID Chamfer 28 22 22 28 14 88 14 A B B PI-8949-052219 POD-QFN-28 Rev B QFN-28

Rev. D 11/20 InnoMux www.power.com HSOP-28 Pin #1 I.D. Detail A 6.40 Ref. 5.15 Ref. 1.30 Ref.

15 Lead Tips

0.41 0.33 (28X) 14871 15212228

0.25 M C A B

0.10 C B

0.10 C A

0.20 C 0.10 C 0.20 C 0.80 7.50 18.00 0.25 0.20 0.05 0.85 0.55 2.35 2.25 Body Thickness 2.70 Max. Total Mounting Height 0° – 8° 1.07 0.97 Gauge Plane Seating Plane Seating Plane Coplanarity: 30 Leads 10.10 A B H C C 3 4 0.29 0.25 (30X) Notes: 1. Dimensioning and Tolerancing per ASME Y14.5M – 1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exculsive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 mm per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include inter-lead flash or protrusions. 5. Dimensions in millimeters. 6. Datums A & B to be determined at Datum H. PI-8799-082718 POD-HSOP-28 Rev A TOP VIEW DETAIL A END VIEWSIDE VIEW

Rev. D 11/20 InnoMux www.power.com PI-9106-011020 QFN-28 PACKAGE MARKING A. Power Integrations Registered Trademark B. Assembly Date Code (last two digits of year followed by 2-digit work week) C. Product Identification (Part #/Package Type) D. Lot Identification Code E. Extended Lot Identification Code A B E C D 1926 IMX101J 01E8L859A H01

Rev. D 11/20 InnoMux www.power.com PI-9105-011020 HSOP-28 PACKAGE MARKING A. Power Integrations Registered Trademark B. Assembly Date Code (last two digits of year followed by 2-digit work week) C. Product Identification (Part #/Package Type) D. Lot Identification Code E. Extended Lot Identification Code A B E C D 1928 IMX101U 028P002D H01 Part Ordering Information

• InnoMux Product Family
• Series Number
• Package Identifier U HSOP J QFN
• Tape & Reel and Other Options TL Tape & Reel, 1 k pcs per reel for HSOP, 2 k pcs per reel for QFN.IMX 101 U - TL

B Code L release. 03/19 C Code A release. 03/20 D Added Storage Temperature data to Absolute Maximum Rating table. 11/20 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at www.power.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: A Lif e support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user A cri tical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperPLC, HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2020, Power Integrations, Inc. World Headquarters

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