HV400

HV400 HARRIS | Alldatasheet

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@ SEMICONDUCTOR HV400 April 1994 High Current MOSFET Driver Features Description driver designed to drive large capacitive loads at high slew + No Supply Current in Quiescent State rates. The device is optimized for driving single or parallel , charge from nC to >1000nC. It features two output stages put stage is an NPN capable of 6A. An SCR provides over icati 30A of current sinking. The HV400 achieves rise and fall Applications times of 54ns and 16ns respectively driving a 10,000pF load. + Switch Mode Power Supplies Special features are included in this part to provide a simple, + DC/DC Converters high speed gate drive circuit for power MOSFETs. The HV400 requires no quiescent supply current, however, the + Motor Controllers input current is approximately 15mA while in the high state. « Uninterruptible Power Supplies With the internal current steering diodes (pin 7) and an external capacitor, both the timing and MOSFET gate power come from the same pulse transformer; no special external ——————————— supply is required for high side switches. No high voltage Ordering Information diode is required to charge the bootstrap capacitor. PART TEMPERATURE The HV400 in combination with the MOSFET and pulse NUMBER RANGE transformer makes an isolated power switch building block for applications such as high side switches, secondary side regulation and synchronous rectification. The HV400 is also suitable for driving IGBTs, MCT, BJTs and small GTOs. The HV400 is a type of butfer; it does not have input logic Bead GeamieSBDIP | devel switching threshold voltages. This single stage design achieves propagation delays of 20ns. The output NPN + begins to source current when the voltage on pin 2 is approximately 2V more positive than the voltage at pin 8. - The output SCR switches on when the input pin 2 voltage is 1V more negative than the voltage at pins 3/6. Due to the use of the SCR for current sinking, once the output switches low, the input must not go high again until all the internal SCR charge has dissipated, 0.5us - 1.5us later. Pinout Schematic savéoo (Po, S801P, S016) a nL Met TOP view onze Kor 4 of Hi 4-0 PINS vs suppcy [i [a] source output 4 b com H 4-0 PINT input [2] DIODES PINS ot bs pms sinc output [3] [a] sink output A z 4 404 4 eno [| [z] ono i j i CAUTION, These devices are cansiive lo electrostatic discharge. Users should follow proper LC. Handling Procedures File Number 2850.1 | Copyright © Harris Corpocation 1984 | 318 i

| Specifications HV400 j | Absolute Maximum Ratings Thermal Information | 9 i SOIC eee eeeeeeeeeesseeeececeneresececereeenscO7W | Operating Temperature Range HV400M/BB3 2. eee cece eee es BEC € Ty < 125°C ; CAUTION: Stresses above those listed in “Absolute Maximum Ratings" may cause permanent damage to the device. Ths is @ stress only rating and operation i of he device at hase or any otner conditions above these indicated inthe operational sections ofthis specification is not imolied | DC Electrical Specifications —Vsuepy = 15V PARAMETERS | Sywaox | conomions | rewpenarune [ww [wae Lowe] (Pin 2 - Pin 8) wo [fw fos Pes Tv | je { (Pin 2 - Pin 4/6) = [rw [ze [oes [| | oS Input High Current Peak | sounce = 6A, Ths pulse, 425°C. Vin = 9V, Vour = OV | Vew2=-20V [ze [0 [so [a | a Oe ‘SOURCE OUTPUT (PIN'8) prewar ere Se eee a | Peak Output Current Vin = 9V, ips Pulse, +25°C Vout = 0V 4 a A a ‘SINK OUTPUT (PIN 3/6) Vow Opt Via a a a | ! Peak Output Current Vw = OV, 515 Pulse, 425°C Vour = 4V a i DIODES D1 AND 07 (PIN7) } | [Des @nrsicesorae [Oe [ips wora [ee se 3 J NOTE: Umits are 100% tested at +25°C; limits over the full temperature range are guaranteed but not tested. ‘v™

Switching Time Specifications Veuppy = 15V NOTES: 1. Switching times are guaranteed but not tested 2. Typical values are for +25°C a Switching Diagram and Test Circuit 90% INPUT 10% 10% ov Tor | Ta Tor | Te Your i oR ouTPUT 90% Ny 10% 10% ce +330uF were ort } Sour zt = ie Nb --- Hi } o oav INPUT + + 0.01uF RL OUTPUT H H rf

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HV400 Switching Test Circuit Parts List n R1 1009, 1W Carbon Resistor RY i vee @ R2 Wire ay ce Ri, 100KQ, 1/8W Carbon Resistor $ $ C1 330uF, SOV Capacitor vs C2 1yF, SOV Capacitor 3 op 1 8 C,, 0.01, F, SOV Chip Capacitor . purse 1G 207 H | PobT: «D1 1N914 Diode : | 2 6 B ray J1, J2 PC Mount Banana Jack Johnson 108-0740-001 f “33, J4 PC Mount SMA Connector Johnson EFJ142 Vv . Ut Harris HV400 I.C. vv eno © ri V gg as o ge gs cy Ps a V+ @) ct Eee gre . @==9_01_ Fae Ck,

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and the MOSFET limit the MOSFET switching time. If they Circuit Operation are too large, the HV400 may operate erratically as ‘The HV400's operation is easily explained by referring tothe _“iSCussed below. Schematic. The control signal is applied to pin 2. If the Cross Conduction Faults control signal is about 2V above pin 8, the output NPNQ1 turns on charsing the MOSFET gate from a capacitor It is possible to have both Q1 and the SCR on at the same connected to pin 1. Resistor Ré helps keep the SCR off by time resulting in very large cross conduction currents. The applying a reverse bias to the SCR anode gate. SCR has larger current capacity so the output goes low and the storage capacitor is discharged. The conditions that When the control input drops about 1V below pin 3/6, PNP cause cross conduction and precautions are discussed Q2 turns on which triggers the SCR by driving both the below. anode and cathode gates. The SCR discharges the MOSFET gate and when its current becomes less than Minimum Off Time TOMA, it tums off. Transistor Q2 conducts any gate leakage The SCR requires a recovery time before voltage can be currents, through resistors Rt and R2, once the SCR tums reapplied without it switching back on, Figure 13 shows how oft Figure 7 shows the output characteristics before the this SCR recovery time, called “minimum off time” (Ton) is a SCR turns on and after it turns off. When the SCR tums on, function of the load capacitance. If the input voltage goes resistor R4 provides a path to remove Q1 base charge. high before this recovery time is complete, the SCR will Resistor R3 provides the base current for Q2 to reduce the switch back on. tum off delay time. Resistors R1 and R2 reduce the SCR recovery time. Note that reverse current flowing through the SCR, for oo _,, example due to load inductance ringing, extends the wo The two diodes connected to the diode input pin 7 provide minimum off time. Since the minimum off time is really ow pom craration tlexiblty’ With pins 2 and 7 connected dependent upon how much stored charge remains in tho as together, diode D1 provides a path to recharge the storage SCR when the anode (pin V6) is taken pesttive, it may vary =e capacitor once the MOSFET gate is pulled high and, along for different applications. Figure 13 indirectly shows that the g = with diodes D2 and D3, keeps Qi from going into hard minimum off time increases with larger currents. It also % Saturation which would increase delay times. Diode D7 increases at elevated temperatures as shown in Figure 14. would clamp the input near ground and provide a current Excessive ringing increases the minimum off time since the Path it an input DC biocking capacitor is used. stored charge doesn’t begin to dissipate until the current Alternatively, pin 7 can be connected to pin 6 so that the drops below 10mA for the last time. Rising anode voltage SCR and NPN Q1 don't have to pass reverse current if the cts on the internal SCR capacitance to generate its own Output “rings” above the supply or below ground. When high triggering current. The excess stored charge increases this Performance diodes are required, pin 7 can be left Capacitance. Faster rise times andlor higher voltages also disconnected and external diodes substituted, increase the amount of internal trigger current from the inter- nal capacitance so applications with larger dV/dt require The diodes in series with pin 2 decouple the input from the longer minimum off times. : ‘output during negative going transitions. The absence of 5 input current turns off Q1 and allows Q2 to trigger the SCR. The minimum off time must be considered for all occur- Diode D8 turns off Q2 once the SCR tums on pulling the out- fences of SCR current. For example, in a half bridge switch Put low, otherwise Q2 would saturate and slow down circuit Mode power supply, there are two MOSFET’ connected to Operation. In addtion, the diodes D2, D3 and D8 improve the transformer primary. Assume that the high side MOSFET noise immunity by adding about 2.5V of input hysteresis. ‘Switch Is off, When the low side MOSFET switch is turned on, the HV400 driving the high side MOSFET will have to The HV400 is capable of large output currents but only for sink gate current from Cy and will have to source gate brief durations due to power dissipation. Current when the low side MOSFET switches back off. Both of these current pulses will try to flow through pin 2/6 since Clroult Board Layout the pin 8 output is turned off. Sourcing current from pins 3/6 PC board layout is very important. Pins 3 and 6 should be through the SCR is possible, the pin /6 voltage becoming Connected together as should pins 4 and 5. Otherwise the negative with respect to pins 4/5 (See Figure 8). But a better internal interconnect impedance is doubled and only half of practice would be to connect a Schottky diode between pins the bond wires are used which would degrade the reliability, 4/5 (anode) and 4/6 (cathode) so reverse current does not The bootstrap capacitor should hold at least 10x the charge OW through the SCR. of the MOSFET and should be connected between pins 1 False SCR Triggering Fa e0d cree lead ee Cees, eMeMiS®. The SCR may be triggered inadvertently. The output may close to the MOSFET as possible. y q inady m Any long PC traces (parasitic inductances) between the 0Vershoot the input due to inductive loading or over driving MOSFET gate and pins 8 or 3/6 or between the source and ® output NPN (allowing it to saturate). Whenever pin 6 is more positive than pin 2 by 1V, the SCR is triggered on. Also, a3 3-23 Atte

| if the output rises too rapidly, greater than 0.5V/nS, the SCR be capable of dissipating the energy stored in the | may self trigger. Both issues are resolved by minimizing the _ transformer. The load may be connected to either the power load inductance and inserting sufficient resistance, usually MOSFET drain or source. 0.1 to 10 ohms, between pin 8 and the load. A very fast negative going input voltage can result in ‘s pa 41 minimum off times of about 2.8us. If the output can not keep Clo Pes i up with the falling input, the stored charge of diode D4 is 2 i H transferred into the base of Q2. This excess charge in Q2 So 7 eho must have time to dissipate. Otherwise, when pin 3/6 goes i positive, Q2 will turn on and trigger the SCR. An external Dy diode in series with pin 2, as shown in Figure 1, wil prevent KS r D4 from discharging into the base of Q2 but that will also avd reduce the output voltage by the forward voltage of that ot B i diode. 7 nnrannnnnnnnnnt & POWER Internal Diodes = nwo MOSFET The internal diodes connected to pin 7 are provided for FIGURE 1. UNIPOLAR DRIVE convenience but may not be suitable for large currents, A diode is added in serles with pins 2 and 7 to allow the Since they are part of the integrated circuit, they are transformer secondary to go negative. The charge storage of physically small, operate at high current densities, and have the pin 7 diode may cause the tun off delay time to be too long recovery times. Figure 15 shows that their forward long. Alternatively, pin 7 could be lett disconnected and a characteristics degrade above 100mA. In addition, Figure 16 second external diode connected between the transformer shows their reverse recovery charge as a function of forward (anode) and pin 1 (cathode). In some applications the diode current. The product of this charge, the applied reverse _in series with pin 2 may be unnecessary but the -35V input voltage and the frequency is the additional power dissipation to output or ground maximum rating should be observed. see need can eer ices one Stee noni use the Sometimes the volt-second balance is achieved by a push Taverse bias, In addition to the extra power dissipation, the Pull dive on the pulse transformer primary, This is especialy Capaetanca of these diodes may extend the switching delay USetUl ft there are two secondary windings driving two tines. HV400's out of phase such as in a half-bridge configuration i Other times it is more convenient to achieve volt-second Power Dissipation Calculations balance by using capacitors to block DC in the primary and The power required to drive the MOSFET is the product of secondary windings as shown in Figure 2. The pin 7 diodes its total gate charge times the gate supply voltage (maximum provide a path for discharging the secondary side DC block- voltage on HV400 pin 1, 2 or 7) times the frequency. ing capacitor. Both capacitors, Ciy and Cs, should be at ‘Assuming that the MOSFET gate resistance is negligible, least 10 times the equivalent MOSFET gate capacitance. this power is dissipated within the HV400. If resistors are placed between the HV400 and the MOSFET, then some of: ne HV4O0 can be used as a current booster for low side the power is dissipated in the resistors, the percentage’ switches ‘by connecting oe ha tne Fn output The | depending upon the ratio of resistors to HVé00 output NM! ® i switching time test circu impedance. Itis worth restating that some consideration (and experimen There are two other sources of power dissipation to ttn) should be given to the choice of external components, e ie. resistors, capacitors and diodes, to optimize consider. First there is the power in 3 which is the product Pe riormance in a given application. of the input pin 2 current and voltage (with no output current) . times the duty cycle. Second is the product of the pin 7 diode 7 preennannnnnnninanniny 4 stored charge, which is dependent upon the forward current, ¢ $ times the applied diode reverse voltage times the frequency. Cw Plo a This information is available from figures 3 and 16 in this 4 »| 2: fe! Rour H data sheet. Fn Beil Applications Circuits a i wey ‘The HV400 was designed to interface a pulse transformer to i a power MOSFET. There must be some means to balance i aw the transformer volt-second product over a cycle. The unipolar drive shown in Figure 1 lets the core magnetization 4 Rereeeneennrmecemeneml inductance reverse the primary and secondary voltages. The zener diode on the primary side limits this voltage and must FIGURE 2. BIPOLAR DRIVE WITH DC BLOCKING CAPACITOR 3-26 .

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FIGURE 15. DIODE D1 ‘AND 07 CURRENT vs Ve FIGURE 16. DIODE Qaa VS FORWARD CURRENT FIGURE 17. DIODE D1 REVERSE RECOVERY ‘WAVEFORM FIGURE 18. Vix [AND hyip VS lops (Your (PIN 8) = 0, V+ = 15V,