HSP3824

HSP3824 HARRIS | Alldatasheet

Document overview

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Technical content

Features

• Complete DSSS Baseband Processor
• Single Supply Operation (33MHz Max) . . 2.7V to 5.5V
• Single Supply Operation (44MHz Max) . . 3.3V to 5.0V
• Supports Full or Half Duplex Operations
• On-Chip A/D Converters for I/Q Data (3-Bit, 44 MSPS) and RSSI (6-Bit, 2 MSPS)

Applications

• Systems Targeting IEEE802.11 Standard
• DSSS PCMCIA Wireless Transceiver
• Spread Spectrum WLAN RF Modems
• TDMA Packet Protocol Radios
• Part 15 Compliant Radio Links
• Portable Bar Code Scanners/POS Terminal
• Portable PDA/Notebook Computer
• Wireless Digital Audio
• Wireless Digital Video
• PCN/Wireless PBX PRELIMINARY March 1996 File Number 4064.2

Description

Sequence (DSSS) baseband pro- cessor is part of the PRISM™ 2.4GHz radio chipset, and contains all the functions necessary for a full or half duplex packet base- band transceiver. The HSP3824 has on-board ADC’s for analog I and Q inputs, for which the HFA3724 IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with optional data scrambling capability, are combined with a pro- grammable PN sequence of up to 16 bits. Built-in flexibility allows the HSP3824 to be configured through a general purpose control bus, for a wide range of applications. A Receive Signal Strength Indicator (RSSI) monitoring function with on-board 6-bit 2 MSPS ADC provides Clear Channel Assessment (CCA) to avoid data collisions and optimize network throughput. The HSP3824 is housed in a thin plastic quad flat package (TQFP) suitable for PCMCIA board applications.

Ordering Information

HSP3824VI -40 oC to +85oC 48 Lead TQFP Q48.7x7 TM

Typical Application Diagram QUAD IF MODULATOR RFPA HFA3925 HFA3724 DSSS BASEBAND PROCESSOR DATA TO MACCTRL HSP3824 TUNE/SELECT HFA3524 0o/90o VCO A/D A/D MAC-PHY INTERFACE 802.11 VCO DUAL SYNTHESIZER HFA3624 RF/IF CONVERTER A/D (FILE# 4067) (FILE# 4064) (FILE# 4062) (FILE# 4066) (FILE# 4132) PRISM™ CHIP SET FILE #4063 M U X M U X DPSK DEMOD DPSK MOD. DE- SPREAD SPREAD Q I HFA3424 (NOTE) (FILE# 4131) TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HSP3824 NOTE: Required for systems targeting 802.11 specifications. CCA RXI RXQ RSSI TXI TXQ □÷ 2 For additional information on the PRISM™ chip set, call (407) 724-7800 to access Harris’ AnswerFAX system. When prompted, key in the four-digit document number (File #) of the datasheets you wish to receive. The four-digit file numbers are shown in Typical Application Diagram, and correspond to the appropriate circuit.

NAME PIN TYPE I/O DESCRIPTION VDD (Analog) 10, 18, 20 Power DC power supply 2.7V - 5.5V VDD (Digital) 7, 21, 29, 42 Power DC power supply 2.7V - 5.5V GND (Analog) 11, 15, 19 Ground DC power supply 2.7V - 5.5V, ground. GND (Digital) 6, 22, 31, 41 Ground DC power supply 2.7V - 5.5V, ground. VREFN 17 I “Negative” voltage reference for ADC’s (I and Q) [Relative to V REFP ] VREFP 16 I “Positive” voltage reference for ADC’s (I, Q and RSSI) IIN 12 I Analog input to the internal 3-bit A/D of the In-phase received data. Q IN 13 I Analog input to the internal 3-bit A/D of the Quadrature received data. RSSI 14 I Receive Signal Strength Indicator Analog input. A/D_CAL 26 O This signal is used internally as part of the I and Q ADC calibration circuit. When the ADC calibration circuit is active, the voltage references of the ADCs are adjusted to maintain the outputs of the ADCs in their optimum range. A logic 1 on this pin indicates that one or both of the ADC outputs are at their full scale value. This signal can be integrated externally as a control voltage for an external AGC. TX_PE 2 I When active, the transmitter is configured to be operational, otherwise the transmitter is in standby mode. TX_PE is an input from the external Media Access Controller (MAC) or network processor to the HSP3824. The rising edge of TX_PE will start the internal transmit state machine and the falling edge will inhibit the state machine. TX_PE envelopes the transmit data. TXD 3 I TXD is an input, used to transfer serial Data or Preamble/Header information bits from the MAC or network processor to the HSP3824. The data is received serially with the LSB first. The data is clocked in the HSP3824 at the falling edge of TXCLK. TXCLK 4 O TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to the HSP3824, synchronously. Transmit data on the TXD bus is clocked into the HSP3824 on the falling edge. The clocking edge is also programmable to be on either phase of the clock. The rate of the clock will be depending upon the modulation type and data rate that is programmed in the signalling field of the header. TX_RDY 5 O When the HSP3824 is configured to generate the preamble and Header information internally, TX_RDY is an output to the external network processor indicating that Preamble and Header information has been generated and that the HSP3824 is ready to receive the data packet from the network processor over the TXD serial bus. The TX_RDY returns to the inactive state when the TX_PE goes inactive indicating the end of the data transmission. TX_RDY is an active high signal. This signal is meaningful only when the HSP3824 generates its own preamble. CCA 32 O Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The CCA algorithm is user programmable and makes its decision as a function of RSSI, Energy detect (ED), Carrier Sense (CRS) and the CCA watch dog timer. The CCA algorithm and its programmable features are described in the data sheet. Logic 0 = Channel is clear to transmit. Logic 1 = Channel is NOT clear to transmit (busy). NOTE: This polarity is programmable and can be inverted. RXD 35 O RXD is an output to the external network processor transferring demodulated Header information and data in a serial format. The data is sent serially with the LSB first. The data is frame aligned with MD_RDY . RXCLK 36 O RXCLK is the clock output bit clock. This clock is used to transfer Header information and data through the RXD serial bus to the network processor. This clock reflects the bit rate in use.RXCLK will be held to a logic “0” state during the acquisition process. RXCLK becomes active when the HSP3824 enters in the data mode. This occurs once bit sync is declared and a valid signal quality estimate is made, when comparing the programmed signal quality thresholds.

MD_RDY 34 O MD_RDY is an output signal to the network processor, indicating a data packet is ready to be transferred to the processor. MD_RDY is an active high signal and it envelopes the data transfer over the RXD serial bus. MD_RDY returns to its inactive state when there is no more receiver data, when the programmable data length counter reaches its value or when the link has been interrupted. MD_RDY remains inactive during preamble synchronization. RX_PE 33 I When active, receiver is configured to be operational, otherwise receiver is in standby mode. This is an active high input signal. ANTSEL 27 O The antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. SD 25 I/O SD is a serial bi-directional data bus which is used to transfer address and data to/from the internal registers. The bit ordering of an 8-bit word is MSB first. The first 8 bits during transfers indicate the register address immediately followed by 8 more bits representing the data that needs to be written or read at that register. SCLK 24 I SCLK is the clock for the SD serial bus.The data on SD is clocked at the rising edge. SCLK is an input clock and it is asynchronous to the internal master clock (MCLK)The maximum rate of this clock is 10MHz or the master clock frequency, whichever is lower. AS 23 I AS is an address strobe used to envelope the Address or the data on SD. Logic 1 = envelopes the address bits. Logic 0 = envelopes the data bits. W8 I R / W is an input to the HSP3824 used to change the direction of the SD bus when reading or writing data on the SD bus. R/W must be set up prior to the rising edge of SCLK. A high level indicates read while a low level is a write. CS 9 I CS is a Chip select for the device to activate the serial control port.TheCS doesn’t impact any of the other interface ports and signals, i.e. the TX or RX ports and interface signals. This is an active low signal. When inactive SD, SCLK, AS and R/ W become “don’t care” signals. TEST 0-7 37, 38, 39, 40, 43, 44, 45, 46 O This is a data port that can be programmed to bring out internal signals or data for monitoring. This data includes: Correlator phase and magnitude, NCO frequency offset estimate, and signal quality estimates. Some of the discrete signals available include: Carrier Sense (CRS), which becomes active when initial PN acquisition has been declared. Energy Detect (ED) which becomes active when the integrated RSSI value exceeds the programmable threshold. Both ED and CRS are active high signals.These bits are primarily reserved by the manufacturer for testing. A further description of the test port is given at the appropriate section of this data sheet. TEST_CK 1 O This is the clock that is used in conjunction with the data that is being output from the test bus (TEST 0-7). RESET 28 I Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the HSP3824 goes into the power standby mode.RESET does not alter any of the configuration register values nor it presets any of the registers into default values. Device requires programming upon power-up. RESET must be inactive during programming of the device. MCLK 30 I Master Clock for device. The maximum frequency of this clock is 44MHz. This is used internally to generate all other internal necessary clocks and is divided by 1, 2, 4, or 8 for the transceiver clocks. I OUT 48 O TX Spread baseband I digital output data. Data is output at the programmed chip rate. Q OUT 47 O TX Spread baseband Q digital output data. Data is output at the programmed chip rate. NOTE: Total of 48 pins; ALL pins are used. Pin Description(Continued) NAME PIN TYPE I/O DESCRIPTION

FIGURE 1. DSSS BASEBAND PROCESSOR

11 TO 16-BIT

TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST

TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST (Continued)

data is output as soon as it is demodulated by the HSP3824. functions, including acquisition, will be in a stand by mode. from the HSP3824 and it envelopes the valid data on RXD.

• The number of data symbols, as defined by the length field in the protocol, has been received and output through RXD in its entirety (normal condition).
• PN tracking is lost during demodulation.
• RX_PE is deactivated by the external controller. MD_RDY can be configured through CR 9, bit 6 to be active low, or active high. Energy Detect (ED) pin 45 (Test port), and Carrier Sense (CRS) pin 46 (Test port), are available outputs from the HSP3824 and can be useful signals for an effective RX interface design. Use of these signals is optional. CRS and ED are further described within this docu- ment. The receive port is completely independent from the operation of the other interface ports including the TX port, supporting therefore a full duplex mode. I/Q ADC Interface The PRISM baseband processor chip (HSP3824) includes two 3-bit Analog to Digital converters (ADCs) that sample the analog input from the IF down converter. The I/Q ADC clock, MCLK, samples at twice the chip rate. The maximum sampling rate is 44MHz (power supply: 3.3V to 5.0V) or 33MHz (power supply 2.7V to 5.5V). The interface specifications for the I and Q ADCs are listed on Table 2 below. The voltages applied to pin 16,V REFP and pin 17, VREFN set the references for the internal I and Q ADC converters. In addition, V REFP is also used to set the RSSI ADC converter reference. For a nominal 500mVP-P, the suggested VREFP voltage is 1.75V, and the suggested VREFN is 0.93V. VREFN should never be less than 0.25V. Since these ADCs are intended to sample AC voltages, their inputs are biased internally and they should be capacitively coupled. The ADC section includes a compensation (calibration) cir- cuit that automatically adjusts for temperature and compo- nent variations of the RF and IF strips. The variations in gain of limiters, AGC circuits, filters etc. can be compensated for up to ±4dB. Without the compensation circuit, the ADCs could see a loss of up to 1.5 bits of the 3 bits of quantization. The ADC calibration circuit adjusts the ADC reference volt- ages to maintain optimum quantization of the IF input over this variation range. It works on the principle of setting the reference to insure that the signal is at full scale (saturation) a certain percentage of the time. Note that this is not an AGC and it will compensate only for slow variations in signal levels (several seconds).

TABLE 2. I, Q, ADC SPECIFICATIONS NOTE: MD_RDY active after CRC16. FIGURE 7. RX PORT TIMING

room for circuit tolerances. the ADCs and the reference circuits. FIGURE 8. INTERFACES transmit in half duplex operation. external processor to assist in network management. listed in the Test Modes Table 5. TABLE 3. ADC CALIBRATION 0 0 Automatic real time adjustment of reference. 0 1 Reference set at mid scale. 1 0 Reference held at most recent value. 1 1 Reference set at mid scale. TABLE 4. RSSI ADC SPECIFICATIONS TABLE 5. TEST MODES

0 Normal

1 Correlator Test

2 Frequency Test

3 Phase Test

4 NCO Test Mode DCLK NCO Phase Accum Reg

5 SQ Test Mode LoadSQ SQ2 (15:8) Phase

6 Bit Sync Test

7 Bit Sync Test

Normal -Device in the full protocol mode (Mode 3). TXCLK - Transmit clock (PN rate). Mag -Magnitude output from the correlator. FrqReg -Contents of the NCO frequency register. Phase -phase of signal after carrier loop correction. RXCLK - Receive clock (RX sample clock). Nominally 22MHz. tion accumulator contents, mantissa only. accumulator 8 MSBs of most recent 16-bit stored value. A/D_Cal_ck -Clock for applying A/D calibration corrections. not be programmed for automatic level adjustment. trolled by the following control signals. required when returning to operational modes. other inputs to the part (MCLK, SCLK, etc.) continue to run.

8 A/D Cal Test

9 Reserved

11 Reserved

12 Reserved

13 Reserved

14 Reserved

15 Reserved

TABLE 5. TEST MODES (Continued) TABLE 6. POWER DOWN MODES tained. Device will return to its active state within 10µs. in its active state within 1µs.

data scrambler and a PN generator, as shown on Figure 9. to DQPSK switchover, as required. of the synchronization preamble bits is programmable. and RX as a function of MCLK, Chips per symbol and N. clocks for proper operation of the device. Symbol Rate = MCLK/(N x Chips per Symbol). expressed on the symbol rate equation. DBPSK modulated, and the data is DQPSK modulated. FIGURE 9. MODULATOR DIAGRAM

to utilize the data scrambling option. the original pattern unless it is disabled. ability of false alarm for signal acquisition. always DBPSK preamble and header fields. FIGURE 10. PREAMBLE/HEADEAR MODES

16 Bits

8 Bits

TABLE 7. BIT RATE TABLE EXAMPLES

when it needs to de-assert the MD_RDY interface signal. MD_RDY envelopes the received data packet as it is being output to the external processor. CCITT - CRC 16 Field (16 Bits) -This field includes the 16- bit CCITT - CRC 16 calculation of the five header fields. This value is compared with the CCITT - CRC 16 code calculated at the receiver. The HSP3824 receiver can be programmed to drop the link upon a CCITT - CRC 16 error or it can be programmed to ignore the error and to continue with data demodulation. The CRC or cyclic Redundancy Check is a CCITT CRC-16 FCS (frame check sequence). It is the ones compliment of the remainder generated by the modulo 2 division of the pro- tected bits by the polynominal: X 16 + x12 + x5 + 1 The protected bits are processed in transmit order. All CRC calculations are made prior to data scrambling. A shift regis- ter with two taps is used for the calculation. It is preset to all ones and then the protected fields are shifted through the register. The output is then complimented and the residual shifted out MSB first. When the HSP3824 generates the preamble and header inter- nally it can be configured into one of four link protocol modes. Mode 0 -In this mode the preamble is programmable up to 256 bits (all 1's) and the SFD field is the only field utilized for the header. This mode only supports DBPSK transmissions for the entire packet (preamble/header and data). Mode 1 -In this mode the preamble is programmable up to 256 bits (all 1's) and the SFD and CCITT - CRC 16 fields are used for the header. The data that follows the header can be either DBPSK or DQPSK. The receiver and transmitter must be pro- grammed to the proper modulation type. Mode 2 -In this mode the preamble is programmable up to 256 bits (all 1's) and the SFD, Length Field, and CCITT - CRC 16 fields are used for the header. The data that follows the header can be either DBPSK or DQPSK. The receiver and transmitter must be programmed to the proper modulation type. Mode 3 -In this mode the preamble is programmable up to 256 bits (all 1's). The header in this mode is using all available fields. In mode 3 the signal field defines the modulation type of the data packet (DBPSK or DQPSK) so the receiver does not need to be preprogrammed to anticipate one or the other. In this mode the device checks the Signal field for the data packet modulation and it switches to DQPSK if it is defined as such in the signal field. Note that the preamble and header are always DBPSK the modulation definition applies only for the data packet. This mode is called the full protocol mode in this document. Figure 10 summarizes the four preamble/head or modes. In the case that the device is configured to accept the preamble and header from an external source it still needs to be configured in one of the four modes (0:3). Even though the HSP3824 trans- mitter does not generate the preamble and header information the receiver needs to know the mode in use so it can proceed with the proper protocol and demodulation decisions. The following Configuration Registers (CR)are used to program the preamble/header functions, more programming details about these registers can be found in the Control Registers section of this document: CR 0 -Defines one of the four modes (bits 4, 3) for the TX. Defines whether the SFD timer is active (bit 2). Defines whether the receiver should stop demodulating after the number of sym- bols indicated in the Length field has been met. CR 2 -Defines to the receiver one of the four protocol modes (bits 1, 0). Indicates whether any detected CCITT - CRC 16 errors need to reset the receiver (return to acquisition) or to ignore them and continue with demodulation (bit 5). Specifies a 128-bit preamble or an 80-bit preamble (bit 2). CR 3 -Defines internal or external preamble generation (bit 2). Indicates to the receiver the data packet modulation (bit 0), note that in mode 3 the contents of this register are overwritten by the information in the received signal field of the header. CR 3 specifies the data modulation type used to the transmitter (bit 1). Bit 1 defines the contents of the signaling field in the header to indicate either DBPSK or DQPSK modulation. CR 41 -Defines the length of time that the demodulator searches for the SFD before returning to acquisition. CR 42 -The contents of this register indicate that the transmit- ted data is DBPSK. If CR 4-bit 1 is set to indicate DBPSK mod- ulation then the contents of this register are transmitted in the signal field of the header. CR 43 -The contents of this register indicates that the transmit- ted data is DQPSK. If CR 4-bit 1 is set to indicate DQPSK mod- ulation then the contents of this register are transmitted in the signal field of the header. CR 44, 45, 46, 47, 48 -Status, read only, registers that indicate the service field, data length field and CCITT - CRC 16 field val- ues of the received header. CR 49, 50 -Defines the transmit SFD field value of the header. The receiver will always search to detect this value before it declares a valid data packet. CR 51 -Defines the contents of the transmit service field. CR 52, 53 -Defines the value of the transmit data length field. This value includes all symbols following the last header field symbol. CR 54,55 -Status, read only, registers indicating the calculated CCITT - CRC 16 value of the most recently transmitted header. CR 56 -Defines the number of preamble synchronization bits that need to be transmitted when the preamble is internally generated. These symbols are used by the receiver for initial PN acquisition and they are followed by the header fields. The full protocol requires a setting of 128d = 80h. For other applications, in general increasing the preamble length will improve low signal to noise acquisition performance at the cost of greater link overhead. For dual receive antenna operation, the minimum suggested value is 128d = 80h. For single receive antenna operation, the minimum suggested value is 80d = 50h. These suggested values include a 2 symbol TX power amplifier ramp up. If an AGC is used, its worst case settling time in sym- bols should be added to these values.

as opposed to a secure communications feature. flashing the 7 bits stored from the previous transmission. are DBPSK modulated, and the data is DQPSK modulated. supply voltages between 2.7V and 5.5V. FIGURE 13. CCA FUNCTIONAL FLOW DIAGRAM

deciding to transmit over the interference. and is also passed to the clear channel assessment logic. clear channel assessment state machine. The energy detection (ED) signal is the digitized RSSI signal. bined to initiate a clear channel assessment decision. timing ED until it meets the programmed time out count. CS are both active. This is an obviously busy channel. acquired or where an interferer turns on. transmit regardless of the state of CCA. the ADC exceeds this threshold then ED becomes active. are included under the receiver section of this document. FIGURE 14. DEMODULATOR BLOCK DIAGRAM

data is output through the RX Port to the external processor. ations are handled with a relatively wide loop bandwidth. quality for acquisition and lock detection. is found and the best antenna is selected.

1. Worst Case Timing; antenna dwell starts before signal is full strength.
2. Time line shown assumes that antenna 2 gets insufficient signal.

FIGURE 15. DUAL ANTENNA ACQUISITION TIMELINE FIGURE 16. SINGLE ANTENNA ACQUISITION TIMELINE

16 SYMBOLS

126 SYMBOL SYNC

16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 7S 16 SYMBOLS

78 SYMBOL SYNC SFD

16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 7 SYM 16 SYMBOLS

7 SYM

These two thresholds, bit sync amplitude CR (22 and 23) and phase error CR (30 and 31) are used to determine if the desired signal is present. If the thresholds are set too “low”, there is the probability of missing a high signal to noise detection due to processing a false alarm. If they are set too “high”, there is the probability of missing a low signal to noise detection. For the bit sync amplitude, “high” actually means high amplitude while for phase noise “high” means high SNR or low noise. A recommended procedure is to set these thresholds individu- ally optimizing each one of them to the same false alarm rate with no desired signal present. Only the background environ- ment should be present, usually additive gaussian white noise (AGWN). When programming each threshold, the other threshold is set so that it always indicates that the signal is present. Set register CR22 to 00h while trying to determine the value of the phase error signal quality threshold for regis- ters CR 30 and 31. Set register CR30 to FFh while trying to determine the value of the Bit sync. amplitude signal quality threshold for registers 22 and 23. Monitor the Carrier Sense (CRS) output (TEST 7, pin 46) and adjust the threshold to pro- duce the desired rate of false detections. CRS indicates valid initial PN acquisition. After both thresholds are programmed in the device the CRS rate is a logic “and” of both signal qualities rate of occurrence over their respective thresholds and will therefore be much lower than either. PN Correlator Description The PN correlator is designed to handle BPSK spreading with carrier offsets up to±50ppm and 11,13,15 or 16 chips per symbol. Since the spreading is BPSK, the correlator is implemented with two real correlators, one for the I and one for the Q channel.The same sequence is always used for both I an Q correlators. The TX sequence can be pro- grammed as a different sequence from the RX sequence. This allows a full duplex link with different spreading parame- ters for each direction. The correlators are time invariant matched filters otherwise known as parallel correlators. They use two samples per chip. The correlator despreads the samples from the chip rate back to the original data rate giving 10.4dB processing gain for 11 chips per bit. While despreading the desired sig- nal, the correlator spreads the energy of any non correlating interfering signal. Based on the fact that correlator output pulse is used for bit timing, the HSP3824 can not be used for any non spread applications. In programming the correlator functions, there are two sets of configuration registers that are used to program the spread sequences of the transmitter and the receiver. They are CR 13 and 14 for transmitter and CR 20 and 21 for the receiver. In addition, CR2 and CR3 define the sequence length or chips per symbol for the receiver and transmitter respectively. These are carried in bits 6 and 7 of CR2 and bits 5 and 6 of CR3. More programming details are given in the Control Registers section of this document. Data Demodulation and Tracking The signal is demodulated from the correlation peaks tracked by the symbol timing loop (bit sync). The frequency and phase of the signal is corrected from the NCO that is driven by the phase locked loop. Demodulation of the DPSK data in the early stages of acquisition is done by delay and subtraction of the phase samples. Once phase locked loop tracking of the carrier is established, coherent demodulation is enabled for better performance. Averaging the phase errors over 16 symbols gives the necessary frequency infor- mation for proper NCO operation. The signal quality is taken as the variance in this estimate. There are two signal quality measurements that are per- formed in real time by the device and they set the demodula- tor performance. The thresholds for these signal quality measurements are user programmable. The same two sig- nal quality measures, phase error and bit sync. amplitude, that are used in acquisition are also used for the data drop lock decision. The data thresholds, though, are programmed independently from the acquisition thresholds. If the radio uses the network processor to determine when to drop the signal, the thresholds for these decisions should be set to their limits allowing data demodulation even with poor signal reception. Under this configuration the HSP3824 data moni- tor mechanism is essentially bypassed and data monitoring becomes the responsibility of the network processor. These signal quality measurements are integrated over 128 symbols as opposed to 16 symbol intervals for acquisition, so the minimum time to drop lock based with these thresholds is 128 symbols or 128ms at 1 MSPS. Note that other than the data thresholds, non-detection of the SFD can cause the HSP3824 to drop lock and return its acquisition mode. Configuration Register 41 sets the search timer for the SFD. This register sets this time-out length in symbols for the receiver. If the time out is reached, and no SFD is found, the receiver resets to the acquisition mode. The suggested value is preamble symbols + 16 symbols. If several transmit pream- ble lengths are used by various transmitters in a network, the longest value should be used for the receiver settings. Procedure to Set Signal Quality Registers CR 26, 27, 34, AND 35 (RX_SQX_IN_DATA) are pro- grammed to hold the threshold values that are used to drop lock if the signal quality drops below their values. These can be set to their limit values if the external network processor is used for drop lock decisions instead of the HSP3824 demodulator. The signal quality values are averaged over 128 symbols and if the bit sync amplitude value drops below its threshold or the phase noise rises over its threshold, the link is dropped and the receiver returnes to the acquisition mode. These values should typically be different for BPSK and QPSK since the operating point in SNR differs by 3dB. If the receiver is intended to receive both BPSK and QPSK modulations, a compromise value must be used or the net- work processor can control them as appropriate.

The suggested method of optimization is to set the transmit- ter in a continuous transmit mode. Then, measure the time until the receiver drops lock at low signal to noise ratio. Each of the 2 thresholds should be set individually to the same drop lock time. While setting thresholds for one of the signal qualities the other should be configured at its limit so it does not influence the drop lock decisions. Set CR 26 to 00h while determining the value of CR 34 and 35 for phase error threshold. Set CR 34 to FFh while determining the value of CR 26 and 27 for bit sync. amplitude threshold. Assuming a 10e-6 BER operating point, it is suggested that the drop lock thresholds are set at 10e-3 BER, with each threshold adjusted individually. Note that the bit sync amplitude is linearly proportional to the signal amplitude at the ADC converters. If an AGC system is being used instead of a limiter, the bit sync amplitude thresh- old should be set at or below the minimum amplitude that the radio will see at its sensitivity level. Data Decoder and Descrambler The data decoder that implements the desired DQPSK cod- ing/decoding as shown in DQPSK Data Decoder Table 9. This coding scheme results from differential coding of the dibits. When used in the DBPSK modes, only the 00 and 11 dibits are used. Vector rotation is counterclockwise. The data scrambler and de-scrambler are self synchronizing circuits. They consist of a 7-bit shift register with feedback of some of the taps of the register. The scrambler can be dis- abled for measuring RF carrier suppression. The scrambler is designed to insure smearing of the discrete spectrum lines produced by the PN code. One thing to keep in mind is that both the differential decod- ing and the descrambling when used cause error extension. This causes the errors to occur in groups of 4 and 6. This is due to two properties of the processing. First, the differential decoding process causes errors to occur in pairs. When a symbol error is made, it is usually a single bit error even in QPSK mode. When a symbol is in error, the next symbol will also be decoded wrong since the data is encoded in the change from one symbol to the next. Thus, two errors are made on two successive symbols. In QPSK mode, these may be next to one another or separated by up to 2 bits. TABLE 9. DQPSK DATA DECODER so the observed errors can be in groups of 4 instead of 6. packet so that it can be recognized in its scrambled state. mance of each individual system. themselves are a small percentage of the overall loss. properties of differential decoding and descrambling.

TABLE 10. CONTROL REGISTER VALUES FOR SINGLE ANTENNA ACQUISITION

TABLE 10. CONTROL REGISTER VALUES FOR SINGLE ANTENNA ACQUISITION (Continued)

The following tables describe the function of each control register along with the associated bits in each control register. CONFIGURATION REGISTER 0 ADDRESS (0h) MODEM CONFIGURATION REGISTER A Bit 7 This bit selects the transmit antenna, controlling the output ANT_SEL pin. It is only used in half duplex mode. (Bit 5 = 0) Logic 1 = Antenna A. Logic 0 = Antenna B. Bit 6 In single antenna operation this bit is used as the output of the ANT_SEL pin. In dual antenna mode this bit is ignored. Logic 1 = Antenna A. Logic 0 = Antenna B. Bit 5 This control bit is used to select between full duplex and half duplex operation. If set for full duplex operation, the ANT_SEL pin reflects the setting of CR0 bit 7 when TX_PE is active and reflects the receiver’s choice when TX_PE is inactive. In full duplex operation, the ANT_SEL pin always reflects the receiver’s choice antenna. Logic 1 = full duplex. Logic 0 = half duplex. Bit 4, 3 These control bits are used to select one of the four input Preamble Header modes for transmitting data. The preamble and header are DBPSK for all modes of operation. Mode 0 is followed by DBPSK data. For modes 1-3, the data can be configured as either DBPSK or DQPSK. This is a “don’t care” if the header is generated externally. Bit 2 This control bit is used to enable the SFD (Start Frame Delimiter) timer. If the time is set and expires before the SFD has been detected, the HSP3824 will return to its acquisition mode. Logic 1: Enables the SFD timer to start counting once the PN acquisition has been achieved. Logic 0: Disables the SFD Timer. Bit 1 This control bit enables counting the number of data bits per the length field embedded in the header. Only used in header modes 2 and 3. Then according to the count it returns the processor into its acquisition mode at the end of the count. If length field is 0000h, modem will reset at end of SFD regardless of this bit setting. Logic 1 = Enable Length Time Out. Logic 0 = Disabled. Bit 0 Unused don’t care. CONFIGURATION REGISTER 1 ADDRESS (04h) MODEM CONFIGURATION REGISTER B Bit 7 When active this bit maintains the RXCLK and TXLK rates constant for preamble and data transfers even if the data is modulated in DQPSK. This bit is used if the external processor can not accommodate rate changes. This is an active high signal. The rate used is the QPSK rate and the BPSK header bits are double clocked. Bit 6, 5, 4, 3, 2 These control bits are used to define a binary count (N) from 0 - 31. This count is used to assert TX_RDY N - clocks (TXCLK) before the beginning of the first data bit. If this is set to zero, then the TX_RDY will be asserted immediately after the last bit of the Preamble Header. Bit 1 When active the internal A/D calibration circuit sets the reference to mid-scale. When inactive then the calibration cir- cuit adjusts the reference voltage in real time to optimize I, Q levels. Logic 1 = Reference set at mid-scale (fixed). Logic 0 = Real time reference adjustment. Bit 0 When active the A/D calibration circuit is held at its last value. Logic 1 = Reference held at the most recent value. Logic 0 = Real time reference level adjustment. MODE BIT 4 BIT 3 MODE DESCRIPTION 0 0 0 Preamble with SFD Field. 1 0 1 Preamble with SFD, and CRC16. 2 1 0 Preamble with SFD, Length, and CRC16. 3 1 1 Full preamble and header.

CONFIGURATION REGISTER 2 ADDRESS (08h) MODEM CONFIGURATION REGISTER C Bit 7, 6 These control bits are used to select the number of chips per symbol used in the I and Q paths of the receiver matched filter correlators (see table below). Bit 5 This control bit is used to disable the CRC16 check. When this bit is set, the processor will accept the received packet and any packet error checks have to be detected externally. The HSP3824 will remain in the receive mode until either the carrier is lost or the network processor resets the device to the acquisition mode, or if, in modes 2 or 3, the length times out. Logic 1 = Disable receiver error checks. Logic 0 = Enable receiver checks. Bit 4, 3 These control bits are used to select the divide ratio for the demodulators receive chip clock timing.The value of N is determined by the following equation: Symbol Rate = MCLK/(N x Chips per symbol). Bit 2 This control bit sets the receiver into single or dual antenna mode. The Preamble acquisition processing length and whether the modem scans antennas is controlled by this bit. If in single antenna mode, the ANT_SEL pin reflects CR0 bit 6 otherwise it reflects the receiver’s choice of antenna. Logic 0 = Acquisition processing is for dual antenna acquisition. Logic 1 = Acquisition processing is for single antenna acquisition. Bit 1, 0 These control bits are used to indicate one of the four Preamble Header modes for receiving data. Each of the modes includes different combinations of Header fields. Users can choose the mode with the fields that are more appropriate for their networking requirements. The Header fields that are combined to form the various modes are:

• SFD field
• CRC16 field
• Data length field (indicates the number of data bits that follow the Header information)
• Full protocol Header CONFIGURATION REGISTER 3 ADDRESS (0Ch) MODEM CONFIGURATION REGISTER D Bit 7 Reserved (must set to “0”). CHIPS PER SYMBOL BIT 7 BIT 6 11 0 0 13 0 1 15 1 0 16 1 1 MASTER CLOCK/N BIT 4 BIT 3 N = 2 0 0 N = 4 0 1 N = 8 1 0 N = 16 1 1 INPUT MODE BIT 1 BIT 0 RECEIVE PREAMBLE - HEADER FIELDS 0 0 0 Preamble, with SFD Field 1 0 1 Preamble, with SFD, CRC16 2 1 0 Preamble, with SFD Length, CRC16 3 1 1 Preamble, with Full Protocol Header

Bit 6, 5 These control bits combined are used to select the number of chips per symbol used in the I and Q transmit paths (see table below). Bit 4, 3 These control bits are used to select the divide ratio for the transmit chip clock timing. NOTE: The value of N is determined by the following equation: Symbol Rate = MCLK/(N x Chips per symbol) Bit 2 This control bit is used to select the origination of Preamble/Header information. Logic 1: The HSP3824 generates the Preamble and Header internally by formatting the programmed header information and generating a TX_RDY to indicate the beginning of the data packet. Logic 0: Accepts the Preamble/Header information from an externally generated source. Bit 1 This control bit is used to indicate the signal modulation type for the transmitted data packet. When configured for mode 0 header, or mode 3 and external header, this bit is ignored. See Register 0 bits 4 and 3. Logic 1 = DBPSK modulation for data packet. Logic 0 = DQPSK modulation for data packet. Bit 0 This control bit is used to indicate the signal modulation type for the received data packet Used only with header modes 1 and 2. See register 2 bits 1 and 0. Logic 1 = DBPSK. Logic 0 = DQPSK. CONFIGURATION REGISTER 4 ADDRESS (10h) INTERNAL TEST REGISTER A Bit 7 - 0 These control bits are used to direct various internal signals to test port output pins. These internal signals are moni- tored to fault isolate the device at manufacturing testing. During normal operation, the value 0h is recommended. This will result to the following signals becoming available at the output test pins of the device: Pin 46 (TEST7): Carrier Sense (CRS), a Logic 1 indicates PN lock. Pin 45 (TEST6): Energy Detect (ED), a Logic 1 indicates that there is energy detected in the channel. The ED goes active when the RSSI exceeds the threshold level programmed by the user. Pin 1 (TEST_CK): PN clock. CONFIGURATION REGISTER 5 ADDRESS (14h,18h) INTERNAL TEST REGISTER B Bits 7 - 0 These bits need to be programmed to 0h. They are used for manufacturing test only. CONFIGURATION REGISTER 7 ADDRESS (1Ch) MODEM STATUS REGISTER A Bit 7 This bit indicates the status of the TX_RDY output pin. TX_RDY is used only when the HSP3824 generates the Pre- amble/Header data internally. Logic 1: Indicates that the HSP3824 has completed transmitting Preamble header information and is ready to accept data from the external source (i.e. MAC) to transmit. Logic 0: Indicates that the HSP3824 is in the process of transmitting Preamble Header information. Bit 6 This status bit indicates the antenna selected by the device. Logic 0: Antenna A is selected. Logic 1: Antenna B is selected. CONFIGURATION REGISTER 3 ADDRESS (0Ch) MODEM CONFIGURATION REGISTER D (Continued) CHIPS PER BIT 6 BIT 5 11 0 0 13 0 1 15 1 0 16 1 1 MASTER BIT 4 BIT 3 N = 2 0 0 N = 4 0 1 N = 8 1 0 N = 16 1 1

Bit 5 This status bit indicates the present state of clear channel assessment (CCA) which is output pin 32. The CCA is being asserted as a result of a channel energy monitoring algorithm that is a function of RSSI, carrier sense, and time out counters that monitor the channel activity. Bit 4 This status bit, when active indicates Carrier Sense, or PN lock. Logic 1: Carrier present. Logic 0: No Carrier Sense. Bit 3 This status bit indicates whether the RSSI signal is above or below the programmed RSSI 6-bit threshold setting. This signal is referred as Energy Detect (ED). Logic 1: RSSI is above the programmed threshold setting. Logic 0: RSSI is below the programmed threshold setting. Bit 2 This bit indicates the status of the output control pin MD_RDY (pin 34). It signals that a valid Preamble/Header has been received and that the next available bit on the TXD bus will be the first data packet bit. Logic 1: Envelopes the data packet as it becomes available on pin 3 (TXD). Logic 0: No data packet on TXD serial bus. Bit 1 This status bit indicates whether the external device has acknowledged that the channel is clear for transmission. This is the same as the input signal TX_PE on pin 2. Logic 1 = Acknowledgment that channel is clear to transmit. Logic 0 = Channel is NOT clear to transmit. Bit 0 This status bit indicates that a valid CRC16 has been calculated. The CRC16 is calculated on the Header information. The CRC16 does not cover the preamble bits. Logic 1 = Valid CRC16 check. Logic 0 = Invalid CRC16 check. CONFIGURATION REGISTER 8 ADDRESS (20h) MODEM STATUS REGISTER B Bit 7 This status bit is meaningful only when the device operates under the full protocol mode. Errors imply CRC errors of the header fields. Logic 0 = Valid packet received. Logic 1 = Errors in received packet. Bit 6 This bit is used to indicate the status of the SFD search timer. The device monitors the incoming Header for the SFD. If the timer, times out the HSP3824 returns to its signal acquisition mode looking to detect the next Preamble and Header. Logic 1 = SFD not found, return to signal acquisition mode. Logic 0 = No time out during SFD search. Bit 5 This status bit is used to indicate the modulation type for the data packet. This signal is generated by the header de- tection circuitry in the receive interface. Logic 0 = DBPSK. Logic 1 = DQPSK. Bit 4 Unused, don’t care. Bit 3 Unused, don’t care. Bit 2 Unused, don’t care. Bit 1 Unused, don’t care. Bit 0 Unused, don’t care. CONFIGURATION REGISTER 9 ADDRESS (24h) I/O DEFINITION REGISTER This register is used to define the phase of clocks and other interface signals. Bit 7 This bit needs to always be set to logic 0. Bit 6 This control bit selects the active level of the MD_RDY output pin 34. Logic 1 = MD_RDY is active 0. Logic 0 = MD_RDY is active 1. CONFIGURATION REGISTER 7 ADDRESS (1Ch) MODEM STATUS REGISTER A (Continued)

Bit 5 This control bit selects the active level of the Clear Channel Assessment (CCA) output pin 32. Logic 1 = CCA active 1. Logic 0 = CCA active 0. Bit 4 This control bit selects the active level of the Energy Detect (ED) output which is an output pin at the test port, pin 45. Logic 1 = ED active 0. Logic 0 = ED active 1. Bit 3 This control bit selects the active level of the Carrier Sense (CRS) output pin which is an output pin at the test port, pin 46. Logic 1 = CRS active 0. Logic 0 = CRS active 1. Bit 2 This control bit selects the active level of the transmit ready (TX_RDY) output pin 5. Logic 1 = TX_RDY active 0. Logic 0 = TX_RDY active 1. Bit 1 This control bit selects the active level of the transmit enable (TX_PE) input pin 2. Logic 1 = TX_PE active 0. Logic 0 = TX_PE active 1. Bit 0 This control bit selects the phase of the transmit output clock (TXCLK) pin 4. Logic 1 = Inverted TXCLK. Logic 0 = NON-Inverted TXCLK CONFIGURATION REGISTER 10 ADDRESS (28h) RSSI VALUE REGISTER Bits 0 - 7 This is a read only register reporting the value of the RSSI analog input signal from the on chip 6-bit ADC. This register is updated at (chip rate/11). Bits 7 and 6 are not used and set to Logic 0. Example: CONFIGURATION REGISTER 11 ADDRESS (2ch) A/D CAL POS REGISTER Bits 0 - 7 This 8-bit control register contains a binary value used for positive increment for the level adjusting circuit of the A/D reference. The larger the step the faster the level reaches saturation. CONFIGURATION REGISTER 12 ADDRESS (30h) A/D CAL NEG REGISTER Bits 0 - 7 This 8-bit control register contains a binary value used for the negative increment for the level adjusting reference of the A/D. The number is programmed as 256 - the value wanted since it is a negative number. CONFIGURATION REGISTER 13 ADDRESS (34h) TX SPREAD SEQUENCE (HIGH) Bits 0 - 7 This 8-bit register is programmed with the upper byte of the transmit spreading code. This code is used for both the I and Q signalling paths of the transmitter. This register combined with the lower byte TX_SPREAD(LOW) generates a transmit spreading code programmable up to 16 bits. Code lengths permitted are 11, 13, 15, and 16. Right justified MSB first. CONFIGURATION REGISTER 9 ADDRESS (24h) I/O DEFINITION REGISTER BITS (0:7) RANGE RSSI_STAT 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 00h (Min) 0 0 1 1 1 1 1 1 3Fh (Max)

CONFIGURATION REGISTER 14 ADDRESS (38h) TX SPREAD SEQUENCE (LOW) Bits 0 - 7 This 8-bit register is programmed with the lower byte of the transmit spreading code. This code is used for the I and Q signalling paths of the transmitter. This register combined with the higher byte TX_SPREAD(HIGH) generates the transmit spreading code programmable up to 16 bits. The example below illustrates the bit positioning for one of the 11 bit Barker PN codes. Example: CONFIGURATION REGISTER 15 ADDRESS (3Ch) SCRAMBLER SEED Bits 0 - 7 This register contains the 7-bit (seed) value for the transmit scrambler which is used to preset the transmit scrambler to a known starting state. The MSB bit position (7) is unused and must be programmed to a Logic 0. The example below illustrates the bit positioning of seed. CONFIGURATION REGISTER 16 ADDRESS (40h) SCRAMBLER TAP Bits 0 - 7 This register is used to configure the transmit scrambler with a 7-bit polynomial tap configuration. The transmit scram- bler is a 7-bit shift register, with 7 configurable taps. A logic 1 is the respective bit position enables that particular tap. The MSB bit 7 is not used and it is set to a Logic 0. The example below illustrates the register configuration for the polynomial F(x) = 1 + X -4+X-7. Each clock is a shift left CONFIGURATION REGISTER 17 ADDRESS (44h)CCA TIMER THRESHOLD Bits 0 - 7 This 8-bit register is used to configure the period of the time-out threshold of the CCA watchdog timer. If the channel is busy the timer counts until it reaches the programmed value and at that point it declares that the channel is clear independent of the actual energy measured within the channel. This register is programmable up to 8 bits. For example, for a chip rate of 11 MCPS and a desired timeout of ~11ms, N = 2ch. CONFIGURATION REGISTER 18 ADDRESS (48h) CCA CYCLE THRESHOLD Bits 0 - 7 This 8-bit register is used to configure how many times the CCA timer is allowed to reach its maximum count before the channel is declared clear for transmission independent of the actual energy in the channel. This is an outer counter loop of the CCA timer. Each increment represents a time out of the CCA timer. Use a value of 03h for a time out of 2 CCA timer counts. Transmit Spreading Code 11-Bit Barker Word Right Justified MSB First. MSB LSB TX_SPREAD(HIGH) 15 14 13 12 11 10 9 8 TX_SPREAD(LOW) 7 6 5 4 3 2 1 0 11-bit Barker code X X X X X 1 0 1 1 0 1 1 1 0 0 0 LSB Bits (0:7) 7 6 5 4 3 2 1 0 XZ -7Z-6Z-5Z−4Z-3Z-2Z-1 Scrambler Taps F(x) = 1 + X -4+X-7 0 1 0 0 1 0 0 0 Time (ms) 1000 N 5632• LSB Bits (0:7) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 02h (Min) CCA_TIMER_TH 1 1 1 1 1 1 1 1 FFh (Max) MSB LSB Bits (0:7) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 2h; 1 CCA timer (Min) CCA_TIMER_TH 1 1 1 1 1 1 1 1 FFh; 256 CCA timer (Max)

CONFIGURATION REGISTER 19 ADDRESS (4Ch) RSSI THRESHOLD, ENERGY DETECT Bits 0 - 7 This register contains the value for the RSSI threshold for measuring and generating energy detect (ED). When the RSSI exceeds the threshold ED is declared. ED indicates the presence of energy in the channel. The threshold that activates ED is programmable. Bits 7 an 6 of this register are not used and set to Logic 0. CONFIGURATION REGISTER 20 ADDRESS (50h) RX SPREAD SEQUENCE (HIGH) Bits 0 - 7 This 8-bit register is programmed with the upper byte of the receive despreading code. This code is used for both the I and Q signalling paths of the receiver. This register combined with the lower byte RX_SPRED(LOW) generates a receive despreading code programmable up to 16 bits. Right justified MSB first. See address 13 and 14 for example. CONFIGURATION REGISTER 21 ADDRESS (54h) RX SPREAD SEQUENCE (LOW) Bits 0 - 7 This 8-bit register is programmed with the lower byte of the receiver despreading code. This code is used for both the I and Q signalling paths of the receiver. This register combined with the upper byte RX_SPRED(HIGH) generates a receive despreading code programmable up to 16 bits. CONFIGURATION REGISTER 22 ADDRESS (58h) RX SIGNAL QUALITY 1 ACQ (HIGH) THRESHOLD Bits 0 - 7 This control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for acquisition. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude signal quality measurements made during acquisition at each antenna dwell. This threshold comparison is added with the SQ2 threshold in registers 30 and 31 for acquisition. A lower value on this threshold will increase the probability of detection and the probability of false alarm. Set the threshold according to instructions in the text. CONFIGURATION REGISTER 23 ADDRESS (5Ch) RX SIGNAL QUALITY 1 ACQ THRESHOLD (LOW) Bits 0 - 7 This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for ac- quisition. This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude sig- nal quality measurement made during acquisition at each antenna dwell. CONFIGURATION REGISTER 24 ADDRESS (60h) RX SIGNAL QUALITY 1 ACQ READ (HIGH) Bits 0 - 7 This status register contains the upper byte bits (8 - 14) of the measured signal quality threshold for the bit sync am- plitude used for acquisition. This register combined with the lower byte represents a 15-bit value, representing the mea- sured bit sync amplitude. This measurement is made at each antenna dwell and is the result of the best antenna. CONFIGURATION REGISTER 25 ADDRESS (64h) RX SIGNAL QUALITY 1 ACQ READ (LOW) Bits 0 - 7 This register contains the lower byte bits (0 - 7) of the measured signal quality threshold for the bit sync amplitude used for acquisition. This register combined with the higher byte represents a 15-bit value, of the measured bit sync ampli- tude. This measurement is made at each antenna dwell and is the result of the best antenna. CONFIGURATION REGISTER 26 ADDRESS (68h) RX SIGNAL QUALITY 1 DATA THRESHOLD (HIGH) Bits 0 - 7 This control register contains the upper byte bits (8-14) of the bit sync amplitude signal quality threshold used for drop lock decisions. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude signal quality measurements, made every 128 symbols. These thresholds set the drop lock probability. A higher value will increase the probability of dropping lock. CONFIGURATION REGISTER ADDRESS 27 (6Ch) RX SIGNAL QUALITY 1 DATA THRESHOLD (LOW) Bits 0 - 7 This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for drop lock decisions. This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude signal quality measurements, made every 128 symbols. MSB LSB Bits (0:7) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 00h (Min) RSSI_STAT 0 0 1 1 1 1 1 1 3Fh (Max)

CONFIGURATION REGISTER 28 ADDRESS (70h) RX SIGNAL QUALITY 1 DATA (high) THRESHOLD READ (HIGH) Bits 0 - 7 This status register contains the upper byte bits (8-14) of the measured signal quality of bit sync amplitude used for drop lock decisions. This register combined with the lower byte represents a 15-bit value, representing the measured signal quality for the bit sync amplitude. This measurement is made every 128 symbols. CONFIGURATION REGISTER 29 ADDRESS (74h) RX SIGNAL QUALITY 1 DATA THRESHOLD READ (LOW) Bits 0 - 7 This register contains the lower byte bits (0-7) of the measured signal quality of bit sync amplitude used for drop lock decisions. This register combined with the lower byte represents a 16-bit value, representing the measured signal qual- ity for the bit sync amplitude. This measurement is made every 128 symbols. CONFIGURATION REGISTER 30 ADDRESS (78h) RX SIGNAL QUALITY 2 ACQ THRESHOLD (HIGH) Bits 0 - 7 This control register contains the upper byte bits (8-15) of the carrier phase variance threshold used for acquisition. This register combined with the lower byte represents a 16-bit threshold value for carrier phase variance measurement made during acquisition at each antenna dwell and is based on the choice of the best antenna. This threshold is used with the bit sync threshold in registers 22 and 23 to declare acquisition. A higher value in this threshold will increase the probability of acquisition and false alarm. CONFIGURATION REGISTER 31 ADDRESS (7Ch) RX SIGNAL QUALITY 2 ACQ THRESHOLD (LOW) Bits 0 - 7 This control register contains the lower byte bits (0-7) of the carrier phase variance threshold used for acquisition. CONFIGURATION REGISTER 32 ADDRESS (80h) RX SIGNAL QUALITY 2 ACQ READ (HIGH) Bits 0 - 7 This status register contains the upper byte bits (8-15) of the measured signal quality of the carrier phase variance used for acquisition. This register combined with the lower byte generates a 16-bit value, representing the measured signal quality of the carrier phase variance. This measurement is made during acquisition at each antenna dwell and is based on the selected best antenna. CONFIGURATION REGISTER 33 ADDRESS (84h) RX SIGNAL QUALITY 2 ACQ READ (LOW) Bits 0 - 7 This status register contains the lower byte bits (0-7) of the measured signal quality of the carrier phase variance used for acquisition. This register combined with the lower byte generates a 16-bit value, representing the measured signal quality of the carrier phase variance. This measurement is made during acquisition at each antenna dwell and is based on the selected best antenna CONFIGURATION REGISTER 34 ADDRESS (88h) RX SIGNAL QUALITY 2 DATA THRESHOLD (HIGH) Bits 0-7 This control register contains the upper byte bits (8-15) of the carrier phase variance threshold. This register combined with the lower byte represents a 16-bit threshold value for the carrier phase variance signal quality measurements made every 128 symbols. CONFIGURATION REGISTER 35 ADDRESS (8Ch) RX SIGNAL QUALITY 2 DATA THRESHOLD (LOW) Bits 0-7 This control register contains the lower byte bits (0-7) of the carrier phase variance threshold. This register combined with the upper byte) represents a 16-bit threshold value for the carrier phase variance signal quality measurements made every 128 symbols. CONFIGURATION REGISTER 36 ADDRESS (90h) RX SIGNAL QUALITY 2 DATA READ (HIGH) Bits 0-7 This status register contains the upper byte bits (8-15) of the measured signal quality of the carrier phase variance. This register combined with the lower byte represents a 16-bit value, of the measured carrier phase variance. This measurement is made every 128 symbols. CONFIGURATION REGISTER 37 ADDRESS (94h) RX SIGNAL QUALITY 2 DATA READ (LOW) Bits 0-7 This register contains the lower byte bits (0-7) of the measured signal quality of the carrier phase variance. This register combined with the represents a 16-bit value, of the measured carrier phase variance. This measurement is made every 128 symbols. CONFIGURATION REGISTER ADDRESS 38 (98h) RX SIGNAL QUALITY 8-BIT READ Bits 0 - 7 This 8-bit register contains the bit sync amplitude signal quality measurement derived from the 16-bit Bit Sync signal quality value stored in the CR28-29 registers. This value is the result of the signal quality measurement for the best antenna dwell. The signal quality measurement provides 256 levels of signal to noise measurement.

CONFIGURATION REGISTER 39 ADDRESS RESERVED Reserved CONFIGURATION REGISTER 40 ADDRESS RESERVED Reserved CONFIGURATION REGISTER 41 ADDRESS (A4h) SFD SEARCH TIME Bits 0 - 7 This register is programmed with an 8-bit value which represents the length of time for the demodulator to search for a SFD in a receive Header. Each bit increment represents 1 symbol period. CONFIGURATION REGISTER 42 ADDRESS (A8h) DSBPSK SIGNAL Bits 0 - 7 This register contains an 8-bit value indicating the data packet modulation is DBPSK. This value will be a OAH for full protocol operation at a data rate of 1 MBPS, and is used in the transmitted Signalling Field of the header. This value will also be used for detecting the modulation type on the received Header. CONFIGURATION REGISTER 43 ADDRESS (ACh) DQPSK SIGNAL Bits 0 - 7 This register contains the 8-bit value indicating the data packet modulation is DQPSK. This value will be a 14h for full protocol operation at a data rate of 2 MBPS and is used in the transmitted Signalling Field of the header. This value will also be used for detecting the modulation type on the received header. CONFIGURATION REGISTER 44 ADDRESS (B0h) RX SERVICE FIELD (RESERVED) Bits 0 - 7 This register contains the detected received 8-bit value of the Service Field for the Header. This field is reserved for the full protocol mode for future use and should be always a 00h. CONFIGURATION REGISTER 45 ADDRESS (B4h) RX DATA LENGTH (HIGH) Bits 0 - 7 This register contains the detected higher byte (bits 8-15) of the received Length Field contained in the Header. This byte combined with the lower byte indicates the number of transmitted bits in the data packet. CONFIGURATION REGISTER 46 ADDRESS (B8h) RX DATA LENGTH (LOW) Bits 0 - 7 This register contains the detected lower byte of the received Length Field contained in the Header. This byte com- bined with the upper byte indicates the number of transmitted bits in the data packet. CONFIGURATION REGISTER 47 ADDRESS (BCh) RX CRC16 (HIGH) Bits 0 - 7 This register contains the upper byte bits (8 -15) of the received CRC16 field Header. This register combined with the lower byte represents a 16-bit CRC16 value protecting transmitted header. The fields protected are selected by con- figuring the header control bits at configuration register 2. CONFIGURATION REGISTER 48 ADDRESS (C0h) RX CRC16 (LOW) Bits 0 - 7 This register contains the lower byte bits (0-7) of the received CRC16 field Header. This register combined with the upper byte represents a 16-bit CRC16 value protecting transmitted header. The fields protected are selected by con- figuring the header control bits at configuration register 2. MSB LSB RX_CRC16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX_CRC16(HIGH) 765432 1 0 RX_CRC16(LOW) 7 6 5 4 3 2 1 0 NOTE: The receive CRC16 Field protects the following fields depending upon the mode selection, as defined in configuration register 2. Mode 0 CRC16 not used Mode 1 CRC16 protects SFD Mode 2 CRC16 protects SFD, and Length Field Mode 3 CRC16 protects Signalling Field, Service Field, and Length Field

CONFIGURATION REGISTER 49 ADDRESS (C4h) SFD (HIGH) Bits 0 - 7 This 8-bit register contains the upper byte bits (8-15) of the SFD used for both the Transmit and Receive header. This register combined with the lower byte represents the 16-bit value for the SFD field. CONFIGURATION REGISTER 50 ADDRESS (C8h) SFD (LOW) Bits 0 - 7 This 8-bit register contains the upper byte bits (0-7) of the SFD used for both the Transmit and Receive header. This register combined with the lower byte represents the 16-bit value for the SFD field. CONFIGURATION REGISTER 51 ADDRESS (CCh) TX SERVICE FIELD Bits 0 - 7 This 8-bit register is programmed with the 8-bit value of the Service Field to be transmitted in a Header. This field is reserved for future use and should be always a 00h. CONFIGURATION REGISTER 52 ADDRESS (D0h) TX DATA LENGTH FIELD (HIGH) Bits 0 - 7 This 8-bit register contains the higher byte (bits 8-15) of the transmit Length Field described in the Header. This byte combined with the lower byte indicates the number of bits to be transmitted in the data packet. CR 52/53 should not be set to 0000h. This value would cause the modem to reset after SFD. CONFIGURATION REGISTER 53 ADDRESS (D4h) TX DATA LENGTH FIELD (LOW) Bits 0 - 7 This 8-bit register contains the lower byte bits (0-7) of the transmit Length Field described in the Header. This byte combined with the higher byte indicates the number of bits to be transmitted in the data packet, including the MAC payload header. CR 52/53 should not be set to 0000h. This value would cause the modem to reset after SFD. CONFIGURATION REGISTER 54 ADDRESS (D8h) TX CRC16 (HIGH) Bits 0 - 7 This 8-bit register contains the upper byte (bits 8-15) of the transmitted CRC16 Field for the Header. This register combined with the lower byte represents a 16-bit CRC16 value calculated by the HSP3824 to protect the transmitted header. The fields protected are selected by configuring the header mode control bits at register address 02. CONFIGURATION REGISTER 55 ADDRESS (DCh) TX CRC16 (LOW) Bits 0 - 7 This 8-bit register contains the lower byte (bits 0-7) of the transmitted CRC16 Field for the Header. This register com- bined with the higher byte represents a 16-bit CRC16 value calculated by the HSP3824 to protect the transmitted header. The fields protected are selected by configuring the header mode control bits at register address 02. configuration register 2 CONFIGURATION REGISTER 56 ADDRESS (E0h) TX PREAMBLE LENGTH Bits 0 - 7 This register contains the count for the Preamble length counter. This counter is programmable up to 8 bits and rep- resents the number of preamble bits. This should be set at 50h for 1 antenna and 80h for dual antennas. MSB LSB RX_CRC16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX_CRC16(HIGH) 7 6 5 4 3 2 1 0 RX_CRC16(LOW) 7 6 5 4 3 2 1 0 NOTE: The receive CRC16 Field protects the following fields depending upon the mode selection. as defined in register address 02. Mode 0 CRC16 not used Mode 1 CRC16 protects SFD Mode 2 CRC16 protects SFD, and Length Field Mode 3 CRC16 protects Signalling Field, Service Field, and Length Field

Specifications HSP3824 at 33MHz Absolute Maximum Ratings Reliability Information Thermal Resistance (Typical) θJA Package Power Dissipation at 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Power Supply Current I CCOP VCC = Max, CLK Frequency 22MHz (Notes 1, 2) -6 9 7 7 m A Standby Power Supply Current I CCSB VCC = Max, Outputs Not Loaded - 1 2.5 mA Input Leakage Current I I VCC = Max, Input = 0V or VCC -10 1 10 µA Output Leakage Current I O VCC = Max, Input = 0V or VCC -10 1 10 µA Logical One Input Voltage V IH VCC = Max, Min 0.7 V CC -V Logical Zero Input Voltage V IL VCC = Min, Max - V CC /3 V Logical One Output Voltage V OH IOH = -1mA, VCC = Min V CC -0.4 V CC -.2 - V Logical Zero Output Voltage V OL IOL = 2mA, VCC = Min - .2 0.4 V Input Capacitance C IN CLK Frequency 1MHz All measurements referenced to GND. T A = +25oC, Note 2 - 5 10 pF Output Capacitance C OUT - 5 10 pF NOTES: 2. Not tested, but characterized at initial design and at major process/design changes. PARAMETER SYMBOL 33MHz UNITSMIN MAX CLK Period (MCLK) t CP 30 - ns CLK High (MCLK) t CH 9- n s CLK Low (MCLK) t CL 9- n s Setup Time to MCLK (TXD) t S2 10 - ns Hold Time from MCLK (TXD) t H2 20 - ns SCLK Clock Period t P 100ns or MCLK - ns SCLK High t H 20 - ns SCLK Low t L 20 - ns Set up to SCLK (SD, AS, R/W, CS) t S1 20 - ns Hold Time from SCLK (SD, AS, R/W, CS) t H1 20 - ns SD OUT from SCLK t D1 -3 0 n s Output Enable of Sd from R/W High t E1 - 20 ns (Note 2) Output disable of SD after R/W Low t F1 - 20 ns (Note2) TXCLK, TXRDY, I, Q from MCLK t D2 -3 5 n s RXCLK, MD_RDY, RXD from MCLK t D3 -3 5 n s TEST 0-7, CCA, AGC, from MCLK t D4 -4 0 n s ANSTEL, TEST_CK ---- OUTPUT Rise/Fall - 10 ns (Note 2, 3) NOTES: 1. AC tests performed with CL = 40pF , IOL = 2mA, and IOH = -1mA. Input reference level all inputs 1.5V. Test VIH = VCC , VIL = 0V; VOH = VOL = VCC /2. 2. Not tested, but characterized at initial design and at major process/design changes. 3. Measured from V ILto VIH.

Specifications HSP3824 I and Q A/D AC Electrical Specifications PARAMETER MIN TYP MAX UNITS Full Scale Input Voltage (VP-P) 0.25 0.50 1.0 V Input Bandwidth (-0.5dB) - 20 - MHz Input Capacitance - 5 - pF Input Impedance (DC) 5 - - k Ω FS (Sampling Frequency) - - 44 MHz RSSI A/D Electrical Specifications PARAMETER MIN TYP MAX UNITS Full Scale Input Voltage (VP-P) - - 1.15 V Input Bandwidth (0.5dB) 1MHz - - MHz Input Capacitance (DC) - 7pF - pF Input Impedance 1M - - M Ω

1. Includes Stray and JIG Capacitance

FIGURE 22. TEST LOAD CIRCUIT of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

1. Not tested, but characterized at initial design and major process/design changes.
2. AC tests performed with CL = 40pF , IOL = 2mA, and IOH = -1mA. Input reference level all inputs 1.5V. Test VIH = Vcc, VIL= 0V; VOH = VOL

D E E1 -A- PIN 1 A2 A1 A 11o-13o 11o-13o 0o-7o 0.020 0.008MIN L 0o MIN PLANE B 0.004/0.008 0.09/0.20WITH PLATING BASE METAL SEATING 0.004/0.006 0.09/0.16 -B- e 0.003

0.08 A-B SD SCM

0.08 0.003 -C- -D- -H- 0.25 0.010 GAGE PLANE Thin Plastic Quad Flatpack Packages (TQFP) Q48.7x7 (JEDEC MO-136AE ISSUE C)

48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE

A - 0.047 - 1.20 - A1 0.002 0.005 0.05 0.15 - A2 0.038 0.041 0.95 1.05 - B 0.007 0.010 0.17 0.27 6 B1 0.007 0.009 0.17 0.23 - D 0.347 0.362 8.80 9.20 3 D1 0.268 0.283 6.80 7.20 4, 5 E 0.347 0.362 8.80 9.20 3 E1 0.268 0.283 6.80 7.20 4, 5 L 0.018 0.029 0.45 0.75 - N4 8 4 87 e 0.020 BSC 0.50 BSC - Rev. 0 4/95 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane . 4. Dimensions D1 and E1 to be determined at datum plane . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum B dimension by more than 0.08mm (0.003 inch). 7. “N” is the number of terminal positions. -C- -H-