HS-1840RH HARRIS | Alldatasheet

Document overview

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Technical content

Features

  • Radiation Environment - Gamma Rate 1 x 10 8 RAD(Si)/s - Gamma Dose ( γ) 2 x 105 RAD(Si)
  • Low Power Consumption
  • Fast Access Time 1000ns
  • High Analog Input Impedance 500MΩ During Power Loss (Open)
  • Dielectrically Isolated Device Islands
  • Excellent In Hi-Rel Redundant Systems
  • Break-Before-Make Switching
  • No Latch-Up

Description

The HS-1840RH is a radiation hardened, monolithic 16 channel multiplexer constructed with the Harris Linear Dielectric Isolation CMOS process. It is designed to provide a high input impedance to the analog source if device power fails (open) or the analog signal voltage inadvertently exceeds the supply rails during powered operation. Excellent for use in redundant applications, since the secondary device can be operated in a standby unpowered mode affording no additional power drain. More significantly, a very high impedance exists between the active and inactive devices preventing any interaction. One of sixteen channel selection is controlled by a 4-bit binary address plus an Enable-Inhibit input which conveniently controls the ON/OFF operation of several multiplexers in a system. All digital inputs have electrostatic discharge protection. The HS-1840RH has been specifically designed to meet exposure to radiation environments. It is available in a 28 lead Ceramic Sidebraze dual-in-line package and 28 lead Ceramic Flatpack. It is guaranteed operational from -55 oC to +125oC. Pinouts

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. HS1-1840RH-Q -55 to 125 28 Ld CERDIP HS1-1840RH-8 -55 to 125 28 Ld CERDIP HS1-1840RH/Proto -55 to 125 28 Ld CERDIP HS1-1840RH/Sample 25 28 Ld CERDIP HS9-1840RH-Q -55 to 125 28 Ld FP HS9-1840RH-8 -55 to 125 28 Ld FP HS9-1840RH/Proto -55 to 125 28 Ld FP HS9-1840RH/Sample 25 28 Ld FP (γ) HS1-1840RH 28 LEAD SIDEBRAZE CERDIP CASE OUTLINE GDIP1-T28, COMPLIANT TO MIL-STD-

1835 PACKAGE

HS9-1840RH 28 LEAD CERAMIC SIDEBRAZE CASE FLATPACK OUTLINE CDFP3-F28, COMPLIANT TO MIL-STD-1835 PACKAGE TOP VIEW +VS NC NC IN 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 GND (+5VS) VREF ADDR A3 OUT IN 8 IN 7 IN 6 IN 5 IN 3 IN 1 ENABLE ADDR A0 ADDR A1 ADDR A2 -VS IN 4 IN 2 +VS NC NC IN 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 GND (+5VS) VREF ADDR A3 OUT -VS IN 8 IN 7 IN 6 IN 5 IN 4 IN 3 IN 2 IN 1 ENABLE ADDR A0 ADDR A1 ADDR A2 NOT RECOMMENDED FOR NEW DESIGNSSee HS-1840ARH

A3 A2 A1 A0 EN “ON” CHANNEL XXXXH None LLLLL 1 LLLHL 2 LLHLL 3 LLH HL 4 LHLLL 5 LHLHL 6 LHHLL 7 LHHHL 8 HLLLL 9 HLLHL 1 0 HLHLL 1 1 HLHHL 1 2 H HLLL 1 3 HHLHL 1 4 HHHL L 1 5 HHHHL 1 6 P EN IN 1 OUT IN 16 DIGITAL ADDRESS DECODERSADDRESS INPUT BUFFER AND LEVEL SHIFTER MULTIPLEX SWITCHES P Spec Number 518022

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS characterized upon initial design and after major process and/or design changes. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

TABLE 4. POST 200K RAD(Si) ELECTRICAL CHARACTERISTICS

TABLE 5. DC POST BURN-IN DELTA ELECTRICAL CHARACTERISTICS TABLE 6. APPLICABLE SUBGROUPS

Performance Characteristics and Test Circuits ACCESS TIME vs LOGIC LEVEL (HIGH) BREAK-BEFORE-MAKE DELAY (tOPEN) ENABLE DELAY (tON(EN), tOFF(EN)) 0.8V 50% 50% tA 4.0V VA VOUT 15V, 0VIN 1 IN 16 IN 2 - IN 15 0V, 15V 0.8V 10K 50pF VOUTEN GND 50ΩVA 0.8V 50% 50% 4.0V tOPEN VOUT VA 0.8V 50Ω +5V 1K 50pF VA VOUTEN OUT IN 1 IN 16 IN 2 - GND IN 15A2 0.8V OUTPUT90% 10% tON(EN) tOFF(EN) 4.0VVA VOUT EN 50Ω +10VIN 1 1K 50pF IN 2 - VA VOUT IN 16 Spec Number 518022

Burn-In/Life Test Circuits DYNAMIC BURN-IN AND LIFE TEST CIRCUIT NOTES: R = 1kΩ± 5% C1 = C2 = 0.01µF ±10%, 1 each per socket, minimum D1 = D2 = 1N4002, 1 each per board, minimum Input Signals: square wave, 50% duty cycle, 0V to 15V peak±10% F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16 NOTES: 1. The above test circuits are utilized for all package types. 2. The Dynamic Test Circuit is utilized for all life testing. STATIC BURN-IN TEST CIRCUIT NOTES: R = 1kΩ± 5%, 1/4W C1 = C2 = 0.01µF minimum, 1 each per socket, minimum Irradiation Circuit HS-1840RH 28 LEAD DIP NOTE: All irradiation testing is performed in the 28 lead CerDIP package. R R GND +VS R 14F4 F3 -VS R R R GND VR +VS R -VS 1K Ω +15V +1V +5V NC NC -15V Spec Number 518022

ADDRESS INPUT BUFFER AND LEVEL SHIFTER ADDRESS DECODER MULTIPLEX SWITCH NN N N P N P N PPP LEVEL SHIFTER ADD IN. 200Ω V R1 NNN N P PP P R3 R4 OVERVOLTAGE PROTECTION LEVEL SHIFTED ADDRESS TO DECODE P LEVEL SHIFTED ADDRESS TO DECODE V REF REF ENABLE PPP P P N A0 OR A0 A1 OR A1 A2 OR A2 TO SWITCH N N N NA3 OR A3 OUT IN P NN P P S D FROM DECODE Spec Number 518022

Harris - Space Level Product Flow SEM - Traceable to Diffusion Method 2018, Modified This device does not meet MIL-STD-883 Method 2018.3 Class S minimum metal step coverage of 50%. The metal does meet the intent of the Class S requirement by meeting the current density requirement of <2E5 A/cm 2. Calculation based on con- tinuous current of 10mA. Data can be provided upon request. Wafer Lot Acceptance Method 5007 Internal Visual Inspection (Note 1) Gamma Radiation Assurance Tests Method 1019 100% Nondestructive Bond Pull Method 2023 Customer Pre-Cap Visual Inspection (Notes 1, 2) Temperature Cycling Method 1010 Condition C Constant Acceleration Method 2001 Y1 30KG Particle Impact Noise Detection Method 2020, Condition A 20G Marking and Serialization X-Ray Inspection Method 2012 Initial Electrical Tests (T0) Static Burn-In 72 Hour, +125 oC (Min) Method 1015 Condition A Room Temperature Electrical Tests (T1) Burn-In Delta Calculation (T0-T1) PDA Calculation 3% Functional 5% Subgroups 1, 7,Δ Dynamic Burn-In 240 Hours at +125 oC or equivalent Method 1015 Condition A Electrical Tests Subgroups 1, 7, 9 (T2) Burn-In Delta Calculation (T0 - T2) PDA Calculation 3% Functional 5% Subgroups 1, 7,Δ Electrical Test +125 oC, -55oC Alternate Group A Inspection Method 5005 Fine and Gross Leak Tests Method 1014 Customer Source Inspection (Note 2) Group B Inspection (Notes 2, 4) Method 5005 Group D Inspection (Notes 2, 4) Method 5005 External Visual Inspection Method 2009 Data Package Generation (Note 3) NOTES: 1. Visual Inspection is performed to MIL-STD-883 Method 2010, Condition A. 2. These steps are optional, and should be listed on the purchase order if required. 3. Data package contains: Assembly Attributes (post seal) Test Attributes (includes Group A) -55 oC, +25oC, +125oC Shippable Serial Number List Radiation Testing Certificate of Conformance Wafer Lot Acceptance Report (includes SEM report) X-Ray Report and Film Test Variables Data, (Table 5 Parameters only) +25 oC Initial Test +25oC Interim Test 1 +25oC Interim Test 2 +25oC Delta Over Burn-In 4. Group B data package contains Attributes Data and Variables Data, (Table 5 Parameters only). Group D data package contains Attributes only. Harris -8 Product Flow Internal Visual Inspection, Alternate Condition B (Note 1) Gamma Radiation Assurance Tests Method 1019 Customer Pre-Cap Visual Inspection (Notes 1, 2) Temperature Cycling Method 1010 Condition C (50 Cycles) Constant Acceleration Method 2001 Y1 30kG Fine and Gross Leak Tests Method 1014 Marking Initial Electrical Tests (T0) Dynamic Burn-In 160 Hours, +125 oC Method 1015 or Equivalent Condition D Electrical Tests Subgroups 1, 7, 9 (T1) Method 5004 PDA Calculation 5% Subgroups 1, 7 Method 5004 Electrical Test +125 oC, -55oC Method 5004 Alternate Group A Inspection Method 5005 Customer Source Inspection (Note 2) Group B Inspection (Notes 2, 4) Method 5005 (Optional) Group C Inspection (Notes 2, 4) Method 5005 (Optional) Group D Inspection (Notes 2, 4) Method 5005 (Optional) External Visual Inspection Method 2009 Data Package Generation (Note 3) NOTES: 1. Visual inspection is performed to MIL-STD-883 Method 2010, Alternate Condition B. 2. These steps are optional, and should be listed on the purchase order if required. 3. Data Package Contents: Test Attributes (including Group A) -55 oC, +25oC, +125oC Radiation Testing Certificate of Conformance 4. Group B, C and D data package contains Attributes Data only. Spec Number 518022

DIE DIMENSIONS: 110 x 159 x 11mils METALLIZATION: Type: Al Thickness: 12.5k Å ± 2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ DIE ATTACH: Material: Gold Eutectic Temperature: Sidebrazed CerDIP - 460 oC (Max) Flatpack - 460oC (Max) WORST CASE CURRENT DENSITY: Modified SEM LEAD TEMPERATURE (10s Soldering): <275oC PROCESS: CMOS-DI Metallization Mask Layout HS-1840RH IN7 IN6 IN5 IN4 IN3 IN2 IN1 ENABLE VREF GND IN8 OUT IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 Spec Number 518022

NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N,N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa C A - BM DS S eA F28.6MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)

28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.490 - 37.85 5 E 0.500 0.610 12.70 15.49 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N2 8 2 8 8 Rev. 0 4/94 Ceramic Dual-In-Line Frit Seal Packages (CerDIP) HS-1840RH Spec Number 518022

NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum lim- its of lead dimensions b and c or M shall be measured at the cen- troid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. -D- -C-

0.004 H A - BM DS S

-A- -B-

0.036 H A - BM DS S

e E A Q L D A SEATING AND LE2 E3 E3 BASE PLANE -H- b C M (c) (b) SECTION A-A BASE LEAD FINISH METAL PIN NO. 1 ID AREA A M K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B)

28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.740 - 18.80 3 E 0.460 0.520 11.68 13.21 - E1 - 0.550 - 13.97 3 E3 0.030 - 0.76 - 7 e 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.00 - 0.00 - 6 N2 8 2 8- Rev. 0 5/18/94 Ceramic Metal Seal Flatpack Packages (Flatpack) HS-1840RH Spec Number 518022