HL15604 HYNIX | Alldatasheet
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Hyundai Electronics Industries System IC Division
- General Description The HL14104 is 1/4 duty LCD display driver. It can drive directly maximum 164 segments. Also it has four general purpose output ports and a key scan function that accepts input from up to 30 keys. 2. Features 1/4 duty - 1/2 bias 1/4 duty - 1/3 bias Input 5 pins, Output 6 pins
- Port ( Including the LCD segment port )
- RC oscillator 17.2 14.0 (1.6) 0.15 1.0 0.12.7 0.35 1.0 0.8 1 16 3348 17.2 14.0 0.81.0 1.0 12.0 10.0 0.15 1.7 max0.18 1 16 12.0 10.0 0.5 1.25 1.25 0.1 0.5 0.5 Package Dimensions
64 QFP (14 × 14) 64 QFP (10 × 10)
Unit : mm Unit : mm (1.6)
- Block Diagram CLOCK GENERATOR KEY SCAN COMMOM DRIVER LCD BIAS SVD OSC SEGMENT DRIVER COM4 COM3 COM2 COM1 SEG39 SEG5 SEG4 / P4 SEG1 / P1 LCD DISPLAY & CONTROL REGISTER SERIAL I/O SI SO SCK CE VDD VSS RESET CLOCK KS6 KS5 KS4 KS3 KS2 KS1 KIN5 KIN4 KIN3 KIN2 KIN1 TEST CONTROLTEST VCL1 VCL2 KS1 / SEG40 KS2 / SEG41
- Pin Diagram KS6 KIN1 KIN2 KIN3 KIN4 KIN5 TEST VDD VCL1 VCL2 VSS OSC SO CE SCK SI HL14104 SEG1 / P1 SEG2 / P2 SEG3 / P3 SEG4 / P4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 KS5 KS4 KS3 KS2 / SEG41 KS1 / SEG40 COM4 COM3 COM2 COM1 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17
- Pin Description PIN Name I/O Pin Number Contents SEG[41:1] O 41 LCD SEG Pins share P1,P2,P3 and P4 COM [4:1] O 4 LCD Common Pins OSC I/O 1 Oscillator Input Pin KS[6:1] O 6 Key Scan Output Pins KIN[5:1] I 5 Key Scan Input Pins CE I 1 Serial I/O Control Pin SCK I 1 Serial I/O Clock Pin SO O 1 Serial I/O Data Output Pin VDD I 1 Power Supply Pin VSS I 1 Ground Pin VCL[2:1] I 2 LCD Bias Pins SI I 1 Serial I/O Data Input Pin TEST I 1 Test Pin. “ 1 ” Test mode , “ 0 ” Normal Mode P[4:1] O 4 Output Port share SEG[4:1]
- Serial I/O Data Format 1) Writing Mode CE SCK SI SO 0 1 0 0 0 0 1 0 D1 D2 D3XX A0 A1 A2 A3 A4 A5 A6 A7 D41 D42 D43 D44 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 0 Display data Control data DD CE SCK SI SO 0 1 0 0 0 0 1 0 D45 D46 XX A0 A1 A2 A3 A4 A5 A6 A7 D83 D84 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Display data Fixed data DD CE SCK SI SO 0 1 0 0 0 0 1 0 D85 D86XX A0 A1 A2 A3 A4 A5 A6 A7 D123 D124 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Display data Fixed data DD i )SCK is stopped at the low level 0 0 CE SCK SI SO 0 1 0 0 0 0 1 0 D125 D126XX A0 A1 A2 A3 A4 A5 A6 A7 D163 D164 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Display data Fixed data DD
A7~A0 : 42H address D164~D1 : Data of LCD display registers S0, S1 : Sleep control data K0, K1 : Key scan output / Segment output selection data P0, P1 : Segment output / general-purpose output port selection data SC : Segment on / off control data DR : 1/2 bias or 1/3 bias drive selection data ii )SCK is stopped at the high level CE SCK SI SO 1 0 0 0 0 1 0 0 D2 D3XX A0 A1 A2 A3 A4 A5 A6 A7 D41 D42 D43 D44 0 0 S0 S1 K0 K1 P0 P1 SC DR 0 0 Display data Control data DD CE SCK SI SO 1 0 0 0 0 1 0 0 D46XX A0 A1 A2 A3 A4 A5 A6 A7 D83 D84 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Display data Fixed data DD D45 CE SCK SI SO 1 0 0 0 0 1 0 0 D86XX A0 A1 A2 A3 A4 A5 A6 A7 D123 D124 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Fixed data DD D85 0 0 0 0 Display data CE SCK SI SO 1 0 0 0 0 1 0 0 D126XX A0 A1 A2 A3 A4 A5 A6 A7 D163 D164 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Fixed data DD D125 0 0 Display data
2) Reading Mode A7 ~ A0 : 43H address K30 ~ K1 : Key data SA : Sleep acknowledge i ) SCK is stopped at the low level CE SCK SI SO 01000011XX XX K1 K2 K3 K4 K5 K6 K7 K8 K9 K11 K29K10 K30 XXK12 SAXX A7A5A3A1 A6A4A2A0 Output data X : don ’t care CE SCK SI SO 1000011XX XX K1 K2 K3 K4 K5 K6 K7 K8 K9 K11 K29K10 K30 XXK12 SAXX A7A5A3A1 A6A4A2A0 Output data X : don ’t care ii ) SCK is stopped at the high level
- Registers 1) Display Registers Output Pin COM1 COM2 COM3 SEG1 D1 D2 D3 SEG2 D5 D6 D7 SEG3 D9 D10 D11 SEG4 D13 D14 D15 SEG5 D17 D18 D19 SEG6 D21 D22 D23 SEG7 D25 D26 D27 SEG8 D29 D30 D31 SEG9 D33 D34 D35 SEG10 D37 D38 D39 SEG11 D41 D42 D43 SEG12 D45 D46 D47 SEG13 D49 D50 D51 SEG14 D53 D54 D55 SEG15 D57 D58 D59 SEG16 D61 D62 D63 SEG17 D65 D66 D67 SEG18 D69 D70 D71 SEG19 D73 D74 D75 SEG20 D77 D78 D79 SEG21 D81 D82 D83 SEG22 D85 D86 D87 SEG23 D89 D90 D91 SEG24 D93 D94 D95 SEG25 D97 D98 D99 SEG26 D101 D102 D103 SEG27 D105 D106 D107 SEG28 D109 D110 D111 SEG29 D113 D114 D115 SEG30 D117 D118 D119 SEG31 D121 D122 D123 SEG32 D129 D130 D131SEG33 D133 D134 D135SEG34 D137 D138 D139SEG35 D141 D142 D143SEG36 D145 D146 D147SEG37 D149 D150 D151SEG38 D153 D154 D155SEG39 D157 D158 D159SEG40 D161 D162 D163SEG41 D125 D126 D127 COM4 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96 D100 D104 D108 D112 D116 D120 D124 D132 D136 D140 D144 D148 D152 D156 D160 D164 D128
2) Control Registers Bias Selection 1/3 Bias Bias Selection Register Sleep Mode Control Register DR 1 1/2 Bias Key Scan / Segment output Selection Register Port Mode Register Port Data Register Maximum number of Input PinsControl Data K0 K1 0 0 0 1 1 X Output Pin Status KS1/SEG40 KS2/SEG41 KS1 KS2 SEG40 KS2 SEG40 SEG41 Control Data P0 P1 0 0 0 1 1 0 Output Pin Status SEG1/ P1 SEG2/ P2 SEG1 SEG2 P1 P2 P1 P2 1 1 SEG3/ P3 SEG4/ P4 SEG3 SEG4 SEG3 SEG4 P3 SEG4 P1 P2 P3 P4 Output Pin SEG1 / P1 SEG2 / P2 SEG3 / P3 SEG4 / P4 Port Data Register D13 Control Data S0 S1 0 0 0 1 1 0 1 1 Operating Stopped Stopped Stopped Normal Sleep Sleep Sleep Mode OSC Oscillator Output Pin Status KS1 KS2 H H L L L L H H KS3 KS4 H H L L L L H H KS5 KS6 H H L H H H H H Operating L L L SEG / COMMON Output
Display On/Off Control Register ADDRESS Read Data K1 ~ K30, SA43 H Key Scan Data & Sleep Acknowledge Read Control Data SC Display Status On Off SEG1 ~ SEG41 KS1 / SEG40 KS2 / SEG41 KS3 KS4 KS5 KS6 KIN1 KIN2 KIN3 KIN4 KIN5 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30
- Key Scan Function 1) Key Scan Timing The key scan period is 384T. The HL14104 scans the key twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request 800T after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the key again.Thus the HL14104 cannot detect a key press shorter than 800T. 768 T KS1 KS2 KS3 KS4 KS5 KS6 Key on *) *) *) In sleep mode the high / low state of these pins is determined by the S0,S1 bits in the control data. Key scan output signals are not output from pins that are set low. 2) In normal mode
- The pins KS1 to KS6 are set high.
- When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set.
- If a key is pressed for longer than 800T ( where T=1/ fosc ) the HL14104 outputs a key data read request (a low level on SO pin) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, SO will be set high.
- After the controller reads the key data, the key data read requests is cleared ( SO pin is set high ) and the HL14104 performs another key scan. Also note that SO pin, being an open-drain output, requires a pull-up resistor.
3) In sleep mode
- The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the sleep mode control register.
- If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key pre- sses are recognized by determining whether multiple key data bits are set.
- If a key is pressed for longer than 800T ( where T=1/ fosc ) the HL14104 outputs a key data read request (a low level on SO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, SO will be set high.
- After the controller reads the key data, the key data read request is cleared ( SO is set high ) and the HL14104 performs another key scan. However this does not clear sleep mode. Also note that SO, being an open-drain output, requires a pull-up resistor ( between 1 and 10 K).
- Sleep mode key scan example Example : S0 = 0, S1 = 1 ( sleep with only KS6 high ) Key input 2 Key Scan CE SI SO
800 T 800 T 800 T
Key data read Key data read Key data read Key data read request Key data read request
(KS6 line) Key Scan CE SI SO
800 T 800 T
Key data read Key data read Key data read request “ L ” KS1 “ L ” KS2 “ L ” KS3 “ L ” KS4 “ L ” KS5 “ H ” KS6 KIN1 KIN2 KIN3 KIN4 KIN5 When any one of these keys is pressed, the oscillator on the OSC pin is started and the keys are scanned. *) These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operation due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. Multiple Key Presses Although the HL14104 is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KIN1 to KIN5 input pin lines, or mult - iple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Application that do not recognize multiple key presses of threes or keys should check the key data for three or more 1 bits and ignore such data.
- LCD Display Function COM1 1) 1/4 Duty 1/2 Bias Waveforms VCL1,VCL2 VDD VCL1,VCL2 VDD COM2 VCL1,VCL2 VDD COM3 VCL1,VCL2 VDDSEG1 ~ SEG41 “ Off ” at COM1 ~ COM4 SEG1 ~ SEG41 “ On ” at COM1 ~ COM4 VCL1,VCL2 VDD VCL1,VCL2 VDD VCL1,VCL2 VDD VCL1,VCL2 VDD VCL1,VCL2 VDD VCL1,VCL2 VDD SEG1 ~ SEG41 “ On ” at COM1 only SEG1 ~ SEG41 “ On ” at COM2 only SEG1 ~ SEG41 “ On ” at COM3 only SEG1 ~ SEG41 “ On ” at COM4 only SEG1 ~ SEG41 “ On ” at COM1 and COM3 VCL1,VCL2 VDD COM4 VCL1,VCL2 VDD VCL1,VCL2 VDD VCL1,VCL2 VDD SEG1 ~ SEG41 “ On ” at COM2 and COM3 SEG1 ~ SEG41 “ On ” at COM2 and COM4 SEG1 ~ SEG41 “ On ” at COM1, COM2 and COM3 VCL1,VCL2 VDDSEG1 ~ SEG41 “ On ” at COM1 and COM2
2) 1/4 Duty 1/3 Bias Waveforms COM2 COM3 SEG1 ~ SEG41 “ Off ” at COM1 ~ COM4 SEG1 ~ SEG41 “ On ” at COM1 ~ COM4 SEG1 ~ SEG41 “ On ” at COM1 only SEG1 ~ SEG41 “ On ” at COM2 only SEG1 ~ SEG41 “ On ” at COM3 only SEG1 ~ SEG41 “ On ” at COM1 and COM2 SEG1 ~ SEG41 “ On ” at COM1 and COM3 SEG1 ~ SEG41 “ On ” at COM2 and COM3 VDD VCL1 VCL2 VDD VCL1 VCL2 VDD VCL1 VCL2 COM4 VDD VCL1 VCL2 VDD VCL1 VCL2 VDD VCL1 VCL2 VDD VCL1 VCL2 VDD VCL1 VCL2 VDD VCL1 VCL2 VDD VCL1 VCL2 VDD VCL1 VCL2 VDD VCL1 VCL2 SEG1 ~ SEG41 “ On ” at COM1, COM2 and COM3 VDD VCL1 VCL2 SEG1 ~ SEG41 “ On ” at COM4 only VDD VCL1 VCL2 VDD VCL1 VCL2 SEG1 ~ SEG41 “ On ” at COM2 and COM4
- Power On Reset 1) Supply Voltage Detection ( SVD ) The SVD generates an output signal and results the system when power is first applied and when the voltage drops. When the power supply voltage is less than or equal to the power down detection voltage, which is 2.0V, typical. To assure that this function operates reliably, a capacitor must be added to the power supply voltage Vdd rise time when power is first applied and the power supply voltage Vdd fall time when the voltage drops are both at least 1ms. 2) System Reset If at least 1ms is assured as the supply voltage Vdd rise time when power is applied, a system reset will be applied by the SVD output signal when the supply voltage is brought up. If at least 1ms is assured as the supply voltage Vdd fall time when power drops, a system reset will be applied in the same manner by the SVD output signal when the supply voltage is lowered. t1 t2 Power supply voltage Vdd rise time : t1 > 1ms Power supply voltage Vdd fall time : t2 > 1ms 3) Internal block states during the reset period
- Clock generator Reset is applied and the base clock is stopped and OSC pin state is low.
- Common , segment drive and display data Reset is applied and the display is turned off but display data is not cleared.
- Key scan Reset is applied and all the key data is set to low. Display and control data transfer Undefined System reset period Defined VDD CE Internal data SVD SVD
- Power Down Mode Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common outputs will also go low, and the oscillator on the OSC pin will stop ( it will be started by a key press). This reduces power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. Note that the SEG1/P1 to SEG4/P4 outputs can be used as general purpose output ports according to the state of the P0 and P1 control data bits, even in sleep mode. 4) Output pin states during the reset period
- SEG1/P1 to SEG4/P4 : Low *)
- SEG5 to SEG39 : Low
- COM1 to COM4 : Low
- KS1/SEG40, KS2/SEG41 : Low *)
- KS3 to KS5 : X **)
- KS6 : High
- SO : High ***) *) These output pins are forcibly set to the segment output function and held low. ) When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred. *) Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 §Ú is required. This pin remains high during the reset period even if a key data read operation is performed.
- Oscillator Port Internal clock C R Oscillator circuit consists of internal R and C. No Capacitor OSC Open OSC Using Capacitor C HL14104 has internal resistor and capacitor, so it can be oscillation without external capacitor. If you want to adjust the clock period then you adjust it using external capacitor.
Absolute Maximum Rating at Ta =25 ¡É, Vss = 0V 13. Electrical Characteristics Parameter Symbol Condition Maximum supply voltage VDD max VDD Rating unit -0.3 to +7.0 V Input voltage Vin1 CE,SCK,SI -0.3 to +7.0 V Vin2 OSC,KIN1 to KIN5, TEST,VCL1,2 -0.3 to VDD+0.3 V Output voltage Vout1 SO -0.3 to +7.0 V Vout2 OSC, SEG1 to SEG41, COM1 to COM4, KS1 to KS6, P1 to P4 -0.3 to VDD+0.3 V Output current Iout1 SEG1 to SEG41 300 uA Iout2 COM1 to COM4 3 mA Iout3 KS1 to KS6 1 mA Iout4 P1 to P4 5 mA Allowable power dissipation Pd max Ta = 85 ¡É 200 mW Operating temperature Topr -40 to +85 ¡É Storage temperature Tstg -55 to +125 ¡É Recommend operating ranges at Ta = -40 ¡É to +85 ¡É, Vss = 0V Note : *. Since SO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and load capacitance CL . Parameter Symbol Condition Supply voltage VDD unit V Input voltage VCL1 V VCL2 V Input high level voltage VIH1 V VIH2 pFCOSC Guaranteed oscillation range KHz Data setup time ns Data hold time ns VILInput low level voltage Recommended external capacitance CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Rise time Fall time SO output delay time SO rise time fOSC tds tdh tcp tcs tch t0H toL tr tf tdc tdr V V max 6.0 VDD VDD 6.0 100 VDD
0.2 VDD
4.5
0.8 VDD
0.6 VDD
CE,SCK,SI KIN1 to KIN5 CE,SCK,SI,KIN1 to KIN5 OSC SO,RPU = 4.7k Ω , CL = 10pF* SO,RPU = 4.7k Ω , CL = 10pF* OSC SCK,SI SCK,SI CE,SCK CE,SCK CE,SCK SCK SCK CE,SCK,SI CE,SCK,SI ns ns ns ns ns 160 160 160 160 160 ns160 ns160 µ s1.5 µ s1.5
Note : *. Excluding the bias voltage generation divider resistor built into VCL1 and VCL2 Parameter Symbol Condition Hysteresis VH unit V Supply voltage detection SVD V IIH µ AInput high level current IIL µ A VIFInput floating voltage µ A Pull-down resistance V Output off leakage current V RPD Input low level current Output high level voltage Output low level voltage Output middle level voltage* IOFFH VOH1 VOH2 VOH3 VOH4 VOL1 VOL2 VOL3 VOL4 VOL5 VMID1 VMID2 V k Ω max 3.0 5.0 6.0
0.05 VDD
1.5 -5.0 VDD -1.2 VDD -1.0 CE,SCK,SI CE,SCK,SI : V1 = 6.0V CE,SCK,SI : V1 = 0V KIN1 to KIN5 KIN1 to KIN5 : VDD = 5.0V COM1 to COM4 : 1/2 bias, Io = ¡¾100 µ A SEG1 to SEG41 : 1/3 bias, Io = ¡¾20 µ A SO : VO = 6.0V KS1 to KS6 : I0 = -500 µ A P1 to P4 : I0 = -1mA SEG1 to SEG41 : I0 = -20 µ A COM1 to COM4 : I0= -100 µ A SO : I0 = 1 mA V V V V V 1.5 1.0 1.0 VDD -1.0 V1.0 V0.5 V1/2 VDD -1.0 V2/3 VDD -1.0 Electrical Characteristics for the Allowable Operating Ranges KS1 to KS6 : I0 = 25 µ A P1 to P4 : I0 = 1mA SEG1 to SEG41 : I0 = 20 µ A COM1 to COM4 : I0 = 100 µ A SEG1 to SEG41 : 1/3 bias, Io = ¡¾20 µ A COM1 to COM4 : 1/3 bias, Io = ¡¾100 µ A COM1 to COM4 : 1/3 bias, Io = ¡¾100 µ A VMID3 VMID4 VMID5 V1/3 VDD -1.0 V2/3 VDD -1.0 V1/3 VDD -1.0 Oscillator frequency fOSC KHz7045OSC : C = 0 typ O.1VDD 2.0 VDD -0.5 100 0.5 0.1 VDD -1.0 1/2 VDD +1.0 2/3 VDD +1.0 1/3 VDD +1.0 2/3 VDD +1.0 1/3 VDD +1.0 Current drain IDD1 µ A100Sleep mode IDD2 µ A700VDD = 6.0V, output open, 1/2 bias, f OSC = 38 KHz 350 IDD3 µ A600VDD = 6.0V, output open, 1/3 bias, f OSC = 38 KHz 300 0.2
- Application LCD panel (up to 164 segments) COM2 COM3 COM4 P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4 SEG5 SEG39 S E G K S S E G K S K S K S K S K S ( SEG40) ( SEG41) ¡Æ¡Æ CE SCK SI SO VCL1 VCL2 VDD VSS TEST OSC K I N K I N K I N K I N K I N +5 V From the controller To the controller To the controller power supply *2) ( p 1) ( p 2) ( p 3) ( p 4) ( general-purpose output ports) Used with the backlight controller or other circuit. Key matrix (up to 30 keys) Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL14104 is reset by the SVD. *2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k Ω ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. 1/2 bias ( for use with normal panels ) C ≥ 0.047uF *1) C COM1
LCD panel (up to 164 segments) COM1 COM2 COM3 P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4 SEG5 SEG39 S E G K S K S K S K S K S ¡Æ¡Æ CE SCK SI SO VCL1 VCL2 VDD VSS TEST OSC K I N K I N K I N K I N K I N +5 V From the controller To the controller To the controller power supply *2) ( p 1) ( p 2) ( p 3) ( p 4) ( general-purpose output ports) Used with the backlight controller or other circuit. Key matrix (up to 30 keys) Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL14104 is reset by the SVD. *2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k Ω ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. 1/3 bias ( for use with normal panels ) C ≥ 0.047uF *1) C C S E G K S ( SEG41) ( SEG40) COM1
LCD panel (up to 164 segments) COM2 COM3 COM4 P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4 SEG5 SEG39 K S K S K S K S ¡Æ¡Æ CE SCK SI SO VCL1 VCL2 VDD VSS TEST OSC K I N K I N K I N K I N K I N +5 V From the controller To the controller To the controller power supply *2) ( p 1) ( p 2) ( p 3) ( p 4) ( general-purpose output ports) Used with the backlight controller or other circuit. Key matrix (up to 30 keys) Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL14104 is reset by the SVD. *2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k Ω ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. 1/3 bias ( for use with large panels ) C ≥ 0.047uF *1) S E G K S S E G K S C C R R R ( SEG41) ( SEG40) COM1