GMS87C2120

GMS81C2020 HYNIX | Alldatasheet

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Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 1 GMS81C2020 / GMS81C2120 CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver 1. OVERVIEW

1.1 Description

The GMS81C2020 and GMS81C2120 are an advanced CMOS 8-bit microcontroller with 20K/12K bytes of ROM. These are a powerful microcontroller which provides a highly flexible and cost effective solution to many VFD applications. These provide the following standard features: 20K/12K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, 8-bit A/D convert- er, 10-bit High Speed PWM Output, Programmable Buzzer Driving Port, 8-bit Basic Interval Timer, 7-bit Watch dog Timer, 8-bit, Serial Peripheral Interface, on-chip oscillator and clock circuitry. They also come with high voltage I/O pins that can directly drive a VFD(Vacuum Fluorescent Display). In addition, the GMS81C2020 and GMS81C2120 support power sav- ing modes to reduce power consumption. This document is only explained for the base of GMS81C2020(GMS81C2120), the eliminated functions are same as below. [The * Mark Devices are OTP Version] Device name ROM Size RAM Size Ports Package GMS81C2020 20Kbytes 448bytes R0,R1,R2,R3,R4,R5,R6,R7 64 SDIP, 64MQFP, 64LQFP, 64TQFP GMS81C2012 12Kbytes 448bytes R0,R2,R3,R5,R6 64SDIP, 64MQFP, 64LQFP, 64TQFP *GMS87C2020 20Kbytes (EPROM) 448bytes R0,R1,R2,R3,R4,R5,R6,R7 64SDIP, 64MQFP, 64LQFP, 64TQFP GMS81C2120 20Kbytes 448bytes R0,R1,R2,R3,R4,R5,R6,R7 42SDIP, 44MQFP, 40PDIP GMS81C2112 12Kbytes 448bytes R0,R2,R3,R5,R6 42SDIP, 44MQFP, 40PDIP *GMS87C2120 20Kbytes (EPROM) 448bytes R0,R1,R2,R3,R4,R5,R6,R7 42SDIP, 44MQFP, 40PDIP

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 2 preliminary Nov. 1999 Ver 0.0

1.2 Features

• 20K/12K bytes ROM(EPROM)
• 448 Bytes of On-Chip Data RAM (Including STACK Area)
• Minimum Instruction Execution time : - 1uS at 4MHz ( 2cycle NOP Instruction )
• One 8-Bit Basic Interval Timer
• One 7-Bit Watch Dog Timer
• Two 8-Bit Timer/Counters
• 10-Bit High Speed PWM Output
• One 8-bit Serial Peripheral Interface
• Two external interrupt ports
• One Programmable 6-Bit Buzzer Driving port
• 60 I/O Lines - 56 Programmable I/O pins : 30 high-voltage pins (40V,max) - 3 Input Only pins : 1 high-voltage pin - 1 Output Only pin
• Eight Interrupt Sources - 2 By External Sources (INT0, INT1) - 2 By Timer/Counter Sources (Timer0, Timer1) - 4 By Functional Sources (SPI,ADC,WDT,BIT)
• 12-Channel 8-Bit On-Chip Analog to Digital Con- verter
• Oscillatior : - Crystal - Ceramic Resonator - External RC Oscillator - Internal RCWDT Oscillatior
• Low Power Dissipation Modes - STOP mode - Wake-up Timer Mode - Standby Mode - Watch Mode - Subactive Mode
• Operating Voltage : 4.0V ~ 5.5V (at 4.5MHz)
• Operating Frequency : 0.4MHz ~ 4.5MHz
• Subclock : 32.768KHz Crystal Oscillator
• Enhanced EMS Improvement Power Fail Processor ( Noise Immunity Circuit ) *where, Total I/O is all ports except power and ground ports Development Tools The GMS800 family is supported by a full-featured macro assembler, an in-circuit emulators CHOICE-Dr.™, and add-on board type OTP writer Dr.Writer™ . Device name Total I/O Normal I/O High Voltage I/O Input Only Output Only GMS81C2020 60 pins 26 pins 30 pins 3 pins 1 pins GMS81C2012 60 pins 26 pins 30 pins 3 pins 1 pins GMS81C2120 38 pins 13 pins 21 pins 3 pins 1 pins GMS81C2112 38 pins 13 pins 21 pins 3 pins 1 pins In Circuit Emulator CHOICE-Dr. Assembler HME Macro Assembler OTP Writer Dr.Writer

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 3 2. BLOCK DIAGRAM (GMS81C2020) ALU Accumulator Interrupt Controller Data Memory 8-bit ADC 8-bit Counter Timer/ Program Memory Data Table PC 8-bit Basic Timer Interval Watchdog Timer PC R4 R5 PSW System controller Timing generator System Clock Controller Clock Generator RESETB XI XO R40 / T0O R41 R50 R20~R27 VDD VSS Power Supply 8-bit serial R51 R52 R53 / SCLK R54 / SIN R55 / SOUT R56 / PWM1O/T1O R57 R10~R17 R30~R35 Interface Buzzer Driver R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7 (448 bytes) 8-bit PWM AV DD AV SS ADC Power Supply Stack Pointer R04 R03/BUZO R02/EC0 R00/INT0 Vdisp/RA R70 / AN8 R71 / AN9 R72 / AN10R42 R43 R73 / AN11 Sub System Clock Controller SXI SXO R05 R06 R07 R01/INT1

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 4 preliminary Nov. 1999 Ver 0.0 3. PIN ASSIGNMENT (GMS81C2020) R40 R42 R43 R50 R51 R52 R53 R54 R55 R56 R57 RESETB XI XO VSS SCLK SIN SOUT PWM1O/T1O SXI SXO AN0 R74 R75 AV SS R60 R61 R62 R63 R64 R65 R66 R67 R70 R71 R72 R73 AV DD AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 RA R35 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 R04 R03 R02 R01 R00 V DD R51 R30 R31 R32 R33 R34 R35 RA R40 R41 R42 R43 R50 T0O Vdisp R66 R04 R03 R02 R01 R00 VDD AV DD R73 R72 R71 R70 R67 AN6 AN8 AN7 R27 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R26 R06 R05 R52 R54 R55 R56 R57 RESETB XI XO VSS R74 R75 AV SS R60 R61 R62 R63 R53 R64 R65 SIN SOUT PWM1O/T1O SXI SXO AN0 AN1 AN2 AN3 SCLK AN4 AN5 4932 64MQFP 64SDIP BUZO EC0 INT1 INT0 Vdisp R41 T0O AN9 AN11 AN10 INT0 EC0 INT1 BUZO

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 5 R06 R05 R04 R03 R02 R01 R00 V DD AV DD R73 R72 R71 R70 R67 R66 R65 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R54 R55 R56 R57 RESETB XI XO V SS R74 R75 AV SS R60 R61 R62 R63 R64 R27 R30 R31 R32 R33 R34 R35 R40 R41 R42 R43 R50 R51 R52 R53 64LQFP SIN SOUT PWM1O/T1O SXI SXO AN0 AN1 AN2 AN3 AN4 AN6 AN8 AN7 AN5 Vdisp T0O SCLK RA AN10 AN11 AN9 INT1 BUZO EC0 INT0

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 6 preliminary Nov. 1999 Ver 0.0 4. BLOCK DIAGRAM (GMS81C2120) ALU Accumulator Interrupt Controller Data Memory 8-bit ADC 8-bit Counter Timer/ Program Memory Data Table PC 8-bit Basic Timer Interval Watchdog Timer PC PSW System controller Timing generator System Clock Controller Clock Generator RESETB XI XO R20~R27 VDD VSS Power Supply 8-bit serial R53 / SCLK R54 / SIN R55 / SOUT R56 / PWM1O/T1O R57 R30~R34 Interface Buzzer Driver R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7 (448 bytes) 8-bit PWM AV DD AV SS ADC Power Supply Stack Pointer R04 R03/BUZO R02/EC0 R00/INT0 Vdisp/RA Sub System Clock Controller SXI SXO R05 R06 R07 R01/INT1

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 7 5. PIN ASSIGNMENT (GMS81C2120) R53 R54 R55 R56 R57 RESETB XI XO VSS SCLK SIN SOUT PWM1O/T1O AN0 AV SS R60 R61 R62 R63 R64 R65 R66 R67 AV DD AN1 AN2 AN3 AN4 AN5 AN6 AN7 RA R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R05 R04 R03 R02 R01 R00VDD R57 RESETB XI XO VSS AV SS R60 R61 R62 R63 R64 AN1 AN0 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 NC R55 R54 R53 RA R34 R33 R32 R31 R30 R56 R65 R67 AV DD VDD R00 R01 R02 R03 R04 NC R66 AN5 AN6 AN7 4233 44MQFP 42PDIP BUZO EC0 INT1 INT0 Vdisp R07 R06 AN2 AN3 AN4 INT0 INT1 EC0 BUZO SOUT SIN SCLK PWM1O/T1O

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 8 preliminary Nov. 1999 Ver 0.0 R53 R54 R55 R56 R57 RESETB XI XO VSS SCLK SIN SOUT PWM1O/T1O AN0 R60 R61 R62 R63 R64 R65 R66 R67 AN1 AN2 AN3 AN4 AN5 AN6 AN7 RA R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R05 R04 R03 R02 R01R00 V DD 40PDIP BUZO EC0 INT1INT0 V disp R07 R06

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 9 6. PACKAGE DIMENSION UNIT: INCH 2.280 2.260 0.022 0.016 0.050 0.030

0.070 BSC

0.140 0.120 min. 0.015 0.680 0.660

0.750 BSC

0-15° 64SDIP 0.012 0.008 0.205 max. 20.10 19.90 24.15 23.65 18.15 17.65 14.10 13.90 3.18 max. 0.50 0.35

1.00 BSC

SEE DETAIL "A" 1.03 0.73 0-7° 0.36 0.10 0.23 0.13 1.95 REF DETAIL "A" UNIT: MM 64MQFP

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 10 preliminary Nov. 1999 Ver 0.0 1.60 max. SEE DETAIL "A" 0.75 0.45 0-7° 0.15 0.05 1.00 REF DETAIL "A" UNIT: MM

10.00 BSC

12.00 BSC

0.38 0.22

0.50 BSC

1.45 1.35 64LQFP

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 11 7. PIN DESCRIPTIONS (GMS81C2020) V DD : Supply voltage. V SS: Circuit ground. AV DD : Supply voltage to the ladder resistor of ADC cir- cuit. To enhance the resolution of analog to digital convert- er, use independent power source as well as possible, other than digital power source. AV SS: ADC circuit ground. RESETB : Reset the MCU. X I: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. X O : Output from the inverting oscillator amplifier. SX I: Input to the internal subsystem clock operating cir- cuit. In addition, SXI serves the R74 pin when selected by the code option. SX O : Output from the inverting subsystem oscillator am- plifier. In addition, SXO serves the R75 pin when selected by the code option. RA(V disp): RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option.. R00~R07 : R0 is an 8-bit high-voltage CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Reg- ister can be used as outputs or inputs. In addition, R0 serves the functions of the various following special fea- tures. R10~R17 : R1 is an 8-bit high-voltage CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Reg- ister can be used as outputs or inputs. R20~R27 : R2 is an 8-bit high-voltage CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Reg- ister can be used as outputs or inputs. R30~R35 : R3 is an 6-bit high-voltage CMOS bidirectional I/O port. R3 pins 1 or 0 written to the Port Direction Reg- ister can be used as outputs or inputs. R40~R43 : R4 is an 8-bit CMOS bidirectional I/O port. R4 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R4 serves the func- tions of the following special features. R50~R57 : R5 is an 8-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R5 serves the func- tions of the various following special features. R60~R67 : R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R6 is shared with the ADC input. R70~R73 : R7 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R7 is shared with the ADC input. Port pin Alternate function RA V disp (High-voltage input power supply) Port pin Alternate function R00 R01 R02 R03 INT0 (External interrupt 0) INT1 (External interrupt 1) EC0 (Event counter input) BUZO (Buzzer driver output) Port pin Alternate function R40 T0O (Timer/Counter 0 output) Port pin Alternate function R53 R54 R55 R56 SCLK (Serial clock) SIN (Serial data input) SOUT (Serial data output) PWM1O (PWM1 Output) T1O (Timer/Counter 1 output) Port pin Alternate function R60 R61 R62 R63 R64 R66 R66 R67 AN0 (Analog Input 0) AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) AN4 (Analog Input 4) AN5 (Analog Input 5) AN6 (Analog Input 6) AN7 (Analog Input 7) Port pin Alternate function R70 R71 R72 R73 AN8 (Analog Input 8) AN9 (Analog Input 9) AN10 (Analog Input 10) AN11 (Analog Input 11)

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 12 preliminary Nov. 1999 Ver 0.0 PIN NAME In/Out Function VDD - Supply voltage VSS - Circuit ground RA (Vdisp) I(I) 1-bit high-voltage Input only port High-voltage input power supply pin RESETB I Reset signal input XI I Oscillation input XO O Oscillation output R00 (INT0) I/O (I) 8-bit high-voltage I/O ports External interrupt 0 input R01 (INT1) I/O (I) External interrupt 1 input R02 (EC0) I/O (I) Timer/Counter 0 external input R03 (BUZO) I/O (O) Buzzer driving output R04~R07 I/O R10~R17 I/O 8-bit high-voltage I/O ports R20~R27 I/O 8-bit high-voltage I/O ports R30~R35 I/O 6-bit high-voltage I/O ports R40 (T0O) I/O (O) 4-bit general I/O ports Timer/Counter 0 output R41~R43 I/O R50~R52 I/O 8-bit general I/O ports R53 (SCLK) I/O (I/O) Serial clock source R54 (SIN) I/O (I) Serial data input R55 (SOUT) I/O (O) Serial data output R56 (PWM1O/T1O) I/O (O) PWM 1 pulse output /Timer/Counter 1 output R57 I/O R60~R67 (AN0~AN7) I/O (I) 8-bit general I/O ports Analog voltage input R70~R73 (AN8~AN11) I/O (I) 4-bit general I/O ports AV DD - Supply voltage input pin for ADC AV SS - Ground level input pin for ADC

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 13 8. PIN DESCRIPTIONS (GMS81C2120) V DD : Supply voltage. V SS: Circuit ground. AV DD : Supply voltage to the ladder resistor of ADC cir- cuit. To enhance the resolution of analog to digital convert- er, use independent power source as well as possible, other than digital power source. AV SS: ADC circuit ground. RESETB : Reset the MCU. X I: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. X O : Output from the inverting oscillator amplifier. RA(V disp): RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option.. R00~R07 : R0 is an 8-bit high-voltage CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Reg- ister can be used as outputs or inputs. In addition, R0 serves the functions of the various following special fea- tures. R20~R27 : R2 is an 8-bit high-voltage CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Reg- ister can be used as outputs or inputs. R53~R57 : R5 is an 5-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R5 serves the func- tions of the various following special features. R60~R67 : R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R6 is shared with the ADC input. Port pin Alternate function RA V disp (High-voltage input power supply) Port pin Alternate function R00 R01 R02 R03 INT0 (External interrupt 0) INT1 (External interrupt 1) EC0 (Event counter input) BUZO (Buzzer driver output) Port pin Alternate function R53 R54 R55 R56 SCLK (Serial clock) SIN (Serial data input) SOUT (Serial data output) PWM1O (PWM1 Output) T1O (Timer/Counter 1 output) Port pin Alternate function R60 R61 R62 R63 R64 R66 R66 R67 AN0 (Analog Input 0) AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) AN4 (Analog Input 4) AN5 (Analog Input 5) AN6 (Analog Input 6) AN7 (Analog Input 7)

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 14 preliminary Nov. 1999 Ver 0.0 PIN DESCRIPTIONS (GMS81C2120) PIN NAME In/Out Function VDD - Supply voltage VSS - Circuit ground RA (Vdisp) I(I) 1-bit high-voltage Input only port High-voltage input power supply pin RESETB I Reset signal input XI I Oscillation input XO O Oscillation output R00 (INT0) I/O (I) 8-bit high-voltage I/O ports External interrupt 0 input R01 (INT1) I/O (I) External interrupt 1 input R02 (EC0) I/O (I) Timer/Counter 0 external input R03 (BUZO) I/O (O) Buzzer driving output R04~R07 I/O R20~R27 I/O 8-bit high-voltage I/O ports R30~R34 I/O 5-bit high-voltage I/O ports R53 (SCLK) I/O (I/O) 5-bit general I/O ports Serial clock source R54 (SIN) I/O (I) Serial data input R55 (SOUT) I/O (O) Serial data output R56 (PWM1O/T1O) I/O (O) PWM 1 pulse output /Timer/Counter 1 output R57 I/O R60~R67 (AN0~AN7) I/O (I) 8-bit general I/O ports Analog voltage input AV DD - Supply voltage input pin for ADC AV SS - Ground level input pin for ADC

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 15 9. PORT STRUCTURES

• RESETB
• XI, XO (Crystal Oscillator)
• XI, XO (RC Oscillator) Internal RESETB Mask version only VSS VDD VSS XO XI Internal System clock stop or mainclk off VDD VDD VDD VSS VSS XO XI Internal System clock stop or mainclk off VDD VDD VDD VSS

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 16 preliminary Nov. 1999 Ver 0.0

• SXI, SXO (Sub Oscillator)
• R40 / T0O
• R41~R43, R50~R52, R57 VSS SXO SXI Internal System clock stop or subclk off VDD VDD VDD VSS VDD VSS Data Bus Data Bus Data Bus Read Function Select Funcout [T0O] Data Register Direction Register V DD Metal Option Data Bus Data Bus Data Bus Data Register Direction Register Read V DD Metal Option

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 17

• R53 / SCLK
• R54 / SIN
• R55 / SOUT VDD VSS Data Bus Data Bus Data Bus Read Data Register Direction Register Funcout [SCLKOUT] N-MOS Open Drain sel. Funcout_sel Funcin_sel V DD Metal Option Funcin [SCLKIN] VDD VSS Data Bus Data Bus Data Bus Read Data Register Direction Register N-MOS Open Drain sel. Funcin_sel V DD Metal Option Funcin [SIN] VDD VSS Data Bus Data Bus Data Bus Read Data Register Direction Register N-MOS Open Drain sel. V DD Metal Option Funcin [IOSWIN] Funcout [SOUT] Funcout_sel IOSWB

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 18 preliminary Nov. 1999 Ver 0.0

• R56 / PWM1O / T1O
• R60~R67 [AN0 ~ AN7], R70~R74 [AN8 ~ AN11]
• RA / Vdisp VDD VSS Data Bus Data Bus Data Bus Read Data Register Direction Register N-MOS Open Drain sel. V DD Metal Option Funcout [PWM1O/T1O] Funcout_sel VDD VSS Data Bus Data Bus Data Bus Read To A/D Converter Analog Input Mode [ANSEL11 ~ 0] Analog Ch. Selection [ADCM.5 ~ ADCM.2] Data Register Direction Register V DD Metal Option [AN11 ~ AN0] Data Bus VDD Read Vdisp Metal option

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 19

• R00 / INT0, R01 / INT1, R02 / EC0
• R03 / BUZO
• R04 ~ R07, R10 ~ R17, R20 ~ R27, R30 ~ R35 VDD Data Bus Data Bus Data Bus Read Data Register Direction Register Funcin_sel Funcin [INT0, INT1, EC0] Vdisp Pull-down Resistor [Metal Option] VDD Data Bus Data Bus Data Bus Data Register Direction Register Vdisp Pull-down Resistor Read Funcout [BUZO] Funcout_sel [Metal Option] VDD Data Bus Data Bus Data Bus Data Register Direction Register Vdisp Pull-down Resistor Read [Metal Option]

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 20 preliminary Nov. 1999 Ver 0.0 10. ELECTRICAL CHARACTERISTICS

• Absolute Maximum Ratings Voltage on any pin

10.1 A/D Converter Characteristics

(TA =25°C, VDD =5V, VSS=0V, AV DD =5.12V, AVSS=0V @ fXI =4MHz) Note: Stresses above those listed under "Absolute Max- imum Ratings" may cause permanent damage to the de- vice. This is a stress rating only and functional operation of the device at these of any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition Specification Unit Min Max Supply Voltage VDD fXI = 4.5 MHz 4.0 5.5 V Operating Frequency fXI VDD = VDD 0.4 4.5 MHz Operating Temperature TOPR -40 125 °C Parameter Symbol Condition Specifications Unit Min. Typ. Max. Analog Power Supply Input Voltage RangeAV DD AV SS - AV DD V Analog Input Voltage Range VAN AV SS -0.3 AV DD +0.3 V Current Following Between AVDD and AV SS IAVDD - − 200 uA Overall Accuracy CA IN - ±1.0 ±1.5 LSB Non-Linearity Error N NLE - ±1.0 ±1.5 LSB Differential Non-Linearity Error N DNLE - ±1.0 ±1.5 LSB Zero Offset Error N ZOE - ±0.5 ±1.5 LSB Full Scale Error N FSE - ±0.25 ±0.5 LSB Gain Error N NLE - ±1.0 ±1.5 LSB Conversion Time TCONV fXI=4MHz -- 2 0 u s

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 21 DC Characteristics for Standard Pins( 5V ) ( VDD = 5.0V ± 10%, VSS = 0V, TA = -40 ~ 125°C, fXI = 4 MHz, Vdisp=VDD -40V to VDD ) Parameter Pin Symbol Test Condition Specification Unit Min Typ Max Input High Voltage XI, SXI V IH1 0.9VDD VDD +0.3 VRESETB,SIN,R55,SCLK, INT0&1,EC0 VIH2 0.8VDD VDD +0.3 R40~R43,R5,R6,R70~R73 VIH3 0.7VDD VDD +0.3 Input Low Voltage XI, SXI V IL1 -0.3 0.1VDD VRESETB,SIN,R55,SCLK, INT0&1,EC0 VIL2 -0.3 0.2VDD R40~R43,R5,R6,R70~R73 VIL3 -0.3 0.3VDD Output High Voltage R40~R43,R5,R6,R70~R73 BUZO,T0O,PWM1O/T1O, SCLK,SOUT V OH IOH = -0.5mA V DD -0.5 V Output Low Voltage R40~R43,R5,R6,R70~R73 BUZO,T0O,PWM1O/T1O, SCLK,SOUT V OL1 VOL2 IOL = 1.6mA IOL = 10mA 0.4 2 V Input High Leakage Current R40~R43,R5,R6,R70~R73 IIH1 1 uA XI IIH2 1 Input Low Leakage Current R40~R43,R5,R6,R70~R73 IIL1 -1 uA XI IIL2 -1 Input Pull-up Current(*Option)R40~R43,R5,R6,R70~R73 IPU 50 100 180 uA Power Fail Detect Voltage VDD VPFD 2.7 V Current dissipation in active mode VDD IDD fXI=4.2MHz 5 mA Current dissipation in standby mode VDD ISTBY fXI=4.2MHz 2 mA Current dissipation in subactive modeVDD ISUB fXI=Off fSXI=32.7KHz 100 uA Current dissipation in watch mode VDD IWTC fXI=Off fSXI=32.7KHz 20 uA Current dissipation in stop mode VDD ISTOP fXI=Off fSXI=32.7KHz 10 uA Hysteresis RESETB,SIN,R55,SCLK, INT0,INT1,EC0 VT+~VT- 0.4 V Internal RC WDT Frequency XO TRCWDT 10 25 MHz RC Oscillation Frequency XO fRCOSC R= 60KΩ 1.5 2 2.5 MHz

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 22 preliminary Nov. 1999 Ver 0.0 DC Characteristics for High-Voltage Pins ( VDD = 5.0V ± 10%, VSS = 0V, TA = -40 ~ 125°C, fXI = 4 MHz, Vdisp=VDD -40V to VDD ) Parameter Pin Symbol Test Condition Specification Unit Min Typ Max Input High Voltage R0,R1,R2,R30~R35,RA VIH 0.7VDD VDD +0.3 V Input Low Voltage R0,R1,R2,R30~R35,RA VIL VDD -40 0.3V DD V Output High Voltage R0,R1,R2,R30~R35 VOH IOH = -15mA IOH = -10mA IOH = - 4mA VDD -3.0 VDD -2.0 VDD -1.0 V Output Low Voltage R0,R1,R2,R30~R35 VOL Vdisp=VDD -40 150KΩ atVDD -40 VDD -37 VDD -37 V Input High Leakage Current R0,R1,R2,R30~R35,RA IIH VIN=VDD -40V to VDD 20 uA Input Pull-down Current(*Option)R0,R1,R2,R30~R35 IPD Vdisp=VDD -35V VIN=VDD 200 600 1000 uA

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 23

10.2 AC Characteristics

(TA =-40~ 125°C, VDD =5V ±10% , V SS=0V) Figure 10-1 Timing Chart Parameter Symbol Pins Specifications Unit Min. Typ. Max. Operating Frequency fCP XI 1 - 8 MHz External Clock Pulse Width tCPW XI 80 - - nS External Clock Transition TimetRCP, tFCP XI - - 20 nS Oscillation Stabilizing Time tST XI, XO - - 20 mS External Input Pulse Width tEPW INT0, INT1, EC0 2 - - tSYS External Input Pulse Transiton Time tREP,tFEP INT0, INT1, EC0 - - 20 nS RESET Input Width tRST RESETB 8 - - tSYS tRCP tFCP XI INT0, INT1 0.5V VDD -0.5V 0.2VDD RESETB tREP tFEP 0.2VDD 0.8VDD EC0 tRST tEPWtEPW 1/fCP tCPW tCPW tSYS

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 24 preliminary Nov. 1999 Ver 0.0

10.3 Typical Characteristics

This graphs and tables provided in this section are for de- sign guidance only and are not tested or guranteed. In some graphs or tables the data presented are out- side specified operating range (e.g. outside specified V DD range). This is for imformation only and divices are guranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Ta= 25°C Ta=25°C IDD −VDD (mA) IDD 23 45 6 VDD (V) Normal Operation (MHz) fXI 23 45 6 VDD (V) Operating Area fXI = 8MHz 4MHz IWKUP −VDD 2.0 1.5 1.0 0.5 (mA) IDD 23 45 6 VDD (V) Wake-up Timer Mode IRCWDT −VDD (µA) IDD 23 45 6 VDD (V) RC-WDT in Stop Mode Ta=25°C fXI = 8MHz 4MHz fXI = 8MHz 4MHz Ta=25°C

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 25 IOL −VOL , VDD =5V (mA) IOL VOL (V) IOH −VOH , VDD =5V -20 -15 -10 (mA) IOH 23 45 6 VOH (V)12 34 5 fXI=4MHz VDD −VIH1 (V) VIH1 23 45 6 VDD (V) VDD −VIH2 (V) VIH2 23 45 6 VDD (V) Ta=25°C fXI=4MHz Ta=25°C XI, RESETB Hysteresis input -25°C 85°C 25°C -25°C 85°C 25°C VDD −VIH3 (V) VIH3 23 45 6 VDD (V) fXI=4MHz Ta=25°C Normal input fXI=4MHz VDD −VIL1 (V) VIL1 23 45 6 VDD (V) VDD −VIL2 (V) VIL2 23 45 6 VDD (V) Ta=25°C fXI=4MHz Ta=25°C XI, RESETB Hysteresis input VDD −VIL3 (V) VIL3 23 45 6 VDD (V) fXI=4MHz Ta=25°C Normal input

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 26 preliminary Nov. 1999 Ver 0.0 11. MEMORY ORGANIZATION The GMS81C2020 and GMS81C2120 have separate ad- dress spaces for Program memory and Data Memory. Pro- gram memory can only be read, not written to. It can be up to 20K/12K bytes of Program memory. Data memory can be read and written to up to 448 bytes including the stack area.

11.1 Registers

This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. Figure 11-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Figure 11-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 00 H to FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initial- ization routine. Normally, the initial value of "FFH " is used. Note: The Stack Pointer must be initialized by software be- cause its value is undefined after RESET. Example: To initialize the SP LDX #0FFH TXSP ; SP ← FFH Program Counter : The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset rou- tine address (PC H :0FFH , PCL:0FEH ). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 11-3 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. A ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD X Y SP PCLPCH PSW Two 8-bit Registers can be used as a "YA" 16-bit Register Y A Y A SP01H Stack Address ( 0100H ~ 01FFH ) 15 0 87 Hardware fixed

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 27 Figure 11-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All inter- rupts are disabled when cleared to "0". This flag immedi- ately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector ad- dress [Direct Page flag G] This flag assign direct page(0-page, 1-page) for direct ad- dressing mode. When G-flag is "0", the direct addressing space is in 0-page(0000h ~ 00FFH). When G-flag is "1", the direct addressing space is in 1-page(0100h ~ 01FFH). It is set and clreared by SETG, CLRG instruction. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction ex- ceeds +127(7F H ) or -128(80H ). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. When the BIT in- struction is executed, bit 7 of memory is copied to this flag. N NEGATIVE FLAG V G B H I Z C MSB LSB [RESET VALUE : 00HPSW OVERFLOW FLAG DIRECT PAGE FLAG CARRY FLAG RECEIVES ZERO FLAG INTERRUPT ENABLE FLAG CARRY OUT HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS BREAK FLAG

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 28 preliminary Nov. 1999 Ver 0.0

11.2 Program Memory

A 16-bit program counter is capable of addressing up to 64K bytes, but these devices have 20K/12K bytes program memory space only physically implemented. Accessing a location above FFFF H will cause a wrap-around to 0000H . Figure 11-4 , shows a map of Program Memory. After re- set, the CPU begins execution from reset vector which is stored in address FFFE H and FFFFH as shown in Figure 11-5 . As shown in Figure 11-4 , each area is assigned a fixed lo- cation in Program Memory. Program Memory area con- tains the user program. Figure 11-4 Program Memory Map Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL in- stead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0 H for TCALL15, 0FFC2 H for TCALL14, etc., as shown in Figure 11-6 . Example: Usage of TCALL The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to loca- tion 0FFFA H . The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFA H and 0FFFBH for External Interrupt 0, etc. As for the area from 0FF00H to 0FFFFH , if any area of them is not going to be used, its service location is avail- able as general purpose Program Memory. Figure 11-5 Interrupt Vector Area PROGRAM MEMORY TCALL AREA INTERRUPT VECTOR AREA B000H FEFFH FF00H FFC0H FFDFH FFE0H FFFFH D000H GMS81C2012 GMS81C2020 PCALL AREA LDA #5 TCALL 0FH ;1BYTE INSTRUCTION :; INSTEAD OF 3 BYTES :; NORMAL CALL ;TABLE CALL ROUTINE FUNC_A: LDA LRG0 RET FUNC_B: LDA LRG1 RET ;TABLE CALL ADD. AREA ORG 0FFC0H ; TCALL ADDRESS AREA DW FUNC_A DW FUNC_B 0FFE0 H Address Vector Area Memory EA EC EE FA FC FE Serial Peripheral Interface Interrupt Vector Area Basic Interval Interrupt Vector Area A/D Converter Interrupt Vector Area Timer/Counter 1 Interrupt Vector Area Timer/Counter 0 Interrupt Vector Area External Interrupt 0 Vector Area RESET Vector Area External Interrupt 1 Vector Area Watchdog Timer Interrupt Vector Area "-" means reserved area. NOTE:

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 29 Figure 11-6 PCALL and TCALL Memory Area PCALL → → → → rel 4F35 PCALL 35H TCALL → → → → n 4A TCALL 4 0FFC0 H Address Program Memory 0FF00 H Address PCALL Area Memory 0FFFF H PCALL Area (256 Bytes) * means that the BRK software interrupt is using same address with TCALL0. NOTE: TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * CA CB CC CD CE CF DA DB DC DD DE DF ~~ ~ NEXT 0FF35H 0FF00H 0FFFFH 11111111 11010110 01001010 PC: FH FH D H 6H ~~ ~ 250FFD6H 0FF00H 0FFFFH NEXT 0FFD7H þ ÀÃ 0F125H Reverse

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 30 preliminary Nov. 1999 Ver 0.0 Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW NOT_USED; (0FFE0) DW NOT_USED; (0FFE2) DW SPI_INT; (0FFE4) Serial Peripheral Interface DW BIT_INT; (0FFE6) Basic Interval Timer DW WDT_INT; (0FFE8) Watchdog Timer DW AD_INT; (0FFEA) A/D Converter DW NOT_USED; (0FFEC) DW NOT_USED; (0FFEE) DW NOT_USED; (0FFF0) DW NOT_USED; (0FFF2) DW TMR1_INT; (0FFF4) Timer-1 DW TMR0_INT; (0FFF6) Timer-0 DW INT1; (0FFF8) Int.1 DW INT0; (0FFFA) Int.0 DW NOT_USED; (0FFFC) DW RESET; (0FFFE) Reset ORG 0F000H ; MAIN PROGRAM * RESET: DI ;Disable All Interrupts LDX #0 RAM_CLR:LDA #0;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR LDX #01FFH;Stack Pointer Initialize TXSP CALL INITIAL; LDM R0, #0;Normal Port 0 LDM R0IO,#1000_0010B;Normal Port Direction LDM R1, #0;Normal Port 1 LDM R1IO,#1000_0010B;Normal Port Direction LDM PFDR,#0;Enable Power Fail Detector

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 31

11.3 Data Memory (GMS81C2020)

Figure 11-7 shows the internal Data Memory space avail- able. Data Memory is divided into two groups, a user RAM(including Stack) and control registers. Figure 11-7 Data Memory Map User Memory The GMS81C2020 has 448 × 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converter, basic interval timer, serial peripheral in- terface, watchdog timer, buzzer driver and I/O ports. The control registers are in address range of 0C0 H to 0FFH . Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit ma- nipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. Example; To write at CKCTLR LDM CKCTLR,#09H ;Divide ratio ÷16 Note: Several names are given at same address. Refer to USER MEMORY CONTROL REGISTERS 0000H 00BFH 00C0H 00FFH PAGE0 USER MEMORY 0100H 01FFH ( including STACK ) PAGE1 Address Symbol R/W RESET Value Addressing mode 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CBH 0CCH 0CDH 0CEH 0CFH R0IO R1IO R2IO R3IO R4IO R5IO R6IO R7IO R/W W R/W W R/W W R/W W R/W W R/W W R/W W R/W W Undefined 0000_0000 Undefined 00000000 Undefined 0000_0000 Undefined --00_0000 Undefined ----_0000 Undefined 0000_0000 Undefined 0000_0000 Undefined ----_0000 byte, bit byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte 0D0H 0D1H 0D1H 0D1H 0D2H 0D3H 0D3H 0D4H 0D4H 0D4H 0D5H 0DEH TM0 TDR0 CDR0 TM1 TDR1 T1PPR CDR1 T1PDR PWM1HR BUR R/W R W R R/W W W R R R/W W W --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte byte 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH 0ECH 0EDH 0EDH 0EFH SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR R/W R/W R/W R/W R/W R/W R/W R/W R R W R W R/W 0000_0001 Undefined 0000_---- 0000_---- 0000_---- 0000_---- ----_0000 -000_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH R0FUNC R4FUNC R5FUNC R6FUNC R7FUNC R5NODR SCMR RA W W W W W W R/W R ----_0000 ----_--00 0000_0000 0000_0000 ----_0000 0000_0000 ---0_0000 Undefined byte byte byte byte byte byte byte Table 11-1 Control Registers 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 32 preliminary Nov. 1999 Ver 0.0 below table. Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the pro- gram counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Addr. When read When write Timer Mode Capture Mode PWM Mode Timer Mode PWM Mode D1H T0 CDR0 - TDR0 - D3H - TDR1 T1PPR D4H T1 CDR1 T1PDR - T1PDR ECH BITR CKCTLR Table 11-2 Various Register Name in Same Address

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 33 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C0H R0 R0 Port Data Register (Bit[7:0]) C1H R0IO R0 Port Direction Register (Bit[7:0]) C2H R1 R1 Port Data Register (Bit[7:0]) C3H R1IO R1 Port Direction Register (Bit[7:0]) C4H R2 R2 Port Data Register (Bit[7:0]) C5H R2IO R2 Port Direction Register (Bit[7:0]) C6H R3 R3 Port Data Register (Bit[5:0]) C7H R3IO R3 Port Direction Register (Bit[5:0]) C8H R4 R4 Port Data Register (Bit[3:0]) C9H R4IO R4 Port Direction Register (Bit[3:0]) CAH R5 R5 Port Data Register (Bit[7:0]) CBH R5IO R5 Port Direction Register (Bit[7:0]) CCH R6 R6 Port Data Register (Bit[7:0]) CDH R6IO R6 Port Direction Register (Bit[7:0]) CEH R7 R7 Port Data Register (Bit[5:0]) CFH R7IO R7 Port Direction Register (Bit[5:0]) D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST D1H T0/TDR0/ CDR0 Timer0 Register / Timer0 Data Register / Capture0 Data Register D2H TM1 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST D3H TDR1/ T1PPR Timer1 Data Register / PWM1 Period Register D4H T1/CDR1/ T1PDR Timer1 Register / Capture1 Data Register / PWM1 Duty Register D5H PWM1HR PWM1 High Register(Bit[3:0]) DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 E0H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR SPI DATA REGISTER E2H IENH INT0E INT1E T0E T1E E3H IENL ADE WDTE BITE SPIE - - - - E4H IRQH INT0IF INT1IF T0IF T1IF E5H IRQL ADIF WDTIF BITIF SPIIF - - - - E6H IEDS IED1H IED1L IED0H IED0L EAH ADCM - ADEN ADS3 ADS2 ADS1 ADS0 ADST ADSF EBH ADCR ADC Result Data Register ECH BITR1 Basic Interval Timer Data Register ECH CKCTLR 1 - WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 Table 11-3 Control Registers of GMS81C2020 These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ".

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 34 preliminary Nov. 1999 Ver 0.0 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EDH WDTR WDTCL 7-bit Watchdog Counter Register EFH PFDR 2 ----- P F D I S P F D M P F D S F4H R0FUNC - - - - BUZO EC0 INT1 INT0 F5H R4FUNC - - - - - - - T0O F6H R5FUNC - PWM1O/ T1O SOUT SIN SCLK - - - F7H R6FUNC AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 F8H R7FUNC - - - - AN11 AN10 AN9 AN8 F9H R5NODR NODR7 NODR6 NODR5 NODR4 NODR3 NODR2 NODR1 NODR0 FAH SCMR - - - CS1 CS0 SUBOFF CLKSEL MAINOFF FBH RA - - - - - - - RA0 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator. Table 11-3 Control Registers of GMS81C2020 These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ".

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 35

11.4 Data Memory (GMS81C2120)

Figure 11-8 shows the internal Data Memory space avail- able. Data Memory is divided into two groups, a user RAM(including Stack) and control registers. Figure 11-8 Data Memory Map User Memory The GMS81C2120 has 448 × 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converter, basic interval timer, serial peripheral in- terface, watchdog timer, buzzer driver and I/O ports. The control registers are in address range of 0C0 H to 0FFH . Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit ma- nipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. Example; To write at CKCTLR LDM CKCTLR,#09H ;Divide ratio ÷16 Note: Several names are given at same address. Refer to USER MEMORY CONTROL REGISTERS 0000H 00BFH 00C0H 00FFH PAGE0 USER MEMORY 0100H 01FFH ( including STACK ) PAGE1 Address Symbol R/W RESET Value Addressing mode 0C0H 0C1H 0C4H 0C5H 0C6H 0C7H 0CAH 0CBH 0CCH 0CDH R0IO R2IO R3IO R5IO R6IO R/W W R/W W R/W W R/W W R/W W Undefined 0000_0000 Undefined 0000_0000 Undefined ---0_0000 Undefined 0000_0--- Undefined 0000_0000 byte, bit byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte 0D0H 0D1H 0D1H 0D1H 0D2H 0D3H 0D3H 0D4H 0D4H 0D4H 0D5H 0DEH TM0 TDR0 CDR0 TM1 TDR1 T1PPR CDR1 T1PDR PWM1HR BUR R/W R W R R/W W W R R R/W W W --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte byte 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH 0ECH 0EDH 0EDH 0EFH SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR R/W R/W R/W R/W R/W R/W R/W R/W R R W R W R/W 0000_0001 Undefined 0000_---- 0000_---- 0000_---- 0000_---- ----_0000 -000_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit 0F4H 0F6H 0F7H 0F9H 0FAH 0FBH R0FUNC R5FUNC R6FUNC R5NODR SCMR RA W W W W R/W R ----_0000 0000_0--- 0000_0000 0000_0--- ---0_0000 Undefined byte byte byte byte byte Table 11-4 Control Registers 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 36 preliminary Nov. 1999 Ver 0.0 below table. Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the pro- gram counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Addr. When read When write Timer Mode Capture Mode PWM Mode Timer Mode PWM Mode D1H T0 CDR0 - TDR0 - D3H - TDR1 T1PPR D4H T1 CDR1 T1PDR - T1PDR ECH BITR CKCTLR Table 11-5 Various Register Name in Same Address

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 37 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C0H R0 R0 Port Data Register (Bit[7:0]) C1H R0IO R0 Port Direction Register (Bit[7:0]) C4H R2 R2 Port Data Register (Bit[7:0]) C5H R2IO R2 Port Direction Register (Bit[7:0]) C6H R3 R3 Port Data Register (Bit[4:0]) C7H R3IO R3 Port Direction Register (Bit[4:0]) CAH R5 R5 Port Data Register (Bit[7:3]) CBH R5IO R5 Port Direction Register (Bit[7:3]) CCH R6 R6 Port Data Register (Bit[7:0]) CDH R6IO R6 Port Direction Register (Bit[7:0]) D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST D1H T0/TDR0/ CDR0 Timer0 Register / Timer0 Data Register / Capture0 Data Register D2H TM1 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST D3H TDR1/ T1PPR Timer1 Data Register / PWM1 Period Register D4H T1/CDR1/ T1PDR Timer1 Register / Capture1 Data Register / PWM1 Duty Register D5H PWM1HR PWM1 High Register(Bit[3:0]) DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 E0H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR SPI DATA REGISTER E2H IENH INT0E INT1E T0E T1E E3H IENL ADE WDTE BITE SPIE - - - - E4H IRQH INT0IF INT1IF T0IF T1IF E5H IRQL ADIF WDTIF BITIF SPIIF - - - - E6H IEDS IED1H IED1L IED0H IED0L EAH ADCM - ADEN ADS3 ADS2 ADS1 ADS0 ADST ADSF EBH ADCR ADC Result Data Register ECH BITR1 Basic Interval Timer Data Register ECH CKCTLR 1 - WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 EDH WDTR WDTCL 7-bit Watchdog Counter Register EFH PFDR 2 ----- P F D I S P F D M P F D S F4H R0FUNC - - - - BUZO EC0 INT1 INT0 F5H R4FUNC - - - - - - - T0O F6H R5FUNC - PWM1O/ T1O SOUT SIN SCLK - - - Table 11-6 Control Registers of GMS81C2120 These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ".

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 38 preliminary Nov. 1999 Ver 0.0 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F7H R6FUNC AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 F8H R7FUNC - - - - AN11 AN10 AN9 AN8 F9H R5NODR NODR7 NODR6 NODR5 NODR4 NODR3 NODR2 NODR1 NODR0 FAH SCMR - - - CS1 CS0 SUBOFF CLKSEL MAINOFF FBH RA - - - - - - - RA0 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator. Table 11-6 Control Registers of GMS81C2120 These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ".

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 39

11.5 Addressing Mode

The GMS87C1404 and GMS87C1408 uses six addressing modes;

• Register addressing
• Immediate addressing
• Direct page addressing
• Absolute addressing
• Indexed addressing
• Register-indirect addressing (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing → → → → #imm In this mode, second byte (operand) is accessed as a data immediately. Example:

0435 ADC #35H

E45535 LDM 35H,#55H (3) Direct Page Addressing → → → → dp In this mode, a address is specified within direct page. Example; C535 LDA 35H ;A ← RAM[35H] (4) Absolute Addressing → → → → !abs Absolute addressing sets corresponding memory data to Data , i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC !0F035H ;A ← ROM[0F035H] A+35H+C → A04 MEMORY E40F100H data ← 55H ~~ ~ data0035H þ 350F102H 550F101H À data 0035H 0F551H data → A À þ~~ ~ ~C50F550H 070F100H ~~ ~ data0F035H þ F00F102H 350F101H À A+data+C → A address: 0F035

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 40 preliminary Nov. 1999 Ver 0.0 The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H . 983500 INC !0035H ;A ← RAM[035H] (5) Indexed Addressing X indexed direct page (no offset) → → → → {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15 H D4 LDA {X} ;ACC← RAM[X]. X indexed direct page, auto increment→ → → → {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; X=35 H DB LDA {X}+ X indexed direct page (8 bit offset) → → → → dp+X This address value is the second byte (Operand) of com- mand plus the data of -register. And it assigns the mem- ory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; X=015H C645 LDA 45H+X 980F100H ~~ ~ data0035H þ 000F102H 350F101H À data+1 → data à address: 0035 data 15H 0E550H data → A À þ ~~ ~ data DB 35H data → A À þ ~~ ~ 36H → X data 5AH 0E551H data → AÀ þ ~~ ~ ~C60E550 H 45H+15H=5AH Ã

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 41 Y indexed direct page (8 bit offset) → → → → dp+Y This address value is the second byte (Operand) of com- mand plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute → → → → !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify mem- ory in whole area. Example; Y=55 H D500FA LDA !0FA00H+Y (6) Indirect Addressing Direct page indirect → → → → [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; 3F35 JMP [35H] X indexed indirect → → → → [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; X=10 H

1625 ADC [25H+X]

data → A þ ~~ ~ data0FA55 H 0FA00H+55H=0FA55H Ã FA0F102H 000F101H À 0A35H jump to address 0E30AH þ ~~ ~ 0FA00 H E336H À 0E30A H NEXT ~~ ~ 0535H 0E005 H~~ ~ 0FA00 H E036H 0E005 H data ~~ ~ Ã A + data + C → A 25 + X(10) = 35Hþ À

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 42 preliminary Nov. 1999 Ver 0.0 Y indexed indirect → → → → [dp]+Y Processes momory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Di- rect pageplus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Y=10 H

1725 ADC [25H]+Y

Absolute indirect → → → → [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example; 1F25E0 JMP [!0C025H] 0525H 0E005 H + Y(10) = 0E015H þ ~~ ~ 0FA00 H E026H À 0E015H data ~~ ~ Ã A + data + C → A 250E025 H jump to~~ ~ 0FA00 H E70E026 H À 0E725H NEXT ~~ ~ ~1F PROGRAM MEMORY þ address 0E30AH

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 43 12. I/O PORTS The GMS81C2020 has eight ports, R0, R1, R2, R3, R4, R5, R6 and R7. The GMS81C2120 has five ports, R0, R2, R3, R5 and R6. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, when a initial reset state, all ports are used as a general purpose input port. All pins have data direction registers which can set these ports as output or input. A "1" in the port direction register defines the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify as an input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55 H " to address C1H (R0 direction register) during initial setting as shown in Figure 12-1 . Reading data register reads the status of the pins whereas writing to it will write to the port latch.. Figure 12-1 Example of port I/O assignment

12.1 RA(Vdisp) register

RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when se- lected by the mask option..

12.2 R0 and R0IO registers

R0 is an 8-bit high-voltage CMOS bidirectional I/O port (address C0H ). Each port can be set individually as input and output through the R0IO register (address C1H ). Each port can directly drive a vacuum fluorescent display. R03 port is multiplexed with Buzzer Output Port(BUZO), R02 port is multiplexed with Event Counter Input Port (EC0), and R01~R00 are multiplexed with External Interrupt In- put Port(INT1, INT0) Figure 12-2 Registers of Port R0 The control register R0FUNC (address F4H ) controls to se- lect alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate func- tion such as Buzzer Output, External Event Counter Input and External Interrupt Input, write "1" to the correspond- ing bit of R0FUNC. Regardless of the direction register R0IO, R0FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (BUZO, EC0, INT1, INT0) Port pin Alternate function RA V disp (High-voltage input power supply) I : INPUT PORT WRITE "55H" TO PORT RA DIRECTION REGISTER 0 1 0 1 0 1 0 1 I O I O I O I O R0 DATA R1 DATA R0 DIRECTION R1 DIRECTION C0H C1H C2H C3H

76543210 B I T

76543210 P O R T

O : OUTPUT PORT - - - - - - - RA0 INPUT DATA RA Data Register RA ADDRESS : FBH RESET VALUE : Undefined PORT R0FUNC [3:0] Description R03 / BUZO

0 R00 (Normal I/O Port)

1 BUZO (Buzzer Output Port)

0 R01 (Normal I/O Port)

1 EC0 (Event Counter Input Port)

1 INT1 (External interrupt 1 Input

Port) R07 R06 R05 R04 R03 R02 R01 R00 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT R0 Data Register ADDRESS : C0H RESET VALUE : Undefined R0 Direction Register R0IO ADDRESS : C1H RESET VALUE : 00000000 INT0 R0 Function Selection Register R0FUNC ADDRESS : F4H RESET VALUE : ----0000 - INT1EC0BUZO--- 0 : R00 1 : INT0 0 : R01 1 : INT1 0 : R02 1 : EC0 0 : R03 1 : BUZO

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 44 preliminary Nov. 1999 Ver 0.0

12.3 R1 and R1IO registers

R1 is an 8-bit high-voltage CMOS bidirectional I/O port (address C2H ). Each port can be set individually as input and output through the R1IO register (address C3H ). Each port can directly drive a vacuum fluorescent display.. Figure 12-3 Registers of Port R1

12.4 R2 and R2IO registers

R2 is an 8-bit high-voltage CMOS bidirectional I/O port (address C4H ). Each port can be set individually as input and output through the R2IO register (address C5H ). Each port can directly drive a vacuum fluorescent display.. Figure 12-4 Registers of Port R2

12.5 R3 and R3IO registers

R1 is an 6-bit high-voltage CMOS bidirectional I/O port (address C6H ). Each port can be set individually as input and output through the R3IO register (address C7H ). Each port can directly drive a vacuum fluorescent display.. Figure 12-5 Registers of Port R3

12.6 R4 and R4IO registers

R4 is an 4-bit bidirectional I/O port (address C8H ). Each port can be set individually as input and output through the R4IO register (address C9H ). R40 port is multiplexed with Timer 0 Output Port(T0O), r Figure 12-6 Registers of Port R4 The control register R4FUNC (address F5H ) controls to se- lect alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate func- tion such as Timer 0 Output, write "1" to the corresponding bit of R4FUNC. Regardless of the direction register R4IO, R4FUNC is selected to use as alternate functions, port pin R00 / INT0

1 INT0 (External interrupt 0 Input

Port) R17 R16 R15 R14 R13 R12 R11 R10 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT R1 Data Register ADDRESS : C2H RESET VALUE : Undefined R1 Direction Register R1IO ADDRESS : C3H RESET VALUE : 00000000 R27 R26 R25 R24 R23 R22 R21 R20 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT R2 Data Register ADDRESS : C4H RESET VALUE : Undefined R2 Direction Register R2IO ADDRESS : C5H RESET VALUE : 00000000 - - R35 R34 R33 R32 R31 R30 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT R3 Data Register ADDRESS : C6H RESET VALUE : Undefined R3 Direction Register R3IO ADDRESS : C7H RESET VALUE : --000000 - - - - R43 R42 R41 R40 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT R4 Data Register ADDRESS : C8H RESET VALUE : Undefined R4 Direction Register R4IO ADDRESS : C9H RESET VALUE : ----0000 T0O R4 Function Selection Register R4FUNC ADDRESS : F5H - --- 0 : R40 1 : T0O ---

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 45 can be used as a corresponding alternate features (T0O) PORT R4FUNC [0] Description R40/ T0O

0 R40 (Normal I/O Port)

1 T0O (Timer 0 Compare Output

Port)

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 46 preliminary Nov. 1999 Ver 0.0

12.7 R5 and R5IO registers

R5 is an 8-bit bidirectional I/O port (address CAH ). Each pin can be set individually as input and output through the R5IO register (address CBH ).In addition, Port R5 is multi- plexed with Serial Peripheral Interface (SPI). The control register R5FUNC (address F6H ) controls to select Serial Peripheral Interface function.After reset, the R5IO register value is "0", port may be used as general I/O ports. To se- lect Serial Peripheral Interface function, write "1" to the corresponding bit of R5FUNC. Figure 12-7 Registers of Port R5 Table 12-1 Registers of Port R5FUNC

12.8 R6 and R6IO registers

R6 is an 8-bit bidirectional I/O port (address CCH ). Each port can be set individually as input and output through the R6IO register (address CDH ). R67~R60 ports are multiplexed with Analog Input Port ( AN7~AN0 ).. Figure 12-8 Registers of Port R6 PORT R5FUNC [6:3] Description R56/ PWM1O/ T1O

0 R56 (Normal I/O Port)

1 PWM1 Data Output / Timer

1 Data Output

0 R55 (Normal I/O Port)

1 SPI Serial Data Output

0 R54 (Normal I/O Port)

1 SPI Serial Data Input

0 R53 (Normal I/O Port)

0 [R5IO.3] SCLKO SPI Synchronous Clock Output 1 [R5IO.3] SCLKI SPI Synchronous Clock Input R53 R52 R51 R50 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT R5 Data Register ADDRESS : CAH RESET VALUE : Undefined R5 Direction Register R5IO ADDRESS : CBH RESET VALUE : 00000000 R5 Function Selection Register R5FUNC ADDRESS : F6H RESET VALUE : -0000--- - -- R57 R56 R55 R54 SCLKSINSOUTPWM1O - 0 : R56 1 : PWM1O/T1O 0 : R55 1 : SOUT 0 : R54 1 : SIN 0 : R53 1 : SCLK 0 [R5IO.3] : SCLKO 1 [R5IO.3] : SCLKI R67 R66 R65 R64 R63 R62 R61 R60 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT R6 Data Register ADDRESS : CCH RESET VALUE : Undefined R6 Direction Register R6IO ADDRESS : CDH RESET VALUE : 00000000 ANSEL0 R6 Function Selection Register R6FUNC ADDRESS : F7H RESET VALUE : 00000000 ANSEL7 ANSEL1ANSEL2ANSEL3ANSEL4ANSEL5ANSEL6 0 : R60 1 : AN0 0 : R61 1 : AN1 0 : R62 1 : AN2 0 : R63 1 : AN3 0 : R64 1 : AN4 0 : R65 1 : AN5 0 : R66 1 : AN6 0 : R67 1 : AN7

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 47 The control register R6FUNC (address F7H ) controls to se- lect alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate func- tion such as Analog Input, write "1" to the corresponding bit of R6FUNC. Regardless of the direction register R6IO, R6FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (AN7~AN0)

12.9 R7 and R7IO registers

R7 is an 4-bit bidirectional I/O port (address CEH ). Each port can be set individually as input and output through the R7IO register (address CFH ). R73~R70 ports are multiplexed with Analog Input Port AN11~AN8 ). . Figure 12-9 Registers of Port R6 The control register R7FUNC (address F8H ) controls to se- lect alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate func- tion such as Analog Input, write "1" to the corresponding bit of R7FUNC. Regardless of the direction register R7IO, R7FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features. PORT R6FUNC [7:0] Description R67/AN7

0 R67 ( Normal I/O Port )

1 AN7 ( ADS3~0=0111 )

0 R66 ( Normal I/O Port )

1 AN6 ( ADS3~0=0110 )

0 R65 ( Normal I/O Port )

1 AN5 ( ADS3~0=0101 )

0 R64 ( Normal I/O Port )

1 AN4 ( ADS3~0=0100 )

0 R63 ( Normal I/O Port )

1 AN3 ( ADS3~0=0011 )

0 R62 ( Normal I/O Port )

1 AN2 ( ADS3~0=0010 )

0 R61 ( Normal I/O Port )

1 AN1 ( ADS3~0=0001 )

0 R60 ( Normal I/O Port )

1 AN0 ( ADS3~0=0000 )

[7:0] Description R73/AN11

0 R73 ( Normal I/O Port )

1 AN11 ( ADS3~0=1011 )

0 R72 ( Normal I/O Port )

1 AN10 ( ADS3~0=1010 )

0 R71 ( Normal I/O Port )

1 AN9 ( ADS3~0=1001 )

0 R70 ( Normal I/O Port )

1 AN8 ( ADS3~0=1000 )

• - - - R73 R72 R71 R70 INPUT / OUTPUT DATA 0 : INPUT PORT 1 : OUTPUT PORT DIRECTION SELECT R7 Data Register ADDRESS : CEH RESET VALUE : Undefined R7 Direction Register R7IO ADDRESS : CFH RESET VALUE : ----0000 ANSEL8 R7 Function Selection Register R7FUNC ADDRESS : F8H RESET VALUE : ----0000 ANSEL9ANSEL10ANSEL11 0 : R70 1 : AN8 0 : R71 1 : AN9 0 : R72 1 : AN10 0 : R73 1 : AN11 - - - -

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 48 preliminary Nov. 1999 Ver 0.0 13. CLOCK GENERATOR The clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and pe- ripheral hardware. The main system clock oscillator oscil- lates with a crystal resonator or a ceramic resonator connected to the XI and XO pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XI pin and open the XO pin. Figure 13-1 Block Diagram of Clock Pulse Generator

13.1 Oscillation Circuit

XI and XO are the input and output, respectively, a invert- ing amplifier which can be set for use as an on-chip oscil- lator, as shown in Figure 13-2 . Figure 13-2 Oscillator Connections SXI and SXO are the input and output, respectively, a in- verting amplifier which can be set for use as an on-chip os- Internal system clock PRESCALER CLOCK PULSE Peripheral clock GENERATOR ÷2048 STOP WAKEUP fXIOSCILLATION CIRCUIT OSCILLATION CIRCUITCIRCUIT SUB fSXI CLKSEL MUXfXI÷ 4 fXI÷ 8 fXI÷32 CS[1:0] ÷4096 System Clock Mode Register SCMR ADDRESS : FAH RESET VALUE : ---00000- - - CS1 CS0 SUBOFF CLKSEL MAINOFF CS[1:0] Clock selection enable bits 00 : fXI ÷ 210 : fXI ÷16 01 : fXI ÷ 811 : fXI ÷ 64 CLKSEL Clock selection bit 0 : Main clock selection 1 : Sub clock selection SUBOFF Sub clock control bit 0: On sub clock 1: Off sub clock MAINOFF Main clock control bit 0: On main clock 1: Off main clock /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 XO XI Vss Recommended: C1, C2 = 30pF±10pF for Crystals

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 51 15. TIMER / COUNTER The GMS81C2020 and GMS81C2120 has two Timer/ Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 can be used either the two 8-bit Tim- er/Counter or one 16-bit Timer/Counter by combining them. In the "timer" function, the register is increased every in- ternal clock input. Thus, one can think of it as counting in- ternal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in Timer0. And Timer1 can use the same clock source too. In addition, Timer1 has more fast clock source ( 1/1 to 1/8 ). In the "counter" function, the register is increased in re- sponse to a 0-to-1 (rising & falling edge) transition at its corresponding external input pin, EC0(Timer 0). In addition the "capture" function, the register is increased in response external interrupt same with timer function. When external interrupt edge input, the count register is captured into capture data register CDRx. Timer1 is shared with "PWM" function and "Compare out- put" function It has seven operating modes: "8-bit timer/counter", "16- bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", "16-bit compare output" and "10-bit PWM" which are selected by bit in Timer mode register TMx as shown in Figure 15-1 and Table 12-1 . Figure 15-1 Timer Mode Register ( TMx , x = 0~1 ) Timer 0 Mode Register TM0 ADDRESS : D0H RESET VALUE : --000000- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST Timer 1 Mode Register TM1 ADDRESS : D2H RESET VALUE : 00000000POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST CAP0 Capture mode selection bit . 0 : Disables Capture 1 : Enables Capture T0CN Continue control bit 0 : Stop counting 1 : Start counting continuously T0CK[2:0] Input clock selection 000 : fXI ÷ 2100 : fXI ÷ 128 001 : fXI ÷ 4101 : fXI ÷ 512 010 : fXI ÷ 8110 : fXI ÷ 2048 011 : fXI ÷ 32111 : External Event (EC0) T0ST Start control bit 0 : Stop counting 1 : Counter register is cleared and start again POL PWM Output Polarity 0 :Duty active low 1 : Duty active high T1CK[2:0]] Input clock selection 00 : fXI 10 : fXI ÷ 8 01 : fXI ÷ 211 : using the Timer 0 clock 16BIT 16-bit mode selection 0 : 8-bit mode 1 : 16-bit mode T1CN Continue control bit 0 : Stop counting 1 : Start counting continuously PWM1E PWM enable bit 0 : Disables PWM 1 : Enables PWM T1ST Start control bit 0 : Stop counting 1 : Counter register is cleared and start again CAP1 Capture mode selection bit . 0 : Disables Capture 1 : Enables Capture

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 52 preliminary Nov. 1999 Ver 0.0 15.1 8-bit Timer/Counter Mode The GMS81C2020 and GMS81C2120 has four 8-bit Tim- er/Counters, Timer 0, Timer 1 as shown in Figure 15-2 . The "timer" or "counter" function is selected by mode reg- isters TMx as shown in Figure 15-1 and Table 15-1 . To use as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to "0" and bits 16BIT of TM1 should be cleared to “0”(Table 15-1 ). Figure 15-2 8-bit Timer / Counter Mode 16BIT CAP0 CAP1 PWM1E T0CK[2:0] T1CK[1:0] PWMO TIMER 0 TIMER1 0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event Counter 8-bit Capture 0 1 0 0 XXX XX 1 8-bit Capture 8-bit Compare output 0 X 1 0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM 1 0 0 0 XXX 11 0 16-bit Timer 10 0 0 1 1 1 11 0 16-bit Event Counter 1 1 X 0 XXX 11 0 16-bit Capture 1 0 0 0 XXX 11 1 16-bit Compare output Table 15-1 Operating Modes of Timer 0 and Timer 1 1. X : The value "0" or "1" corresponding your operation. ÷ 1 ÷ 2 ÷ 8 TM0 ADDRESS : D0H RESET VALUE : --000000- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST TM1 ADDRESS : D2H RESET VALUE : 00000000POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST -- 0 XXXXX X 000 XXXX ÷ 2 ÷ 4 ÷ 128 ÷ 512 ÷ 8 ÷ 32fXI EC0 Edge Detector MUX MUX T0 ( 8-bit ) TDR0 ( 8-bit ) T0IF CLEAR COMPARATOR TIMER 0 INTERRUPT T1 ( 8-bit ) TDR1 ( 8-bit ) CLEAR COMPARATOR T0ST 0 : Stop 1 : Clear and Start T1ST 0 : Stop 1 : Clear and Start T0CN T1CN T0CK[2:0] T1CK[1:0]÷ 2048 X : The value "0" or "1" corresponding your operation. T0CK F/F R40/T0O R4FUNC.0 F/F R56/PWM1O/T1O R5FUNC.6 T1IF TIMER 1 INTERRUPT

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 55 timer register T0 (T1) increases and matches TDR0 (TDR1). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 15-8 , the pulse width of captured signal is wider than the timer data value (FFH ) over 2 times. When external interrupt is occured, the captured value (13H ) is more little than wanted value. It can be ob- tained correct value by counting the number of timer over- flow occurence. Timer/Counter still does the above, but with the added fea- ture that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1), to be cap- tured into registers CDRx (CDR0, CDR1), respectively. After captured, Timer x register is cleared and restarts by hardware. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In ad- dition, the transition at INTx pin generate an interrupt. Note: The CDRx, TDRx and Tx are in same address. In the capture mode, reading operation is read the CDRx, not Tx because path is opened to the CDRx, and TDRx is only for writing operation. Figure 15-6 8-bit Capture Mode ÷ 1 ÷ 2 ÷ 8 TM0 ADDRESS : D0H RESET VALUE : --000000- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST TM1 ADDRESS : D2H RESET VALUE : 00000000POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST -- 1 XXXXX X 001 XXXX ÷ 2 ÷ 4 ÷ 128 ÷ 512 ÷ 8 ÷ 32fXI EC0 Edge Detector MUX MUX T0 ( 8-bit ) CDR0 ( 8-bit ) T0IF CLEAR COMPARATOR TIMER 0 INTERRUPT T0ST 0 : Stop 1 : Clear and Start T0CN T1CN T0CK[2:0] T1CK[1:0] TDR0 ( 8-bit ) INT0IF INT 0 INTERRUPT INT0 T1 ( 8-bit ) CDR1 ( 8-bit ) T1IF CLEAR COMPARATOR TIMER 1 INTERRUPT TDR1 ( 8-bit ) INT1IF INT 1 INTERRUPT INT1 T0ST 0 : Stop 1 : Clear and StartIEDS[1:0] IEDS[3:2] CAPTURE CAPTURE ÷ 2048 T0CK

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 57 15.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0. In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to "1" respectively. Figure 15-9 16-bit Capture Mode

15.6 PWM Mode

The GMS81C2020 and GMS81C2120 has a high speed PWM (Pulse Width Modulation) functions which shared with Timer1. In PWM mode, pin R56/PWM1O/T1O outputs up to a 10- bit resolution PWM output. This pin should be configured as a PWM output by setting "1" bit PWM1O in R5FUNC.6 register. The period of the PWM output is determined by the T1PPR (PWM1 Period Register) and PWM1HR[3:2] (bit3,2 of PWM1 High Register) and the duty of the PWM output is determined by the T1PDR (PWM1 Duty Regis- ter) and PWM1HR[1:0] (bit1,0 of PWM1 High Register). The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the PWM1HR[3:2]. And writes duty value to the T1PDR and the PWM1HR[1:0] same way. The T1PDR is configured as a double buffering for glitch- less PWM output. In Figure 15-10 , the duty data is trans- fered from the master to the slave when the period data matched to the counted value. ( i.e. at the beginning of next duty cycle ) PWM Period = [ PWM1HR[3:2]T1PPR ] X Source Clock PWM Duty = [ PWM1HR[1:0]T1PDR ] X Source Clock The relation of frequency and resolution is in inverse pro- portion. Table 15-2 shows the relation of PWM frequency vs. resolution. TM0 ADDRESS : D0H RESET VALUE : --000000- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST TM1 ADDRESS : D2H RESET VALUE : 00000000POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST -- 1 XXXXX X 10 X 11 XX ÷ 2 ÷ 4 ÷ 128 ÷ 512 ÷ 8 ÷ 32fXI EC0 Edge Detector T0 + T1 ( 16-bit ) TDR1 T0IF CLEAR COMPARATOR TIMER 0 INTERRUPT T0ST 0 : Stop 1 : Clear and Start TDR0 INT0IF INT 0 INTERRUPT INT0 IEDS[1:0] CAPTURE CDR1 CDR0 ( 8-bit )( 8-bit )( 8-bit ) ( 8-bit )÷ 2048 X : The value "0" or "1" corresponding your operation. MUX T0CN T0CK[2:0] XX T1CK[1:0] ÷ 1 ÷ 2 ÷ 8 fXI

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 59 Figure 15-11 Example of PWM at 4MHz Figure 15-12 Example of Changing the Period in Absolute Duty Cycle (@4MHz) fXI PWM ~~~ 01 02 03 04 05 7F 80 81 3FF 02 03 ~~ ~ POL=1 PWM POL=0 Duty Cycle [ 80H x 250nS = 32uS ] Period Cycle [ 3FFH x 250nS = 255.75uS, 3.9KHz ] PWM1HR = 0CH T1PPR = FFH T1PDR = 80H T1CK[1:0] = 00 ( fXI ) PWM1HR3 PWM1HR2 PWM1HR1 PWM1HR0 T1PPR (8-bit) T1PDR (8-bit) Period Duty

11 F F H

POL=1 Duty Cycle Period Cycle [ 0EH x 2uS = 28uS, 35.5KHz ] PWM1HR = 00H T1PPR = 0EH T1PDR = 05H 01 02 03 04 05 06 08 09 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 01 02 03 0407 0A 05 [ 05H x 2uS = 10uS ] Duty Cycle [ 05H x 2uS = 10uS ] Period Cycle [ 0AH x 2uS = 20uS, 50KHz ] Duty Cycle [ 05H x 2uS = 10uS ] Write T1PPR to 0AH Period changed clock

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 60 preliminary Nov. 1999 Ver 0.0 16. Serial Peripheral Interface The Serial Peripheral Interface (SPI) module is a serial in- terface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D con- verters, etc. Figure 16-1 SPI Registers and Block Diagram The SPI allows 8-bits of data to be synchronously transmit- ted and received. To accomplish communication, typically three pins are used: - Serial Data In R54/SIN - Serial Data Out R55/SOUT - Serial Clock R53/SCLK The serial data transfer operation mode is decided by set- ting the SM1 and SM0 of SPI Mode Control Register, and the transfer clock rate is decided by setting the SCK1 and SCK0 of SPI Mode Control Register as shown in Figure 16-1 . And the polarity of transfer clock is selected by set- SPI Mode Control Register SIOM ADDRESS : E0H RESET VALUE : 00000000POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF POL Serial Clock Polarity Selection bit. 0 : Data Transmission at falling edge ( Received data latch at rising edge ) 1 : Data Transmission at rising edge ( Received data latch at falling edge ) SCK[1:0] Serial Clock Selection bits 00 : fXI ÷ 4 01 : fXI ÷ 16 10 : TMR0OV ( Overflow of Timer 0 ) 11 : External Clock IOSW Serial Input Pin Selection bit 0 : SIN(R54) Pin Selection 1 : SOUT(R55) Pin Selection SIOST Serial Transmit Start bit 0 : Disable 1 : Start ( After one SCLK, becomes “0” ) SM[1:0] Serial Operation Mode Selection bits 00 : Normal Port ( R55, R54, R53 ) 01 : Transmit Mode ( SOUT,R54, SCLK ) 10 : Receive Mode ( R55, SIN, SCLK ) 11 : Transmit & Receive Mode ( SOUT, SIN, SCLK ) SIOSF Serial Transmit Status bit 0 : During Transmission 1 : Finished SPI Data Register SIOR ADDRESS : E1H RESET VALUE : Undefined ÷ 4 ÷16 fXI SPI Control Circuit SPI INTERRUPT SIOST 0 : Disable 1 : Clear and Start R53/SCLK MUX T0CK[2:0] SCLKI TMR0OV (Timer 0 overflow) POL [SIOM.7] SCLK [R5FUNC.3] SCLKO Octal Counter ( 3-Bit ) SIOSF 0 : Process 1 : Completed SIOR ( 8-Bit ) MSB LSB R54/SIN IOSW R55/SOUT IOSW SPIIF

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 61 ting the POL.. Figure 16-2 SPI Timing Diagram D1 D2 D3 D4 D6 D7D0 D5 D1 D2 D3 D4 D6 D7D0 D5 SIOST SCLK (POL=1) SCLK (POL=0) SOUT SIN SPIIF (SPI Int. Req) 76543210 C "0" 76543210C SIOR (Data Output :SOUT) SIOR (Data Input :SIN)

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 62 preliminary Nov. 1999 Ver 0.0 17. Buzzer Output function The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (480 Hz~250 KHz at fxin = 4 MHz) by user programmable counter. Pin R03 is assigned for output port of Buzzer driver by set- ting the bit BUZO of R0FUNC to "1". The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BUR. It is increased from 00H until it matches 6-bit register BUR. Also, it is cleared by counter overflow and count up to output the square wave pulse of duty 50%. The bit 0 to 5 of BUR determines output frequency for buzzer driving. Frequency calculation is following as shown below. The bits BUCK1, BUCK0 of BUR selects the source clock from prescaler output. Figure 17-1 Buzzer Driver /G05/G06/G07 () Oscillator Frequency BUR ADDRESS : DEH RESET VALUE : 11111111BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 ÷ 64 ÷ 16 ÷ 32 fXI MUX Counter ( 6-bit ) BUR ( 6-bit ) F/F BUCK[1:0] R03/BUZO ÷ 8 Input clock selection 00 : fXI ÷ 8 01 : fXI ÷ 16 10 : fXI ÷ 32 11 : fXI ÷ 64 Buzzer Period Data BUZO [R0FUNC.3] Bit Manipulation Not Available Overflow Detector Writing to BUR[5:0] RESET

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 63 18. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has twelve analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The A/D module has two registers which are the control register ADCM and A/D result register ADCR. The ADCM register, shown in Figure 18-2 , controls the oper- ation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O. To use analog inputs, each port is assigned analog input port by setting the bit ANSEL[7:0] in R6FUNC register. Also it is assigned analog input port by setting the bit AN- SEL[11:8] in R7FUNC register. And selected the corre- sponding channel to be converted by setting ADS[3:0]. The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hard- ware. The register ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag ADIF is set. The block diagram of the A/D module is shown in Figure 18-1 . The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conver- sion is in process. The conversion time takes maximum 20 uS (at f XI=4 MHz). Figure 18-1 A/D Converter Block Diagram R67/AN7 ANSEL7 0111 AVDD ADEN S/H Successive Approximation Circuit ADIF Resistor Ladder Circuit ADS[3:0] ADCR(8-bit) Sample & Hold A/D Interrupt ADDRESS : EBH RESET VALUE : Undefined A/D Result Register R7FUNC[3:0]R6FUNC[7:0] R66/AN6 ANSEL6 0110 R65/AN5 ANSEL5 0101 R64/AN4 ANSEL4 0100 R63/AN3 ANSEL3 0011 R62/AN2 ANSEL2 0010 R61/AN1 ANSEL1 0001 R60/AN0 ANSEL0 0000 R73/AN11 ANSEL11 1011 R72/AN10 ANSEL10 1010 R71/AN9 ANSEL9 1001 R70/AN8 ANSEL8 1000 [ADCM.6] COMPARATOR

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 65 (3) Pins AN11/R73 to AN8/R70 and AN7/R67 to AN0/ R60 The analog input pins AN11 to AN0 also function as input/ output port (PORT R7 and R6) pins. When A/D conver- sion is performed with any of pins AN11 to AN0 selected, be sure not to execute a PORT input instruction while con- version is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (4) AVDD pin input impedance A series resistor string of approximately 10KΩ is connected be- tween the AVDD pin and the AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AVDD pin and the AVSS pin, and there will be a large reference voltage error.

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 66 preliminary Nov. 1999 Ver 0.0 19. INTERRUPTS The GMS81C2020 and GMS81C2120 interrupt circuits consist of Interrupt enable register (IENH, IENL), Inter- rupt request flags of IRQH, IRQL, Interrupt Edge Selec- tion Register (IEDS), priority circuit and Master enable flag("I" flag of PSW). The configuration of interrupt cir- cuit is shown in Figure and Interrupt priority is shown in Table 19-1 . The External Interrupts INT0 and INT1 can each be transi- tion-activated (1-to-0, 0-to-1 and both transiton). The flags that actually generate these interrupts are bit INT0IF and INT1IF in Register IRQH. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 0 and Timer 1 Interrupts are generated by T0IF and T1IF, which are set by a match in their respective tim- er/counter register. The AD converter Interrupt is generat- ed by ADIF which is set by finishing the analog to digital conversion. The Watch dog timer Interrupt is generated by WDTIF which set by a match in Watch dog timer register (when the bit WDTON is set to "0"). The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflowing of the Basic Interval Timer Register(BITR). The Serial Peripheral Interface (SPI) is generated by SPIIF which is set by communicating with other peripheral of mi- crocontroller devices (by finishing the data transmission). Figure 19-1 Block Diagram of Interrupt Function BIT BITIF WDTIFWDT A/D Converter Timer 1 Timer 0 External Int. 1 External Int. 0 IENH[7:4] Interrupt Enable Interrupt Enable IRQH[7:4] IRQL Interrupt Vector Address Generator Internal bus line Register (Lower byte) Internal bus line Register (Higher byte) Release STOP To CPU Interrupt Master Enable Flag[PSW.2] I Flag IENL[7:4] Priority I-flag is in PSW, it is cleared by "DI", set by "EI" instruction.When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware. INT0IF INT1IF T0IF T1IF ADIF SPI SPIIF 4 IEDS[3:0] IRQL[7:4] IRQH Control

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 67 The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 19-2 . These registers are composed of interrupt enable flags of each in- terrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corre- sponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. Figure 19-2 Interrupt Enable Registers and Interrupt Request Registers When an interrupt is occured, the I-flag is cleared and dis- able any further interrupt, the return address and PSW are pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits. The interrupt request flag bit(s) must be cleared by soft- ware before re-enabling interrupts to avoid recursive inter- rupts. The Interrupt Request flags are able to be read and written. Reset/Interrupt Symbol Priority Vector Addr. Hardware Reset External Interrupt 0 External Interrupt 1 Timer 0 Timer 1 A/D Converter Watch Dog Timer Basic Interval Timer Serial Interface RESET INT0 INT1 Timer 0 Timer 1 A/D C WDT BIT SPI FFFE H FFFA H FFF8 H FFF6 H FFF4 H FFF2 H FFF0 H FFEE H FFEC H FFEA H FFE8 H FFE6 H Table 19-1 Interrupt Priority IENH ADDRESS : E2H RESET VALUE : 0000----INT0E INT1E T0E T1E Interrupt Enable Register High IENL ADDRESS : E3H RESET VALUE : 0000----ADE WDTE BITE SPIE - - - - Interrupt Enable Register Low IRQH ADDRESS : E4H RESET VALUE : 0000----INT0IF INT1IF T0IF T1IF Interrupt Request Register High IRQL ADDRESS : E5H RESET VALUE : 0000----ADIF WDTIF BITIF SPIIF - - - - Interrupt Request Register Low 0 : Disable 1 : Enable Enables or disables the interrupt individually If flag is cleared, the interrupt is disabled. 0 : Not occurred 1 : Interrupt request is occurred Shows the interrupt occurrence - - - - - - - -

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 68 preliminary Nov. 1999 Ver 0.0

19.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an in- struction. Interrupt acceptance sequence requires 8 f OSC (2 µs at fXI=4MHz) after the completion of the current in- struction execution. The interrupt service task is terminat- ed upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the inter- rupt service program is executed. Figure 19-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction A interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to "1" by “EI” instruction in the interrupt service program. In this case, acceptable interrupt sources are se- lectively enabled by the individual interrupt enable flags. Saving/Restoring General-purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. V.L. System clock Address Bus PC SP SP-1 SP-2 V.H. New PC V.L.Data Bus Not used PCH PCL PSW ADL OP codeADH Instruction Fetch Internal Read Internal Write Interrupt Processing Step Interrupt Service Task ADL and ADH are start addresses of interrupt service routine as vector contents. Basic Interval Timer 012H 0E3H 0FFE6 H 0FFE7 H 0EH 2EH 0E312 H 0E313H Entry Address Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. Vector Table Address

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 69 The following method is used to save/restore the general- purpose registers. Example: Register save using push and pop instructions General-purpose register save/restore using push and pop instructions;

19.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distin- guish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 19-4 . Figure 19-4 Execution of BRK/TCALL0

19.3 Multi Interrupt

If two requests of different priority levels are received si- multaneously, the request of higher priority level is ser- viced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence deter- mines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accept- ed, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further inter- rupt can be serviced even if certain interrupt is in progress. INTxx: PUSH A PUSH X PUSH Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG. interrupt processing POP Y POP X POP A RETI ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return B-FLAG BRK INTERRUPT ROUTINE RETI TCALL0 ROUTINE RET BRK or TCALL0

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 70 preliminary Nov. 1999 Ver 0.0 Figure 19-5 Execution of Multi Interrupt Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER1: PUSH A PUSH X PUSH Y LDM IENH,#80H;Enable INT0 only LDM IENL,#0;Disable other EI ;Enable Interrupt LDM IENH,#0FFH;Enable all interrupts LDM IENL,#0F0H POP Y POP X POP A RETI enable INT0 TIMER 1 service INT0 service Main Program service Occur TIMER1 interrupt Occur INT0 EI disable other enable INT0 enable other In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 71

19.4 External Interrupt

The external interrupt on INT0 and INT1 pins are edge triggered depending on the edge selection register IEDS (address 0E6 H ) as shown in Figure 19-6 . The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. Figure 19-6 External Interrupt Block Diagram Example: To use as an INT0, INT1 ;** Set port as an input port R00,R01 LDM R0IO,#1111_1100B ; Set port as an interrupt port LDM R0FUNC,#03H ;** Set Falling-edge Detection LDM IEDS,#0000_0101B Response Time The INT0 and INT1 edge are latched into INT0IF and INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a re- quest is active and conditions are right for it to be acknowl- edged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. shows interrupt response timings. Figure 19-7 Interrupt Response Timing Diagram INT0IFINT0 pin INT0 INTERRUPT INT1IFINT1 pin INT1 INTERRUPT IEDS [0E6H ] edge selection INT0 edge select Ext. Interrupt Edge Selection IEDS ADDRESS : 0E6 H RESET VALUE : ----0000 00: Int. disable WW W W 01: falling 10: rising 11: both INT1 edge select 00: Int. disable 01: falling 10: rising 11: both Register Interrupt goes active Interrupt latched Interrupt processing Interrupt routine 8 fOSCmax. 12 fOSC

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 72 preliminary Nov. 1999 Ver 0.0 20. WATCHDOG TIMER The purpose of the watchdog timer is to detect the mal- function (runaway) of program due to external noise or other causes and return the operation to the normal condi- tion. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is sep- arate from the external oscillator of the Xin pin. It means that the watchdog timer will run, even if the clock on the Xin pin of the device has been stopped, for example, by en- tering the STOP mode. The other type is a prescaled system clock. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as WDT interrupt or reset the CPU in accordance with the bit WDTON . Note: Because the watchdog timer counter is enabled af- ter clearing Basic Interval Timer, after the bit WD- TON set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 maching cycle. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below. The RCWDT oscillation period is vary with temperature, VDD and process variations from part to part (approxi- mately, 40~120uS ). The following equation shows the RCWDT oscillated watchdog timer time-out. T RCWDT =CLK RCWDT ×28×[WDTR.6~0]+(CLK RCWDT ×28)/2 where, CLK RCWDT = 40~120uS In addition, this watchdog timer can be used as a simple 7- bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. T WDT = [WDTR.6~0] ×××× Interval of BIT Figure 20-1 Block Diagram of Watchdog Timer LDM CKCTLR,#3FH; enable the RC-osc WDT LDM WDTR,#0FFH; set the WDT period STOP ; enter the STOP mode NOP NOP ; RC-osc WDT running Basic Interval Timer Interrupt Watchdog Timer BITIF 7-bit Counter WDTR (7-bit) OFD WDTCL WDTON Interrupt Request To RESET Clock Control Register CKCTLR ADDRESS : ECH RESET VALUE : -0010111- WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 - 0X1 XXXX Watchdog Timer Register WDTR ADDRESS : EDH RESET VALUE : 01111111WDTCL 7-bit Watchdog Counter Register Overflow Detection Bit Manipulation Not Available Bit Manipulation Not Available WDTCL RESET ÷ 8 ÷ 16 ÷ 128 ÷ 256 ÷ 512 ÷1024 ÷ 32 ÷ 64 0 MUXfXI BITR (8-BIT) BTS[2:0] RCWDT Internal RC OSC BTCL Clear WAKEUP STOP

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 73 21. Power Saving Mode For applications where power consumption is a critical factor, device provides four kinds of power saving func- tions, STOP mode, Subactive mode and Wake-up Timer mode(Standby mode, Watch mode). Table 21-1 shows the status of each Power Saving Mode. The power saving function is activated by execution of STOP instruction and by execution of STOP instruction after setting the corresponding status (WAKEUP) of CKCTLR. we shows the release sources from each Power Saving Mode Peripheral STOP Mode Subactive Mode Wake-up Timer Mode Standby Mode Watch Mode RAM Retain Retain Retain Retain Control Registers Retain Retain Retain Retain I/O Ports Retain Retain Retain Retain CPU Stop Operation Stop Stop Timer0 Stop Operation Operation Operation Oscillation Stop Stop Oscillation Stop Sub Oscillation Stop Oscillation Stop Oscillation Prescaler Stop Operation ÷ 2048 only ÷ 2048 only Entering Condition [WAKEUP] 00 1 1 Table 21-1 Power Saving Mode Release Source STOP Mode Subactive Mode Wake-up Timer Mode Standby Mode Watch Mode RESET O O O O RCWDT O O O O EXT.INT OOOO EXT.INT1 Timer0 X X O O Table 21-2 Release Sources from Power Saving Mode

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 74 preliminary Nov. 1999 Ver 0.0

21.1 Operating Mode

SCMR.1 = 0 fXI : oscillation fSXI : oscillation cpu : fSYS tmr : fSYS peri : fSYS SCMR.0 = 0 SCMR.1 = 0 SCMR.1 = 1 SUB-ACTIVE Mode SCMR.1 = 1 fXI : stop fSXI : oscillation cpu : fSUB tmr : fSUB peri : fSUB SCMR.0 = 0/1 STANDBY Mode SCMR.1 = 0 fXI : oscillation fSXI : oscillation cpu : stop tmr : ps11(f XI) peri : stop CKCTLR[10] STOP TIMER0 EXT_INT RESET RC_WDT WATCH Mode SCMR.1 = 1 fXI : stop fSXI : oscillation cpu : stop tmr : ps11(f SXI) peri : stop CKCTLR[10] STOP TIMER0 EXT_INT RESET RC_WDT STOP Mode SCMR.2 = 1 fXI : stop fSXI : stop cpu : stop tmr : stop peri : stop (SUB_CLK OFF) EXT_INT RESET RC_WDT CKCTLR[00] STOP EXT_INT RESET RC_WDT CKCTLR[00] STOP System Clock Mode Register SCMR ADDRESS : FAH RESET VALUE : ---00000- - - CS1 CS0 SUBOFF CLKSEL MAINOFF CS[1:0] Clock selection enable bits 00 : fXI ÷ 210 : fXI ÷16 01 : fXI ÷ 811 : fXI ÷ 64 CLKSEL Clock selection bit 0 : Main clock selection 1 : Sub clock selection SUBOFF Sub clock control bit 0: On sub clock 1: Off sub clock MAINOFF Main clock control bit 0: On main clock 1: Off main clock fXI : main clock frequency fSXI : sub clock frequency fSYS : fXI÷2,fXI÷8,fXI÷16,fXI÷64 fSUB : fSXI÷2,fSXI÷8,fSXI÷16,fSXI÷64 cpu : system clock tmr : timer0 clock peri : peripheral clock CKCTLR = CKCTLR[6:5]

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 75

21.2 Stop Mode

In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port di- rection registers. Oscillator stops and the systems internal operations are all held up.

• The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held.
• The program counter stop the address of the instruction to be executed after the instruction "STOP" which starts the STOP operating mode. The Stop mode is activated by execution of STOP in- struction after clearing the bit WAKEUP of CKCTLR to “0”. ( This register should be written by byte operea- tion. If this register is set by bit manipulation instrunc- tion, for example "set1" or "clr1" instruction, it may be undesired operation ) In the Stop mode of operation, V DD can be reduced to min- imize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. Note: After STOP instruction, at least two or more NOP in- struction should be written Ex) LDM CKCTLR,#0000_1110B STOP NOP NOP In the STOP operation, the dissipation of the power asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (V DD /VSS); however, when the input level gets high- er than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. Release the STOP mode The exit from STOP mode is hardware reset or external in- terrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their val- ues. If I-flag = 1, the normal interrupt response takes place. If I- flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vec- tor to interrupt service routine. ( refer to Figure 21-1 ) When exit from Stop mode by external interrupt, enough oscillation stabilization time is required to normal opera- tion. Figure 21-4 shows the timing diagram. When release the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00 H until FFH . The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler di- vide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure 21-5 . Figure 21-1 STOP Releasing Flow by Interrupts IEXX STOP INSTRUCTION STOP Mode Interrupt Request STOP Mode Release I-FLAG Interrupt Service Routine Next INSTRUCTION Master Interrupt Enable Bit PSW[2] Corresponding Interrupt Enable Bit (IENH, IENL)

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 76 preliminary Nov. 1999 Ver 0.0 Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Note: In the STOP operation, the power dissipation asso- ciated with the oscillator and the internal hardware is lowered; however, the power dissipation associat- ed with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD /VSS ); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means. It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn’t flow. But input voltage level should be V SS or VDD . Be careful that if unspecified voltage, i.e. if unfirmed voltage level (not V SS or VDD ) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up re- sistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. Figure 21-2 Application Example of Unused Input Port INPUT PIN VDD GND i VDD X Weak pull-up current flows VDD internal pull-up INPUT PIN i VDD X Very weak current flowsVDD O O OPEN OPEN i=0 O i=0 O GND When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption.* Pull-up is Metal Option

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 78 preliminary Nov. 1999 Ver 0.0 Figure 21-5 Timing of STOP Mode Release by RESET

21.3 Wake-up Timer Mode

In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler( only 2048 devided ratio ) and Timer0, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port di- rection registers. The Wake-up Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP of CKCTLR to “1”. ( This register should be written by byte opereation. If this register is set by bit manipula- tion instrunction, for example "set1" or "clr1" instruc- tion, it may be undesired operation ) Note: After STOP instruction, at least two or more NOP in- struction should be written Ex) LDM TDR0,#0FFH LDM TM0,#0001_1011B LDM CKCTLR,#0100_1110B STOP NOP NOP In addition, the clock source of timer0 should be selected to 2048 devided ratio. Otherwise, the wake-up function can not work. And the timer0 can be operated as 16-bit tim- er with timer1. ( refer to timer function )The period of wake-up function is varied by setting the timer data regis- ter 0, TDR0. Release the Wake-up Timer mode The exit from Wake-up Timer mode is hardware reset, Timer0 overflow or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts and Timer0 overflow allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I- flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vec- tor to interrupt service routine.( refer to Figure 21-1 ) When exit from Wake-up Timer mode by external inter- rupt or timer0 overflow, the oscillation stabilization time is not required to normal operation. Because this mode do not stop the on-chip oscillator shown as Figure 21-6 . STOP Mode Time can not be control by software Oscillator (XI pin) ~~~ STOP Instruction Execution Stabilization Time tST = 64mS @4MHz Internal Clock Internal ~~ ~ RESETB RESETB Wake-up Timer Mode Oscillator (XI pin) /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 STOP Instruction Normal Operation Normal Operation CPU Clock Request Interrupt ~~~ Execution Do not need Stabilization Time( stop the CPU clock )

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 79 Figure 21-6 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt

21.4 Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction regis- ters. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after set- ting the bit WAKEUP and RCWDT of CKCTLR to " 01 ". ( This register should be written by byte operea- tion. If this register is set by bit manipulation instruc- tion, for example "set1" or "clr1" instruction, it may be undesired operation ) Note: Caution : After STOP instruction, at least two or more NOP instruction should be written Ex) LDM WDTR ,#1111_1111B LDM CKCTLR ,#0010_1110B STOP NOP NOP The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt. Reset re-de- fines all the Control registers but does not change the on- chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine.(Figure 21-7 ) However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal RESET signal and exe- cute the reset processing. (Figure 21-8 ) If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.( refer to Figure 21-1 ) When exit from Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to normal operation. Figure 21-7 shows the timing diagram. When release the Internal RC-Oscil- lated Watchdog Timer mode, the basic interval timer is ac- tivated on wake-up. It is increased from 00 H until FFH . The count overflow is set to start normal operation. There- fore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from internal RC-Oscillated Watchdog Tim- er mode is shown in Figure 21-8 . Figure 21-7 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt RCWDT Mode Normal Operation Oscillator (XI pin) /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 ~~~ N+1NN + 2 00 01 FE FF 00 00N-1N-2 ~~~ ~~ ~ Clear Basic Interval TimerSTOP Instruction Execution Normal Operation Stabilization Time tST > 20mS Internal Clock External Interrupt BIT Counter Internal RC Clock ( or WDT Interrupt )

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 80 preliminary Nov. 1999 Ver 0.0 Figure 21-8 Internal RCWDT Mode Releasing by RESET Oscillator (XI pin) ~~ ~ Internal Clock Internal RC Clock Time can not be control by software STOP Instruction Execution Stabilization Time tST = 64mS @4MHz Internal RESET by WDT RESET RESET RCWDT Mode

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 81 22. RESET The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 26-2 . Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. Initial state of each register is shown as Table 11-3 . Figure 22-1 Timing Diagram after RESET MAIN PROGRAM Oscillator (XI pin) /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 ? ? FFFE FFFF Stabilization Time tST = 64mS at 4MHz RESET ADDRESS DATA 1 2 3 4 5 6 7 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 ?? Start ? ?? FE? ADL ADH OP /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0/i0/i0/i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 BUS BUS RESET Process Step ~~ ~ ~~~ ~~~

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 83 Figure 23-3 Power Fail Processor Situations Internal RESET Internal RESET Internal RESET VDD VDD VDD PFV DD MAX PFV DD MIN PFV DD MAX PFV DD MIN PFV DD MAX PFV DD MIN 64mS 64mS t < 64mS 64mS When PFDM = 1

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 84 preliminary Nov. 1999 Ver 0.0 24. OTP PROGRAMMING

24.1 DEVICE CONFIGURATION AREA

The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as secu- rity bit. sixteen memory locations ( 7030 H ~ 703FH ) are designat- ed as Customer ID recording locations where the user can store check-sum or other customer identification numbers. This area is not accessible during normal execution but is readable and writable during program / verify. Figure 24-1 Device Configuration Area DEVICE 7030H 7030H 703FH 703FH ID CONFIG CONFIGURATION AREA 7031HID 7032HID 7033HID 7034HID 7035HID 7036HID 7037HID 7038HID 7039HID Configuration Register CONFIG ADDRESS :703FHSXB / R7 0 : Crystal Oscillator 1 : External RC Oscillator EXTERNAL RCOSC 703AHID 703BHID 703C HID 703D HID 703EHID PFD1 PFD0 EXTERNAL RCOSC CODE PROTECT 0 : ALLOW CODE READ OUT 1 : LOCK CODE READ OUT CODE PROTECT 0 0 : PFD1 = 2.7V PFD LEVEL SELECTION 0 1 : PFD1 = 2.7V 1 0 : PFD2 = 3.0V 1 1 : PFD3 = 2.4V 0 : SUB CLOCK 1 : R74, R75 SXB / R7

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 85 Figure 24-2 Pin Assignmen (64SDIP)t VDD VPP A_D0 A_D1 A_D2 A_D3 EPROM Enable A_D7 A_D6 A_D5 A_D4 CTL2 CTL1 CTL0 VSS R40 R42 R43 R50 R51 R52 R53 R54 R55 R56 R57 RESETB XI XO VSS SXI SXO AVSS R60 R61 R62 R63 R64 R65 R66 R67 R70 R71 R72 R73 AVDD RA/Vdisp R35 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 R04 R03 R02 R01 R00 VDD R41 CTL3 64SDIP Pin No. User Mode EPROM MODE Pin Name Pin Name Description

8 R53 CTL3 Read/Write Control P_Vb

9 R54 CTL2 Address/Data Control D_Ab

10 R55 CTL1 Write 8Bytes Control PGM8

11 R56 CTL0 Write 4Bytes Control PGM4

13 RESETB VPP Programming Power (0V, 12.75V)

14 XI EPROM Enable High Active, Latch Address in falling edge

15 XO NC No connection

16 VSS VSS Connect to VSS (0V)

20 R60 A_D0

21 R61 A_D1 A9 A1 D1

22 R62 A_D2 A10 A2 D2

23 R63 A_D3 A11 A3 D3

24 R64 A_D4

25 R65 A_D5 A13 A5 D5

26 R66 A_D6 A14 A6 D6

27 R67 A_D7 A15 A7 D7

33 VDD VDD Connect to VDD

(6.0V) Table 24-1 Pin Description in EPROM Mode (GMS81C2020)

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 86 preliminary Nov. 1999 Ver 0.0 Figure 24-3 Pin Assignmen (42SDIP)t VPP A_D0 A_D1 A_D2 A_D3 EPROM Enable A_D7 A_D6 A_D5 A_D4 CTL2 CTL1 CTL0 VSS CTL3 R53 R54 R55 R56 R57 RESETB XI XO VSS AV SS R60 R61 R62 R63 R64 R65 R66 R67 AV DD RA R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R05 R04 R03 R02 R01 R00VDD 42PDIP R07 R06VDD Pin No. User Mode EPROM MODE Pin Name Pin Name Description

2 R53 CTL3 Read/Write Control P_Vb

3 R54 CTL2 Address/Data Control D_Ab

4 R55 CTL1 Write 8Bytes Control PGM8

5 R56 CTL0 Write 4Bytes Control PGM4

7 RESETB VPP Programming Power (0V, 12.75V)

8 XI EPROM Enable High Active, Latch Address in falling edge

9 XO NC No connection

10 VSS VSS Connect to VSS (0V)

12 R60 A_D0

13 R61 A_D1 A9 A1 D1

14 R62 A_D2 A10 A2 D2

15 R63 A_D3 A11 A3 D3

16 R64 A_D4

17 R65 A_D5 A13 A5 D5

18 R66 A_D6 A14 A6 D6

19 R67 A_D7 A15 A7 D7

21 VDD VDD Connect to VDD

(6.0V) Table 24-2 Pin Description in EPROM Mode (GMS81C2120)

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 87 Figure 24-4 Timing Diagram in Program (Write & Verify) Mode VPP CTL0/1 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0 High 8bit HA LA DATA IN DATA ~~~~ ~~~ ~OUT LA DATA IN DATA OUT EPROM Enable CTL2 CTL3 A_D7~ VDD VDD1H Address Input Low 8bit Address Input Write Mode Verify Low 8bit Address Input Write Mode Verify A_D0 TVDDS TVPPR TVPPS VDD1H VDD1H VIHP THLD1 THLD2TSET1 TDLY1 TDLY2 TCD1 TCD1 TCD1 TCD1

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 88 preliminary Nov. 1999 Ver 0.0 Figure 24-5 Timing Diagram in READ Mode Parameter Symbol MIN TYP MAX Unit Programming Supply Current IVPP -- 5 0 m A Supply Current in EPROM Mode IVDDP -- 2 0 m A VPP Level during Programming VIHP 11.5 12.0 12.5 V VDD Level in Program Mode VDD1H 56 6 . 5 V VDD Level in Read Mode VDD2H -2 . 7-V CTL3~0 High Level in EPROM Mode VIHC 0.8VDD -- V CTL3~0 Low Level in EPROM Mode VILC -- 0.2VDD V A_D7~A_D0 High Level in EPROM Mode VIHAD 0.9VDD -- V A_D7~A_D0 Low Level in EPROM Mode VILAD -- 0.1VDD V VDD Saturation Time TVDDS 1-- m S VPP Setup Time TVPPR --1 m S VPP Saturation Time TVPPS 1-- m S EPROM Enable Setup Time after Data Input TSET1 200 nS EPROM Enable Hold Time after TSET1 THLD1 500 nS Table 24-3 AC/DC Requirements for Program/Read Mode VPP CTL0/1 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0 High 8bit HA LA DATA LA DATA DATA EPROM Enable CTL2 CTL3 A_D7~ VDD VDD2H Address Input Low 8bit Address Input DATA A_D0 TVDDS TVPPR TVPPS VDD2H VDD2H VIHP THLD1 THLD2TSET1 TDLY1 TDLY2 TCD1 TCD2 TCD2 TCD1 HA LA Output Low 8bit Address Input High 8bit Address Input Low 8bit Address Input DATA Output DATA Output After input a high address, output data following low address inputAnothe high address step

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 89 Figure 24-6 Programming Flow Chart EPROM Enable Delay Time after THLD1 TDLY1 200 nS EPROM Enable Hold Time in Write Mode THLD2 100 nS EPROM Enable Delay Time after THLD2 TDLY2 200 nS CTL2,1 Setup Time after Low Address input and Data input TCD1 100 nS CTL1 Setup Time before Data output in Read and Verify ModeTCD2 100 nS Table 24-3 AC/DC Requirements for Program/Read Mode START Set VDD=V DD1H Set VPP=VIHP Verify blank First Address Location EPROM Write N=1 Verify pass Last address Apply 3N program cycle 100uS program time Next address location Verify pass Report Programming failure Report Programming failure Verify fof all address Verify OK Report Verify failure Report Programming OK VDD=VPP=0v END NO YES YES YES YES YES NO NO NO NO

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 90 preliminary Nov. 1999 Ver 0.0 START Set VDD=V DD2H Set VPP=VIHP Last address First Address Location VDD=0V Report Read OK VPP=0V Next address location Verify fof all address END NO YES

Hyundai Micro Electronics GMS81C2020/GMS81C2120 Nov. 1999 Ver 0.0 preliminary 91 GMS81C2 Series [GMS81C2020/12] Option List Package I/O Option [VFD Driving Port] I/O Option [Normal Port] RA / Vdisp 64SDIP 64MQFP 64LQFP 64TQFP Date of Order Customer Department Name ROM Code Name Check sum ROM Size 1999 / 2000. . . 20KBytes 12KBytes RA Without pull-down resistance Vdisp *Note : In the I/O options list, you must select Vdisp even if only one pin is selected with pull-down resistance. ROM Code Option List : 703FH 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 - SXB / R7 PFD1 PFD0 - LOW RCOSCVOLTAGE * Refer to Device Configuration Area Bit I/O I/O Option On Off R40/T0O I/O R41 I/O R42 I/O R43 I/O Bit I/O I/O Option On Off R10 I/O R11 I/O R12 I/O R13 I/O R14 I/O R15 I/O R16 I/O R17 I/O Bit I/O I/O Option On Off R50 I/O R51 I/O R52 I/O R53/SCLK I/O R54/SIN I/O R55/SOUT I/O R56/PWM1O I/O R57 I/O Bit I/O I/O Option On Off R20 I/O R21 I/O R22 I/O R23 I/O R24 I/O R25 I/O R26 I/O R27 I/O Bit I/O I/O Option On Off R60/AN0 I/O R61/AN1 I/O R62/AN2 I/O R63/AN3 I/O R64/AN4 I/O R65/AN5 I/O R66/AN6 I/O R67/AN7 I/O Bit I/O I/O Option On Off R30 I/O R31 I/O R32 I/O R33 I/O R34 I/O R35 I/O Bit I/O I/O Option On Off R70/AN8 I/O R71/AN9 I/O R72/AN10 I/O R73/AN11 I/O Bit I/O I/O Option On Off R00/INT0 I/O R01/INT1 I/O R02/EC0 I/O R03/BUZO I/O R04 I/O R05 I/O R06 I/O R07 I/O * On : with pull-down resistance * Off : without pull-down resistance * On : with pull-up * Off : without pull-up R74 I/O R75 I/O

GMS81C2020/GMS81C2120 Hyundai Micro Electronics 92 preliminary Nov. 1999 Ver 0.0 GMS81C2 Series [GMS81C2120/12] Option List Package I/O Option [VFD Driving Port] I/O Option [Normal Port] RA / Vdisp 42SDIP 40PDIP 44MQFP Date of Order Customer Department Name ROM Code Name Check sum ROM Size 1999 / 2000. . . 20KBytes 12KBytes RA Without pull-down resistance Vdisp *Note : In the I/O options list, you must select Vdisp even if only one pin is selected with pull-down resistance. ROM Code Option List : 703FH 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 - - PFD1 PFD0 - LOW RCOSCVOLTAGE * Refer to Device Configuration Area Bit I/O I/O Option On Off R53/SCLK I/O R54/SIN I/O R55/SOUT I/O R56/PWM1O I/O R57 I/O Bit I/O I/O Option On Off R20 I/O R21 I/O R22 I/O R23 I/O R24 I/O R25 I/O R26 I/O R27 I/O Bit I/O I/O Option On Off R60/AN0 I/O R61/AN1 I/O R62/AN2 I/O R63/AN3 I/O R64/AN4 I/O R65/AN5 I/O R66/AN6 I/O R67/AN7 I/O Bit I/O I/O Option On Off R30 I/O R31 I/O R32 I/O R33 I/O R34 I/O Bit I/O I/O Option On Off R00/INT0 I/O R01/INT1 I/O R02/EC0 I/O R03/BUZO I/O R04 I/O R05 I/O R06 I/O R07 I/O * On : with pull-down resistance * Off : without pull-down resistance * On : with pull-up * Off : without pull-up