HC2509C HYNIX | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 6
Technical content
Features
l Phase - Locked Loop Clock Distribution for Synchronous DRAM Applications l Supports PC - 100 and Meets “ PC100 SDRAM registered DIMM Specification Rev. 1.2 ” l Distrib utes One Clock Input to One Bank of Five and One Bank of Four Outputs l No External RC Network Required l External Feedback (FBIN) Pin is Used to Synchronize the Outputs to the Clock Input l Separate Output Enable for Each Output Bank l Operates at 3.3 V V cc l 125 MHz Maximum Frequency l On - chip Series Damping Resistors l Support Spread Spectrum Clock(SSC) Synthesizers l ESD Protection Exceeds 3000 V per MIL - STD - 883, Method 3015 ; Exceeds 350 V Using Machine Model ( C = 200 pF, R = 0 ) l Latch - Up Performance Exceeds 40 0 mA per JESD 17 l Packaged in Plastic 24 - Pin Thin Shrink Small - Outline Package Pin Configuration General Description The HC2509C is a low - skew, low jitter, phase - locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM. The H C2509C operates at 3.3V V cc and provides integrated series - damping resistors that make it ideal for driving point - to - point loads. The propagation delay from the CLK input to any clock output is nearly zero. One bank of five outputs and one bank of four ou tputs provide nine low - skew and low - jitter clocks. Each bank of outputs can be enabled or disabled separately via the control inputs (1G and 2G). Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The HC2509C is sp ecially designed to interface with high speed SDRAM applications in the range of 25MHz to 125MHz and includes an internal RC network which provides excellent jitter characteristics and eliminates the needs for external components. For the test purpose, the PLL can be bypassed by strapping AV cc to ground. The HC2509C is characterized for operation from 0 °C to 85 °C. Function Table INPUTS OUTPUTS 1Y 2Y 1G 2G CLK (0:4) (0:3) FBOUT X X L L L L L L H L L H L H H L H H H L H H L H H H H H H H TSSOP 24 PACKAGE (TOP VIEW) AGND Vcc 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 Vcc FBOUT CLK AVcc Vcc 2Y0 2Y1 GND GND 2Y2 2Y3 Vcc FBIN
Table 1. Pin Description CLK 24 I Clock Input. CLK provides the reference signal to the internal PLL. FBIN 13 I Feedback Input. FBIN provides the feedback signal to th e internal PLL. IG 11 I Output Bank Enable. When 1G is high, all outputs 1Y(0:4) are enabled. When 1G is low, Outputs 1Y(0:4) are disabled to a logic - low state. 2G 14 I Output Bank Enable. When 2G is high, all outputs 2Y(0:3) are enabled. When 2G is low, Outputs 2Y(0:3) are disabled to a logic - low state. has an emb edded series - damping resistor. has an embedded series - damping resistor. circuitry. AV cc can be also used to bypass the PLL for the test purpose. AGND 1 Ground Analog Ground. AGND provides the ground reference for the analog c ircuitry. Table 2. Absolute Maximum Ratings Over Operating Free - air Temperature
Table 3. Recommended Operating Conditions Table 4. Electrical Characteristics Over Recommended Operating
0.2 Min to Max IOL = 100 µA
§ Time to obtain phase lock of its feedback signal to it s reference signal.
Table 6. Switching Characteristics Over Recommended Ranges of Supply =These parameters are not production tested. ♣ Phase error does not include jitter . Figure 1. Load Circuit and Voltage Waveforms
Figure 2. Phase Error and Skew Calcu lations