H5GQ1H24AFR

H5GQ1H24AFR HYNIX | Alldatasheet

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 1 H5GQ1H24AFR 1Gb (32Mx32) GDDR5 SGRAM H5GQ1H24AFR

Rev. 1.0/Nov. 2009 2 H5GQ1H24AFR

Revision History

Revision No. History Draft Date Remark 0.1 Defined target spec. Dec. 2008 Preliminary 0.2 Updated tRTPS / tRTW / tFAW / t32AW / Thermal Characteristics Mar. 2009 Preliminary 0.3 Updated tCKE / Pin Cap / CRCWL / CRCRL/ IDD / PLL Value April. 2009 Preliminary

0.4 Updated tRRDL / Revision ID/ Density ID

May. 2009 Preliminary 0.5 Updated tCKE / tCKSRE / tCKSRX (@ 6Gbps only) May. 2009 Preliminary

0.6 Updated CRCWL / VREFD Selection Coding

Updated Auto VREFD Training Updated tCKE & tPD Updated Leakage Current Updated x16 Mode IDD Value & 1.35V Timing Parameters Updated Ordering Information July. 2009 Preliminary 0.7 VREFD Options Figure31 change Sep. 2009 Preliminary 1.0 Revision 1.0 Release Nov. 2009

Rev. 1.0/Nov. 2009 3 H5GQ1H24AFR TABLE OF CONTENTS

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 4 H5GQ1H24AFR

Rev. 1.0/Nov. 2009 5 H5GQ1H24AFR

FEATURES

• S i n g l e ended interface for data, address and command
• Q u a r t e r data‐rate differential clock inputs CK/CK# for ADR/CMD
• T w o half data‐rate differential clock inputs WCK/ WCK#, each associated with two data bytes (DQ, DBI#, EDC)
• D o u b l e Data Rate (DDR) data (WCK)
• S i n g l e Data Rate (SDR) command (CK)
• D o u b l e Data Rate (DDR) addressing (CK)
• 1 6 internal banks
• 4 bank groups for tCCDL = 3 tCK
• 8 n prefetch architecture: 256 bit per array read or write access
• B u r s t length: 8 only
• Programmable CAS latency: 5 to 20 tCK
• Programmable WRITE latency: 1 to 7 tCK
• W R I T E Data mask function via address bus (single/ double byte mask)
• Data bus inversion (DBI) & address bus inversion (ABI)
• Input/output PLL on/off mode
• Address training: address input monitoring by DQ pins
• WCK2CK clock training with phase information by EDC pins
• Data read and write training via READ FIFO
• R E A D FIFO pattern preload by LDFF command
• D i r e c t write data load to READ FIFO by WRTR command
• C o n s e c u t i v e read of READ FIFO by RDTR command
• Read/Write data transmission integrity secured by cyclic redundancy check (CRC‐8)
• READ/WRITE EDC on/off mode
• Programmable EDC hold pattern for CDR
• Programmable CRC READ latency = 0 to 3 tCK
• Programmable CRC WRITE latency = 7 to 14 tCK
• L o w Power modes
• R D Q S mode on EDC pin
• O p t i o n a l on‐chip temperature sensor with read‐out
• A u t o & self refresh modes
• A u t o precharge option for each burst access
• 32ms, auto refresh (8k cycles)
• Temperature sensor controlled self refresh rate
• O n ‐die termination (ODT); nominal values of 60 ohm and 120 ohm
• P s e u d o open drain (POD‐15) compatible outputs (40 ohm pulldown, 60 ohm pullup)
• O D T and output drive strength auto‐calibration with external resistor ZQ pin (120 ohm)
• Programmable termination and driver strength offsets
• Selectable external or internal VREF for data inputs; programmable offsets for internal VREF
• Separate external VREF for address / command inputs
• V e n d o r ID, FIFO depth and Density info fields for identification
• x32/x16 mode configuration set at power‐up with EDC pin
• M i r r o r function with MF pin
• Boundary scan function with SEN pin
• 1 . 6 V / 1.5V +/‐ 0.045V supply for device operation (VDD)
• 1 . 6 V / 1.5V +/‐ 0.045V supply for I/O interface (VDDQ)
• 170 ball BGA package FUNCTIONAL DESCRIPTION The GDDR5 SGRAM is a high speed dynamic random‐access memory designed for applications requiring high bandwidth. GDDR5 devices contain the following number of bits:

1 Gb has 1,073,741,824 bits and sixteen banks

The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high‐ speed operation. The device can be configured to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device initialization. The GDDR5 interface transfers two 32 bit wide data words per WCK clock cycle to/from the I/O pins. Corresponding to the 8n‐prefetch a single write or read access consists of a 256 bit wide, two CK clock cycle data transfer at the internal memory core and eight corresponding 32 bit wide one‐half WCK clock cycle data transfers at the I/O pins. The GDDR5 SGRAM operates from a differential clock CK and CK#. Commands are registered at every rising edge of CK. Addresses are registered at every rising edge of CK and every rising edge of CK#. GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running differential forwarded clock (WCK/WCK#) with both input and output data registered and driven respectively at both edges of the forwarded WCK. Read and write accesses to the GDDR5 SGRAM are burst oriented; an access starts at a selected location and consists of a total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command and the next rising CK# edge are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command and the next rising CK# edge are used to select the bank and the column location for the burst access.

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ORDERING INFORMATION

Above Hynix P/N’s are Leead-free, RoHS Compliant and Halogen-free. Part No Power Supply CK Frequency WCK Frequency Max Data Rate Interface H5GQ1H24AFR-R0C VDD/VDDQ = 1.6V 1.50GHz 3.00GHz 6.0Gbps/pin POD_15 H5GQ1H24AFR-T3C VDD/VDDQ = 1.5V 1.375GHz 2.75GHz 5.5Gbps/pin H5GQ1H24AFR-T2L (Note1) 1.25GHz 2.50GHz 5.0Gbps/pin H5GQ1H24AFR-T2C 1.25GHz 2.50GHz 5.0Gbps/pin H5GQ1H24AFR-T1C 1.125GHz 2.25GHz 4.5Gbps/pin H5GQ1H24AFR-T0C 1.00GHz 2.00GHz 4.0Gbps/pin

Rev. 1.0/Nov. 2009 7 H5GQ1H24AFR 0.1. DEFINITION OF SIGNAL STATE TERMINOLOGY GDDR5 SGRAM will be operated in both ODT Enable (terminated) and ODT Disable (unterminated) modes. For highest data rates it is recommended to operate in the ODT Enable mode. ODT Disable mode is designed to reduce power and may operate at reduced data rates. There exist situations where ODT Enable mode can not be guaranteed for a short period of time, i.e. during power up. Following are four terminologies defined for the state of a device (GDDR5 SGRAM or controller) pin dur‐ ing operation. The state of the bus will be determined by the combination of the device pins connected to the bus in the system. For example in GDDR5 it is possible for the SGRAM pin to be tristated while the controller pin is High or ODT. In both cases the bus would be High if the ODT is enabled. For details on the GDDR5 SGRAM pins and their function see “PACKAGE SPECIFICATION” on page 156 and “SIG‐ NALS” on page 158 in the section entitled “PACKAGE SPECIFICATION” on page 156. Device pin signal level:

• H i g h : A device pin is driving the Logic “1” state.
• L o w : A device pin is driving the Logic “0” state.
• H i ‐Z: A device pin is tristate.
• O D T : A device pin terminates with ODT setting, which could be terminating or tristate depending on Mode Register setting. Bus signal level:
• H i g h : One device on bus is High and all other devices on bus are either ODT or Hi‐Z. The voltage level on the bus would be nominally VDDQ
• L o w : One device on bus is Low and all other devices on bus are either ODT or Hi‐Z. The voltage level on the bus would be nominally VOL(DC) if ODT was enabled, or VSSQ if Hi‐Z.
• H i ‐Z: All devices on bus are Hi‐Z. The voltage level on bus is undefined as the bus is floating.
• O D T : At least one device on bus is ODT and all others are Hi‐Z. The voltage level on the bus would be nominally VDDQ.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 8 H5GQ1H24AFR 0.2. CLOCKING The GDDR5 SGRAM operates from a differential clock CK and CK#. Commands are registered at every rising edge of CK. Addresses are registered at every rising edge of CK and every rising edge of CK#. GDDR5 uses a DDR data interface and an 8n‐prefetch architecture. The data interface uses two differen‐ tial forwarded clocks (WCK/WCK#). DDR means that the data is registered at every rising edge of WCK and rising edge of WCK#. WCK and WCK# are continuously running and operate at twice the frequency of the command/address clock (CK/CK#). Figure 1: GDDR5 Clocking and Interface Relationship CK CK# COMMAND ADDRESS DQ*1 WCK WCK# Note : Figure.1 shows the relationship between the data rate of the buses and the clocks and is not a timing diagram.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 9 H5GQ1H24AFR Figure 2: Block Diagram of an example clock system Clock Phase Oscillator QD CMD/ADD CMD/ADD DRAM QD QB DQ [0]‐[7] DQ early/late Receiver D Q WCKint DQ DRAM PLL QD DQ Phase detector/ corelogic early/late from For 8 data bits Controller GDDR5 SGRAM PLL clock Data Tx/Rx WCK/WCK# (2GHz) CK/CK# (1GHz) CMD sampled by CK/CK# as SDR ADD sampled by CK/CK# as DDRADD/CMD centered with CK/CK# calibration data Phase accumulator Controller Clock Phase Controller (4Gbps) core core (1GHz) D Q WCK2CK Alignment To EDC pin

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 10 H5GQ1H24AFR 1. INITIALIZATION 1.1. POWER‐UP SEQUENCE GDDR5 SGRAMs must be powered up and initialized in a pr edefined manner as shown in <Link>Figure . Operational procedures other than those specified may result in undefined operat ion. The Mode Registers do not have RESET default values, except for ABI#, ADR/CMD termination, and the EDC hold pattern. If the mode registers are not set dur- ing the initialization sequence, it may lead to unspecified operation. Step 1A p p l y power to VDD 2A p p l y power to VDDQ at same time or after power is applied to VDD 3A p p l y VREFC and VREFD at same time or after power is applied to VDDQ 4A f t e r power is stable, provide stable clock signals CK/CK# 5 Assert and hold RESET# low to ensure all drivers are in Hi‐Z and all active terminations are off. Assert and hold NOP command. 6 Wait a minimum of 200μs. 7 If boundary scan mode is necessary, SEN can be asserted HIGH to enter boundary scan mode. Boundary scan mode must be entered directly after power‐up while RESET# is low. Once boundary scan is executed, power‐up sequence should be followed. Set CKE# for the desired ADR/CMD ODT settings, then bring RESET# High to latch in the logic state of CKE#, tATS and tATH must be met during this procedure. See <Link>Table 1 for the values and logic states for CKE#. The rising edge of RESET# will determine x32 mode or x16 mode depending on the state of EDC1(EDC2 when MF=1). In normal x32 mode, EDC1 has to be sustained HIGH until RESET# is HIGH. See <Link>Table for the values and logic states for EDC1(EDC2 when MF=1). 9B r i n g CKE# Low after tATH is satisfied

10 Wait at least 200μs referenced from the beginning of tATS

11 Issue at least 2 NOP commands

12 Issue a PRECHARGE ALL command followed by NOP commands until tRP is satisfied

13 Issue MRS command to MR15. Set GDDR5 SGRAM into address training mode (optional)

14 Complete address training (optional)

15 Issue MRS command to read the Vendor ID

16 Issue MRS command to set WCK01/WCK01# and WCK23/WCK23# termination values

17 Provide stable clock signals WCK01/WCK01# and WCK23/WCK23#

Issue MRS commands to use PLL or not and select the position of a WCK/CK phase detector. The use of PLL and the position of a phase detector should be issued before WCK2CK training. Issue MRS commands including PLL reset to the mode registers in any order. tMRD must be met during this procedure. WLmrs, CLmrs, CRCWL and CRCRL must be programmed before WCK2CK training.

19 Issue two REFRESH commands followed by NOP until tRFC is satisfied

20 After any necessary GDDR5 training sequences such as WCK2CK training, READ training (LDFF, RDTR) and WRITE training (WRTR, RDTR), the device is ready for operation.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 12 H5GQ1H24AFR 1) Assert RESET# Low anytime when reset is needed. 2) Hold RESET# Low for minimum 100ns. Assert and hold NOP command. 3) Set CKE# for the desired ADR/CMD ODT settings, then bring RESET# High to latch in the logic state of CKE#; tATS and tATH must be met during this procedure. Keep EDC1 (MF=0) / EDC2 (MF=1) at the same logic level as during power‐up initialization as device functionality is not guaranteed if the I/O width has changed. 4) Continue with step 9 of the power‐up initialization sequence. Figure 4: Initialization with Stable Power TRAIN / MRS ADR CKE# min. 100 ns CMD VDD, VDDQ VREFD/C RESET# tATS tATH DQ<31:0>, DBI#<3:0> ADR EDC<3:0> All Banks Precharge WCK NOPNOP CK# CK WCK# PRE NOP tRP Execution of steps 13‐21 in Power‐up sequence TRAIN / MRS TRAIN / MRS ADR A.C. ADR ADR min. 200 μs NOPNOP TRAIN / MRS A.C. ) ) ) ) 2. Device functionality is not guaranteed if x32/x16 mode is not the same as during power‐up initialization. Notes: 1. A.C. = Any Command

responsability for use of circuits described. No patent licenses are implied. bits [11:10] as shown in Table 3 & Table4. Bits [15:12] are RFU. The Vendor ID will be driven onto the DQ bus after the MRS command that sets bits A6 to 1 and A7 to 0. would be replicated on Byte 0 and Byte 3 would be replicated on Byte 2. TABLE 2. Manufacturers Vendor Code

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 14 H5GQ1H24AFR Figure 5: Vendor ID Timing Diagram Table 3 Revision ID & Density & FIFO Depth Revision ID Density FIFO Bit 7 Bit 6 Bit 6 Bit 4 Bit 9 Bit 8 Bit 11 Bit 10 00010110 Table 4 Vendor ID to DQ mapping Bit 7 6 5 4 3 2 1 0 MF=0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 MF=1 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 Feature Revision Identification Manufacturers Vendor Code Bit 15 14 13 12 11 10 9 8 MF=0 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 MF=1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 Feature RFU FIFO Depth Density CK# CK CMD BA0‐BA3 A2‐A5 A9,A10 A0,A1 A11 MRA MRA Code Code Code Code Code Code CodeCode tWRIDON(max) DQ tWRIDOFF(min) Vendor ID + Rev Code MRA = Mode Register Address; Code = Opcode to be loaded NOP MRS NOP NOP NOP NOP MRS NOP NOP NOP NOP Donʹt Care CodeCode

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 15 H5GQ1H24AFR 2. ADDRESS 2.1. ADDRESSING GDDR5 SGRAMs use a double data rate address scheme to reduce pins required on the GDDR5 SGRAM as shown in Table 5. The addresses should be provided to the GDDR5 SGRAM in two parts; the first half is latched on the rising edge of CK along with the command pins such as RAS#, CAS# and WE#; the second half is latched on the next rising edge of CK#. The use of DDR addressing allows all address values to be latched in at the same rate as the SDR com‐ mands. All addresses related to command access have been positioned for latching on the initial rising edge for faster decoding. Note: Address pin A12 is required only for 2G density. GDDR5 addressing includes support for 1G density. For all densities two modes are supported (x32 mode or x16 mode). x32 and x16 modes differ only in the number of valid column addresses, as shown in Table6. Table 5 Address Pairs Clock Rising CK BA3 BA2 BA1 BA0 (A12) A11 A10 A9 A8 Rising CK# A3 A4 A5 A2 (RFU) A6 A0 A1 A7 Table 6 Addressing Scheme x32 mode x16 mode Row address A0~A11 A0~A11 Column address A0~A5 A0~A6 Bank address BA0~BA3 BA0~BA3 Autoprecharge A8 A8 Page Size 2K 2K Refresh 8K/32ms 8K/32ms Refresh period 3.9us 3.9us

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 16 H5GQ1H24AFR 2.2. ADDRESS BUS INVERSION (ABI) Address Bus Inversion (ABI) reduces the power requirements on address pins, as the no. of address lines driving a low level can be limited to 4 (in case A12/RFU is not wired) or 5 (in case A12/RFU is wired). The Address Bus Inversion function is associated with the electrical signalling on the address lines between a controller and the GDDR5 SGRAM, regardless of whether the information conveyed on the address lines is a row or column address, a mode register op‐code, a data mask, or any other pattern. The ABI# input is an active Low double data rate (DDR) signal and sampled by the GDDR5 SGRAM at the rising edge of CK and the rising edge of CK# along with the address inputs. Once enabled by the corresponding ABI Mode Register bit, the GDDR5 SGRAM will invert the pattern received on the address inputs in case ABI# was sampled Low, or leave the pattern non‐inverted in case ABI# was sampled High, as shown in Figure 6. Figure 6: Example of Address Bus Inversion Logic 8 (9) 8 (9) to DRAM core ABI# Address Pins from Mode Register: 0 = enabled 1 = disabled Note: bus width is 8 when A12/RFU pin is not present, and 9 when A12/RFU pin is present

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 17 H5GQ1H24AFR The flow diagram in Figure 7 illustrates the ABI operation. The controller decides whether to invert or not invert the data conveyed on the address lines. The GDDR5 SGRAM has to perform the reverse operation based on the level of the ABI# pin. Address input timing parameters are only valid with ABI being enabled and a maximum of 4 address inputs driven Low. Figure 7: Address Bus Inversion (ABI) Flow Diagram Data to be sent on address lines ’0’ count > 4 ? ABI# = ’L’ Invert Yes ABI# = ’H’ Don’t invert No Determine ’0’ count Data received on address lines ABI# = ’H’ Don’t invert ABI# = ’L’ Invert Controller GDDR5 SGRAM

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 18 H5GQ1H24AFR 2.3. BANK GROUPS For GDDR5 SGRAM devices operating at frequencies above a certain threshold, the activity within a bank group must be restricted to ensure proper operation of the device. The 8 or 16 banks in GDDR5 SGRAMs are divided into four bank groups. The bank groups feature is controlled by bits A10 and A11 in Mode Register 3 (MR3). The assignment of the banks to the bank groups is shown in Table 7. These bank groups allow the specification of different command delay parameters depending on whether back‐to‐back accesses are to banks within one bank group or across bank groups as shown in Table 8. Table 7 Bank Groups Bank Addressing 1G BA3 BA2 BA1 BA0 16 banks 00000 Group A 10001 20010 30011 40100 Group B 50101 60110 70111 81000 Group C 91001 1 0 1010 1 1 1011 1 2 1100 Group D 1 3 1101 1 4 1110 1 5 1111

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 19 H5GQ1H24AFR Note.1 : Parameters tRTPS and tRTPL apply only when READ and PRECHARGE go to the same bank; use tRTPS when BG are disabled, and tRTPL when BG are enabled. Table 8 Command Sequences Affected by Bank Groups Command Sequence Corresponding AC Timing Parameter NotesBank Groups Disabled Bank Groups Enabled Accesses to different bank groups Accesses within the same bank group ACTIVE to ACTIVE t RRDS tRRDS tRRDL WRITE to WRITE t CCDS tCCDS tCCDL READ to READ t CCDS tCCDS tCCDL Internal WRITE to READ t WTRS tWTRS tWTRL READ to PRECHARGE t RTPS 1 tck t RTPL 1

Rev. 1.0 /Nov. 2009 20 H5GQ1H24AFR T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CLK CAS DQ A0 A1 B0 B1 C0 C1 A0 A1 B0 B1 C1 Example 1 (Bank Groups disabled): tCCDS = 2 * tCK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CLK CAS DQ A0 A1 A2 A3 A0 A1 A2 Example 2: (Bank Groups enabled): tCCDL = 4 * tCK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CLK CAS DQ A0 B0 A1 B1 C0 D0 A0 B0 A1 B1 C0 Example 3: (Bank Groups enabled): tCCDS = 2 * tCK T12 T12 T12 T13 T13 T13 C0 D0 D0 C1 Back-to-back column accesses based on tCCDL and tCCDS parameters. Notes: 1) Column accesses are to open banks, and tRCD has been met. 2) CL = 0 assumed 3) Ax, Bx, Cx, Dx: accesses to bank groups A, B, C or D, respectively 4) With bank groups enabled, tCCDL is 3tCK, as programmed in MR3.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 21 H5GQ1H24AFR 3. TRAINING 3.1. INTERFACE TRAINING SEQUENCE Due to the high data rates of GDDR5, it is recommended that the interfaces be trained to operate with the optimal timings. GDDR5 SGRAM has features defined which allow for complete and efficient training of the I/O interface without the use of the GDDR5 SGRAM array. The interface trainings are required for nor‐ mal DRAM functionality unless running in lower frequency modes as described in the low frequency sec‐ tion. Interface timings will only be guaranteed after all required trainings have been executed. A recommended order of training sequences has been chosen based on the following criteria: The address training must be done first to allow full access to the Mode Registers. (MRS for address train‐ ing is a special single data rate mode register set guaranteed to work without training). Address input tim‐ ing shall function without training as long as tAS/H are met at the GDDR5 SGRAM. WCK2CK training should be done before read training because a shift in WCK relative CK will cause a shift in all READ timings relative to CK. READ training should be done before WRITE training because optimal WRITE training depends on cor‐ rect READ data. Figure 8: Interface Training Sequence Initialization Address Training (optional) WCK2CK Alignment Training READ Training WRITE Training Start Normal Operation

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 22 H5GQ1H24AFR 3.2. ADDRESS TRAINING The GDDR5 SGRAM provides means for address bus interface training. The controller may use the address training mode to improve the timing margins on the address bus. Address training mode is entered and exited via the ADT bit in Mode Register 15 (MR15). Mode Register 15 supports the same setup and hold times on the address pins as for commands to allow a safe entry into address training mode. Address training mode uses an internal bridge between the GDDR5 SGRAM’s address inputs and DQ/ DBI# outputs. It also uses a special READ command for address capture that is encoded using the SDR command pins only (CS#,RAS#,CAS#,WE# = L,H,L,H). The address values normally used to encode the commands will not be interpreted. Once the address training mode has been entered, the address values registered coincident with this special READ command will be transmitted to the controller on the DQ/ DBI# pins. The controller is then expected to compare the address pattern received to the expected value and to adjust the address transmit timing accordingly. The procedure may be repeated using different address pattern and interface timings. No WCK clock is required for this special READ command operation during address training mode. The latched addresses are driven out asynchronously. The only commands allowed during address training mode are this special READ, MRS (e.g. to exit address training mode) and NOP / DESELECT. When enabled by the ABI bit in Mode Register 1, address bus inversion (ABI) is effective during address training mode. It is suggested to train the ABI# pin’s interface timing together with the other address lines. The timing diagram in Figure 9 illustrates the typical command sequence in address training mode. The DQ/DBI# output drivers are enabled as long as the ADT bit is set. The minimum spacing between consec‐ utive special READ commands is 2 tCK.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 23 H5GQ1H24AFR Figure 9: Address Training Timing Table 10 defines the correspondence between address bits and DQ/DBI#. Devices configured to x16 mode reflect the address on the two bytes being enabled in that mode, which are bytes 0 and 2 for MF=0 and bytes 1 and 3 for MF=1 configurations. Devices configured to x32 mode reflect the address on the same DQ as in x16 mode; in addition they are allowed but not required to reflect the address on those bytes that are disabled in x16 mode, thus reflecting each address twice. Devices not supporting an A12/RFU pin shall drive a logic High on the DBI# pins. Table 9 AC timings in Address Training Mode Parameter Symbol Min Max Unit READ command to data out delay tADR 0.5*tCK+0 0.5*tCK+10 ns ADT off to DQ/DBI# in ODT state delay t ADZ ‐‐ 0.5*tCK+10 ns CK# CK tADR Even DQ Notes: 1) READ command encoding: CS# = L, RAS# = H, CAS# = L, WE# = H 2) ADRxR = 1st half of address x, sampled on rising edge of CK; ADRxR# = 2nd half of address x, sampled on rising edge of CK# 3) Addresses sampled on rising edge of CK are returned on even DQ after tADR; addresses sampled on rising edge of CK# are returned on odd DQ simultaneously with even DQ 4) DQs are enabled when ADT bit in Mode Register 15 set to 1 (Enter Address Training Mode) DQs are disabled after tADZ when ADT bit in Mode Register 15 set to 0 (Exit Address Training Mode) ADRx CMD ADDR ADRy R ADRy Odd DQ tADRtMRD MR15 A10=1 ADRx R Donʹt Care ADRx R ADRy R ADRx ADRy ADRz R ADRz R ADRz tADR MR15 A10=0 tADZ ADRz MRS NOP READ (*) NOP READ (*) NOP READ (*) NOP MRS NOP NOP NOP NOP

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 24 H5GQ1H24AFR Table 10 Address to DQ Mapping in Address Training Mode Output Address bits registered at rising edge of CK A12 A8 A11 BA1 BA2 BA3 BA0 A9 A10 DQ DBI0# DQ22 DQ20 DQ18 DQ16 DQ6 DQ4 DQ2 DQ0 DBI1# DQ30 DQ28 DQ26 DQ24 DQ14 DQ12 DQ10 DQ8 Output Address bits registered at rising edge of CK# RFU A7 A6 A5 A4 A3 A2 A1 A0 DQ DBI2# DQ23 DQ21 DQ19 DQ17 DQ7 DQ5 DQ3 DQ1 DBI3# DQ31 DQ29 DQ27 DQ25 DQ15 DQ13 DQ11 DQ9

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 27 H5GQ1H24AFR Figure 12: EDC pin Behaviour for WCK2CK Training (assumes ‘1111’ as EDC Hold Pattern) The ideal alignment is indicated by the phase detector output transitioning from “early” to “late” when the delay of the WCK phase is continuously increased. The WCK phase range for ideal alignment is speci‐ fied by the parameter tWCK2CKPIN ; the value(s) vary with the PLL mode (on or off) and the selected align‐ ment point. If enabled, the PLL shall not interfere in the behavior of the WCK2CK training. Significantly moving the phase and/or stopping the WCK during training may disturb the PLL. It is required to perform a PLL reset after the WCK2CK training has determined and selected the proper alignment between WCK and CK clocks. The PLL lock time tLK must be met before exiting WCK2CK training to guarantee that the PLL is in lock such that the GDDR5 SGRAM data synchronizers are set upon WCK2CK training exit. WCK2CK training is exited via MRS by resetting bit A4 in MR3. For proper reset of the data synchronizers it is required that the WCK and CK clocks are aligned within tWCK2CKSYNC at the time of the WCK2CK training exit. Table 11 Phase Detector and EDC Pin behavior WCK/2 value sampled by CK WCK2CK Phase Data on EDC Pin Action ‘1’ ‘Early’ EDC hold (‘1111’) Increase Delay on WCK ‘0’ ‘Late’ Inverted EDC Hold (‘0000’) Decrease Delay on WCK xEDC0 CK WCK01/2 WCK23/2 (internal) x x x x x x x x x x x x x xEDC2 ‐ tWCK2CK tWCKTPH WCK Early EDC0 WCK01/2 WCK23/2 (internal) x x x x x x x x x x x x x x xEDC2 + tWCK2CK tWCKTPH WCK Late 1 1 1 1 0 0 0 0 EDC0 WCK01/2 WCK23/2 (internal) x x x x x x x x x x x x x x xEDC2 tWCKTPH 3 x x x xAligned Late Early ~~~~

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 29 H5GQ1H24AFR Also, this mode works for both normal and PIN mode. When WCK2CK automatic synchronization mode is enabled, a full WCK2CK training including Phase search is not required after power‐down exit, although WCK2CK MRS must be issued momentarily for setting the data synchronizers. However, WCK and CK clocks must meet the tWCK2CKSYNC specification upon power‐down exit. Any allowed command may be issued after tXPN or after tLK in case the PLL had been enabled upon power‐down entry. The PLL sequence is not affected by this mode. The use of WCK2CK automatic synchronization mode is restricted to lower operating frequencies up to fCKAUTOSYNC as described in the datasheets. Table 12 describes WCK2CK training methods for different frequency ranges. Each Frequency range is vendor specific. Normal and PIN mode of WCK2CK training are described in Table 12. Each frequency range is DRAM vendor specific. Divider initialization can be done by training with WCK2CK inversion, WCK2CK stopping, or WCK2CK auto‐sync. If the user wants to use WCK2CK stop for divider initializa‐ tion instead of WCK2CK auto‐sync, the user must not set the WCK2CK auto‐sync. Low frequency, the combined use of PIN and WCK2CK auto‐sync modes can minimize WCK2CK training time. * Note: The divided WCK/WCK# should be aligned CK/CK# by WCK2CK Auto Synchronization or WCK stop mode The following examples describe the WCK2CK training in more detail. Example 1: outline of a basic WCK2CK training sequence without WCK clock stop: 1) Enable training mode via MRS and wait tMRD 2) Sweep and observe the phase independently for WCK01 on EDC0 and WCK23 on EDC2; in case the internal divide‐by‐2 circuits are at opposite phase use either the WCK01 or WCK23 inversion bit to flip one of the WCK divide‐by‐2 circuits 3) Adjust the WCK phase independently for WCK01 and WCK23 to the optimal point (“ideal alignment”) 4) Issue a PLL reset and wait for tLK (PLL on mode only) 5) While all WCK and CK are aligned, exit WCK2CK training mode via MRS 6) Wait tMRD for the reset of data synchronizers Table 12 WCK2CK training simplified for Normal mode and PIN mode High Frequency Low Frequency Frequency ≥ 2Gbps ＜ 2Gbps WCK2CK alignment mode Normal PIN Normal PIN Phase Search Required Required No* No*

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 30 H5GQ1H24AFR Example 2: outline of a basic WCK2CK training sequence with optional WCK clock stop: 1) Stop WCK clocks with WCK01/WCK23 LOW and WCK01#/WCK23# HIGH 2) Wait tWCK2MRS for internal WCK clocks to settle 3) Enable training mode via MRS and wait tMRD for divide‐by‐2 circuits to reset 4) Start WCK clocks without glitches (both divide‐by‐2 circuits remain in sync) 5) Wait tWCK2TR for internal WCK clocks to stabilize 6) Sweep and observe the phase independently for WCK01 on EDC0 and WCK23 on EDC2; adjust the WCK phase to the optimal point (“ideal alignment”) 7) Issue a PLL reset and wait tLK (PLL on mode only) 8) While all WCK and CK are aligned, exit WCK2CK training mode via MRS 9) Wait tMRD for the reset of data synchronizers READ and WRITE latency timings are defined relative to CK. Any offset in WCK and CK at the pins and/ or the phase detector will be reflected in the latency timings. The parameters used to define the relation‐ ship between WCK and CK are shown in Figure 6. For more details on the impact on READ and WRITE timings see the OPERATIONS section. Figure 15: WCK2CK Timings CK CK# tCH tCLtCK WCK WCK# tWCK2CKPIN Case 1: Negative tWCK2CKPIN; tWCK2CK = 0 (ideal WCK2CK alignment) tWCK WCK WCK# Case 2: Negative tWCK2CKPIN; negative tWCK2CK WCK WCK# tWCK2CKPIN Case 3: Positive tWCK2CKPIN; tWCK2CK = 0 (ideal WCK2CK alignment) tWCK2CKPIN + tWCK2CK WCK# WCK Case 4: Positive tWCK2CKPIN; positive tWCK2CK tWCK2CKPIN + tWCK2CK Note: tWCK2CKPIN and tWCK2CK parameter values could be negative or positive numbers, depending on the selected WCK2CK alignment point, PLL‐on‐or PLL‐off mode operation and design implementation. They also vary across PVT. WCK2CK training is required to determine the correct WCK‐to‐CK phase for stable device operation. tWCKH tWCKL

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 31 H5GQ1H24AFR GDDR5 WCK2CK Training in x16 mode For configurations with WCK clocks not shared between two GDDR5 SGRAMs it is suggested to set the WCK phase to the ideal alignment point. However, for configurations where two GDDR5 SGRAMs (x16) share their WCK clocks as in a x16 clamshell, an offset given by the midpoint of both DRAM’s ideal WCK positions may be required. The maximum allowed offset in this case is specified by parameter tWCK2CKSYNC: it defines the WCK offset range from the ideal alignment which still guarantees a GDDR5 SGRAM device to internally synchronize its WCK and CK clocks upon training exit. Example: outline of training sequence for x32 and x16 configurations with 2 GDDR5 SGRAMs sharing their WCK clocks (e.g. clamshell): 1) Enable training mode for both DRAMs via MRS and wait tMRD 2) For both DRAMs sweep and observe the phase independently for WCK01 on EDC0 and WCK23 on EDC2; in case the internal divide‐by‐2 circuits are at opposite phases use either the WCK01 or WCK23 inversion bit to flip one of the WCK divide‐by‐2 circuits; in case of shared CS# signals use MREMF0 and MREMF1 bits in MR15 to explicitly direct the MRS command for this phase flipping to either DRAM1 or DRAM2 (“soft chip select”); 3) Sweep and observe the phase on DRAM1 independently for WCK01 on EDC0 and WCK23 on EDC2; store the setting for the optimal WCK phase 4) Sweep and observe the phase on DRAM2 independently for WCK01 on EDC0 and WCK23 on EDC2; store the setting for the optimal WCK phase 5) Sweep WCK01 and WCK23 phase to midpoint of DRAM1 and DRAM2 optimal settings 6) Issue a PLL reset and wait for tLK (PLL on mode only) 7) While all WCK and CK are aligned, exit WCK2CK training mode via MRS 8) Wait tMRD for the reset of data synchronizers

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 32 H5GQ1H24AFR 3.4. READ TRAINING Read training allows the memory controller to find the data‐eye center (symbol training) and burst frame location (frame training) for each high‐speed output of the GDDR5 SGRAM. Each pin (DQ0‐DQ31, DBI0#‐ DBI3#, EDC0‐EDC3) can be individually trained during this sequence. For Read Training the following conditions must be true:

• a t least one bank is active, or an auto refresh must be in progress and bit A2 in Mode Register 5 (MR5) is set to 0 to allow training during auto refresh (to disable this special REF enabling of the WCK clock tree an ACT command must be issued, or the device must be set into power‐down or self refresh mode)
• W C K 2 C K training must be complete
• t h e PLL must be locked, if enabled
• R D B I and WDBI must be enabled prior to and during Read Training if the training shall include the DBI# pins. RDCRC and WRCRC must be enabled prior to and during Read Training if the training shall include the EDC pins. The following commands are associated with Read Training:
• L D F F to preload the Read FIFO;
• R D T R to read a burst of data directly out of the Read FIFO. Neither LDFF nor RDTR access the memory core. No MRS is required to enter Read Training. Figure 16 shows an example of the internal data paths used with LDFF and RDTR. Table 13 lists AC timing parameters associated with Read Training. Table 13 LDFF and RDTR TIMINGS PARAMETER SYMBOL VALUES UNIT NOTES MIN MAX ACTIVE to LDFF command delay t RCDLTR 10 – ns ACTIVE to RDTR command delay t RCDRTR 10 – ns REFRESH to RDTR or WRTR command delay t REFTR 10 – ns RDTR to RDTR command delay t CCDS 2– t CK LDFF to LDFF command cycle time t LTLTR 4– t CK LDFF(111) to LDFF command cycle time t LTL7TR 4– t CK a a. The min. value does not exceed 8 tCK. LDFF(111) to RDTR command delay t LTRTR 4– t CK READ or RDTR to LDFF command delay t RDTLT 4– t CK

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 33 H5GQ1H24AFR Figure 16: Data Paths used for Read and Write Training LDFF Command The LDFF command (Figure 17) is used to securely load data to the GDDR5 SGRAM Read FIFOs via the address bus. Depending on the GDDR5 SGRAM READ FIFO depth nFIFO 6, any bit pattern of length 32‐ 48 can be loaded uniquely to every DQ, DBI# and EDC pin within a byte. The FIFO depth is fixed by design and can be read via the Vendor ID function. Eight LDFF commands are required to fill one FIFO stage; each LDFF command loads one burst position, and the bank addresses BA0‐BA2 select the burst position from 0 to 7. The data pattern is conveyed on address pins A0‐A7 for DQ0‐DQ7, A9 for DBI0#, and BA3 for EDC0; the data are internally replicated to all 4 bytes, as shown in Figure 18. WRTR strobe (CK domain) WRTR FIFO 6 × 72=432 bits per byte RDTR strobe (WCK) Reverse DBI DRAM Core WRTR output pointer input pointer DQ0‐DQ7 DBI0# EDC0 e.g. 500Mbps DBI e.g. 4Gbps e.g. 500Mbps RDTR strobe (WCK) LDFF ADDR DEMUX LDFF BA0‐BA2 Notes: 1) FIFO depth of 5 shown; supported FIFO depths: 4, 5 or 6 2) data paths shown for 1 of 4 bytes (byte 0) Address Path 4321043210 output pointer input pointer 4321043210 88:1TX Parallel to Serial Converter Serial to Parallel Converter 728:1RX 8:1 Parallel to Serial Converter CRC strobe LDFF strobe (burst 7) WRTR strobe LDFF strobe (burst 7) M U X M U X M U X DQ M U X CRC8 RX Data path used with RDTR Data path used with WRTR M U X 0 1 2 3 4 5 67 CRC FIFO 6 × 8 =48 bits per byte Data path used with LDFF Data path used with LDFF/WRTR TX

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 34 H5GQ1H24AFR LDFF loads the DBI FIFO regardless of the WDBI and RDBI Mode Register bits. It also loads the EDC FIFO regardless of the WRCRC and RDCRC Mode Register bits, and no CRC is calculated; however, RDBI and RDCRC must be enabled to read the DBI and EDC bits, respectively, with the RDTR command. Figure 17: LDFF Command CS# WE# CAS# RAS# CKE# LOW LDFF CK CK# A9, BA3 A1, A3 A8,A10,A11 BA0‐BA2 A2, A4,A5 0,0,1A0,A7,A6 DATA DATA DATA DATA DATA = FIFO data BP BP = Burst Position

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 35 H5GQ1H24AFR Figure 18: LDFF Command Address to DQ/DBI#/EDC Mapping All burst addresses 0 to 7 must be loaded; LDFF commands to burst address 0 to 6 may be issued in ran‐ dom order; the LDFF command to burst address 7 (LDFF7) must be the last of 8 consecutive LDFF com‐ mands, as it effectively loads the data into the FIFO and results in a FIFO pointer increment. Consecutive LDFF commands have to be spaced by at least tLTLTR, and at least tLTL7TR cycles are required after each LDFF command to burst address 7. LDFF pattern may efficiently be replicated to the next FIFO stages by issuing consecutive LDFF commands to burst address 7 (with identical data pattern). The data pattern in the scratch memory for LDFF will be available until the first RDTR command. The DQ/DBI# output buffers remain in ODT state during LDFF. An amount of LDFF commands to burst address 7 greater than the FIFO depth is allowed and shall result in a looping of the FIFO’s data input. The total number of LDFF commands to burst address 7 modulo FIFO depth must equal the total number of RDTR commands modulo FIFO depth when used in conjunction with RDTR. No READ or WRITE com‐ mands are allowed between LDFF and RDTR. The EDC hold pattern is driven on the EDC pins during LDFF (provided RDQS mode is not enabled). A10 A11 BA1

1 FIFO STAGE = 1 BURST

H L Burst Position BA2 BA1 BA0 CK LDFF FIFO Load Pulse L LDFF Command CK# Address‐to‐DQ Mapping BA3 BA3 DBI0# DBI1# DBI2# DBI3# EDC0 EDC1 EDC2 EDC3 DQ7 DQ15 DQ23 DQ31 DQ6 DQ14 DQ22 DQ30 DQ5 DQ13 DQ21 DQ29 DQ4 DQ12 DQ20 DQ28 DQ3 DQ11 DQ19 DQ27 DQ2 DQ10 DQ18 DQ26 DQ1 DQ9 DQ17 DQ25 DQ0 DQ8 DQ16 DQ24 Byte 0B y t e 1B y t e 2 Byte 3 A2BA0 BA2

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 36 H5GQ1H24AFR RDTR Command A RDTR burst is initiated with a RDTR command as shown in Figure 19. No bank or column addresses are used as the data is read from the internal READ FIFO, not the array. The length of the burst initiated with a RDTR command is eight. There is no interruption nor truncation of RDTR bursts. Figure 19: RDTR Command A RDTR command may only be issued when a bank is open or a refresh is in progress and bit A2 in MR5 is set to 0 to allow training during refresh. RDBI and RDCRC must be enabled to read the DBI and EDC bits, respectively, with the RDTR command. If not set, the DBI# pins will remain in ODT state, and the EDC pins will drive the EDC hold pattern. In case of the RDQS mode, the EDC pin functions like with a normal READ in this mode. The DBI# pin behaves like a DQ, and no encoding with DBI is performed. An amount of RDTR commands greater than the FIFO depth is allowed and shall result in a looping of the FIFO’s data output. The FIFO depth from which the RDTR data is read must be a number between 4‐6 and must be specified by the DRAM vendor. The FIFO depth is read via the Vendor ID function. During RDTR bursts, the first valid data‐out element will be available after the CAS latency (CL). The latency is the same as for READ. The data on the EDC pins comes with additional CRC latency (tCRCRD) after the CL. Upon completion of a burst, assuming no other RDTR command has been initiated, all DQ and DBI# pins will drive a value of ʹ1ʹ and the ODT will be enabled at a maximum of 1 tCK later. The drive value and ter‐ mination value may be different due to separately defined calibration offsets. If the ODT is disabled, the pins will drive Hi‐Z. CS# WE# CAS# RAS# CKE# A9 (A12) A8,A10,A11 BA0‐BA3 A2‐A5 LOW RDTR CK CK# 0,1,1 A7,A0,A6

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 37 H5GQ1H24AFR Data from any RDTR burst may be concatenated with data from a subsequent RDTR command. A contin‐ uous flow of data can be maintained. The first data element from the new burst follows the last element of a completed burst. The new RDTR command should be issued after the first RDTR command according to the tCCDS timing. A WRTR can be issued any time after a RDTR command as long as the bus turn around time tRTW is met. The total number of RDTR commands modulo FIFO depth must be equal to total number of WRTR com‐ mands modulo FIFO depth when used in conjunction with WRTR. No READ or WRITE commands are allowed between WRTR and RDTR. The total number of RDTR commands modulo FIFO depth must be equal to the total number of LDFF commands to burst position 7 modulo FIFO depth when used in conjunction with LDFF. No READ or WRITE commands are allowed between LDFF and RDTR.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 38 H5GQ1H24AFR 3.5. WRITE TRAINING Write training allows the memory controller to find the data‐eye center (symbol training) and burst frame location (frame training) for each high‐speed input of the GDDR5 SGRAM. Each pin (DQ0‐DQ31, DBI0#‐ DBI3#) can be individually trained during this sequence. For Write Training the following conditions must be true:

• a t least one bank is active, or an auto refresh must be in progress and bit A2 in Mode Register 5 (MR5) is set to 0 to allow training during auto refresh (to disable this special REF enabling of the WCK clock tree an ACT command must be issued, or the device must be set into power‐down or self refresh mode)
• t h e PLL must be locked, if enabled.
• W C K 2 C K training should be complete
• Read training should be complete
• R D B I and WDBI must be enabled prior to and during Write Training if the training shall include the DBI# pins. RDCRC and WRCRC must be enabled prior to and during Write Training if the training shall include the EDC pins. The following commands are associated with Write Training:
• W R T R to write a burst of data directly into the Read FIFO;
• R D T R to read a burst of data directly out of the Read FIFO. Neither WRTR nor RDTR access the memory core. No MRS is required to enter Write Training. Figure 16 shows an example of the internal data paths used with WRTR and RDTR. Figure 21 shows a typ‐ ical Write training command sequence using WRTR and RDTR. Table 14 lists AC timing parameters asso‐ ciated with WRITE Training. Table 14 WRTR and RDTR Timings PARAMETER SYMBOL VALUES UNIT NOTES MIN MAX ACTIVE to WRTR command delay t RCDWTR 10 – ns ACTIVE to RDTR command delay t RCDRTR 10 – ns REFRESH to RDTR or WRTR command delay t REFTR 10 – ns RD/WR bank A to RD/WR bank B command delay different bank groups tCCDS 2– t CK a a. t CCDS is either for gapless consecutive READ or RDTR (any combination), gapless consecutive WRITE, or gapless consecutive WRTR commands. WRTR to RDTR command delay t WTRTR WL‐tWLmin – t CK WRITE to WRTR command delay t WRWTR WL+CRCWL+2 – t CK READ or RDTR to WRITE or WRTR command delay t RTW 1– n s b b. t RTW is not a device limit but determined by the system bus turnaround time. The difference between tWCK2DQO and tWCK2DQI shall be considered in the calculation of the bus turnaround time.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 39 H5GQ1H24AFR WRTR Command A WRTR burst is initiated with a WRTR command as shown in Figure 20. No bank or column addresses are used as the data is written to the internal READ FIFO, not the array. The length of the burst initiated with a WRTR command is eight. There is no interruption nor truncation of WRTR bursts. Figure 20: WRTR Command A WRTR command may only be issued when a bank is open or a refresh is in progress and bit A2 in MR5 is set to 0 to allow training during refresh. WDBI and WRCRC must be enabled to write the DBI and EDC bits, respectively, with the WRTR com‐ mand. If WDBI is not set, a ‘1’ will be written to the DBI FIFO, and a ‘1’ will be assumed for the DBI# input in the CRC calculation. In contrast to a normal WRITE, no CRC is returned by the WRTR command and the EDC pins will drive the EDC hold pattern. In case of the RDQS mode, the EDC pin functions like with a normal READ in this mode. Please note that RDCRC must be enabled to read the calculated CRC data with the RDTR command. An amount of WRTR commands equal to the FIFO depth is required to fully load the FIFO; any number of WRTR commands greater than the FIFO depth is allowed and shall result in a looping of the FIFO’s data input. The FIFO depth to which the WRTR data is written must be 6. The FIFO depth is read via the Ven‐ dor ID function. During WRTR bursts, the first valid data‐in element must be available at the input latch after the Write Latency (WL). The Write Latency is the same as for WRITE. Upon completion of a burst, assuming no other WRTR data is expected on the bus the GDDR5 SGRAM DQ and DBI# pins will be driven according to the ODT state. Any additional input data will be ignored. WRTR CS# WE# CAS# RAS# CKE# LOW CK CK# A9 (A12) A8,A10,A11 BA0‐BA3 A2‐A5 0,1,1A7,A0,A6

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 40 H5GQ1H24AFR Data from any WRTR burst may be concatenated with data from a subsequent WRTR command. A contin‐ uous flow of data can be maintained. The first data element from the new burst follows the last element of a completed burst. The new WRTR command should be issued after the previous WRTR command according to the tCCDS timing. A RDTR can be issued any time after a WRTR command as long as the internal bus turn around time tRTWTR is met. The total number of WRTR commands modulo FIFO depth must equal the total number of RDTR com‐ mands modulo FIFO depth when used in conjunction with RDTR. No READ or WRITE commands are allowed between WRTR and RDTR. Figure 21: Write Training using WRTR and RDTR Commands CK# CK CMD WLmrs DQ NOPWRTR 1. WLmrs, CLmrs and CRCRL set to 1 for ease of illustration; check Mode Register definition for supported settings WRTR ADDR T0 T1 T2 T3 T4 T5 Ta Ta+1 Ta+2 Ta+3 Ta+4 NOP NOP NOP RDTR NOP RDTR NOP NOP WCK WCK# EDC D7EDC HoldEDC HoldEDC HoldEDC Hold EDC HoldEDC HoldEDC Hold EDC Hold Donʹt Care WLmrs CLmrs CRCRL CLmrs CRCRLtWTRTR 2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

responsability for use of circuits described. No patent licenses are implied. gramming the Mode Registers will not alter the contents of the memory array. requirements will result in unspecified operation. isters to the desired values e.g. upon power-up. is not defined for 1G density. Figure 22. Mode Registers Overview

responsability for use of circuits described. No patent licenses are implied.

00000 W r i t e Recovery (WR) TM CAS Latency (CLmrs) Write Latency

000 R F U

Figure 23. Mode Register 0 (MR0) Definition

Rev. 1.0 /Nov. 2009 43 H5GQ1H24AFR WRITE Latency (WLmrs) The WRITE latency (WLmrs) is the delay in clock cycles used in the calculation of the total WRITE latency (WL) between the registration of a WRITE command and the availability of the first piece of input data. DRAM vendor specifications should be checked for value(s) of WLmrs supported. The full WRITE latency definition can be found in the section entitled OPERATION. receivers turn on when the WRITE command is registered. Refer to vendor datasheets for value(s) of WLmrs where the input receivers are always on or only turn on when the WRITE command is registered Speed Allowable Operating Frequency (Gbps) WL7 WL6 WL5 WL4 WL3 WL2 WL1 6.0Gbps 5.5Gbps 5.0Gbps 4.5Gbps 4.0Gbps CAS Latency (CLmrs) The CAS latency (CLmrs) is the delay in clock cycles used in the calculation of the total READ latency (CL) between the registration of a READ command and the availability of the first piece of output data. By default CLmrs is specified by bits A3‐A6, defining a CLmrs range of 5 to 20 tCK. DRAM vendor specifications should be checked for value(s) of CLmrs supported. The full READ latency definition can be found in the section entitled OPERATION Speed RDBI ON/OFF Allowable Operating Frequency (Gbps) CL20 CL19 CL18 CL17 CL16 CL15 CL14 CL13 CL12 6.0Gbps OFF ON 5.5Gbps OFF ON 5.0Gbps OFF ON 4.5Gbps OFF ON 4.0Gbps OFF ON

Rev. 1.0 /Nov. 2009 44 H5GQ1H24AFR WRITE Recovery (WR) The programmed WR value is used for the auto precharge feature along with tRP to determine tDAL. The WR register bits are not a required function and may be implemented at the discretion of the DRAM manufacturer. WR must be programmed with a value greater than or equal to RU{tWR/tCK}, where RU stands for round up, tWR is the analog value from the vendor datasheet and tCK is the operating clock cycle time. By default WR is specified by bits A8‐A11, defining a WR range of 4 to 19 tCK. Test Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to ’0’, and bits A0‐A6 and A8‐A11 set to the desired values. Programming bit A7 to ‘1’ places the device into a test mode that is only to be used by the DRAM manufacturer. No functional operation is specified with test mode enabled.

responsability for use of circuits described. No patent licenses are implied. Read DBI, Write DBI, ABI, control of calibration updates and PLL as shown in Figure 24. and BA3=0. Bits A0‐A1, A4‐A6 and A10 of this register are initialized with’0’s. Figure 24. Mode Register 1 (MR1) Definition

00 Auto Calibration On

01 R F U

11 R F U

00010 PLL

00 D i s a b l e d

01 Z Q / 2

10 Z Q

11 D i s a b l e d

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 46 H5GQ1H24AFR value of 120 Ohms is equivalent to the 40 Ohms Pulldown and 60 Ohms Pullup nominal impedances of GDDR5 SGRAMs. RESET#, CK and CK# are not internally terminated. CK and CK# shall be terminated on the system using external 1% resistors to VDDQ. The output driver and on‐die termination impedances are updated during all REFRESH commands to compensate for variations in supply voltage and temperature. The impedance updates are transparent to the system. Driver Strength Bits A0 and A1 define the driver strength. The Auto Calibration setting enables the Auto‐Calibration functionality for the Pulldown, Pullup and Termination over process, temperature and voltage changes. The design target for the factory setting is 40 Ohm Pulldown, 60 Ohm Pullup driver strength with nominal process, voltage and temperature conditions. The nominal option enables the factory setting for the Pulldown, Pullup driver strength and termination. With this option enabled, driver strength and termination are expected to change with process, voltage and temperature. AC timings are only guaranteed with Auto Calibration. Data Termination Bits A2 and A3 define the data termination value for the on‐die termination (ODT) for the DQ and DBI# pins in combination with the driver strength setting. The termination can be set to a value of ZQ/2 which is intended for a single loaded system, or ZQ which is intended for a weaker termination used in a lower power or frequency applications. The data termination may also be turned off. ADR/CMD Termination Bits A4 and A5 define the address/command termination. The default setting (’00’) provides that the address/command termination is determined by latching CKE# on the rising edge of RESET#. The address/command termination can also be set to a value of ZQ/2 which is intended for a single loaded system, or ZQ which is intended for double loaded configurations with two devices sharing a common address/command bus. The address/command termination may also be turned off.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 47 H5GQ1H24AFR Calibration Update The Calibration Update setting enables the calibration value to be updated automatically by the auto calibration engine. The function is enabled upon power‐up to reduce update induced jitter. The user may decide to suppress updates from the auto calibration engine by disabling Calibration Update (A6=1). The calibration updates can occur with any REFRESH command. The update is not complete for a time tKO after the latching of the REFRESH command. During this tKO time, only NOP or DESELECT commands may be issued PLL and PLL Reset If a PLL is to be used, it must be enabled for normal operation by setting bit A7 to ’1’. A PLL reset is done by turning the PLL off then on, or by use of the PLL Reset bit A11. The PLL Reset bit is self clearing meaning that it returns back to the value ‘0’ after the PLL reset function has been issued. RDBI and WDBI Bit A8 controls Data Bus Inversion (DBI) for READs (RDBI), and bit A9 controls Data Bus Inversion for WRITEs (WDBI). For more details on DBI see READ and WRITE Data Bus Inversion (DBI) in the section entitled OPERATION. ABI Address Bus Inversion (ABI) is selected independently from DBI using bit A10. When enabled any data sent over the address bus (whether opcode, addresses, LDFF data or DM) is inverted or not inverted based on the state of ABI# signal. For more details on ABI see Address Bus Inversion (ABI) in the section entitled OPERATION.

responsability for use of circuits described. No patent licenses are implied. Mode Register 2 defines the output driver (OCD) and termination offsets as shown in Figure 25. Figure 25. Mode Register 2 (MR2) Definition

00100 ADR/CMD

responsability for use of circuits described. No patent licenses are implied. the termination value will be decreased. IV curves and AC timings are only guaranteed with zero offset. Figure 26. Impedance Offsets

responsability for use of circuits described. No patent licenses are implied. DRAM Info and WCK2CK training as shown in Figure 27. Figure 27. Mode Register 3 (MR3) Definition The refresh interval in self refresh mode may be set to 32ms, 16ms and 8ms. sequence, see the section on TRAINING.

11 RFU

00110 Bank

01 V e n d o r ID

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 51 H5GQ1H24AFR WCK01 / WCK23 Inversion Bits A2 and A3 control whether the internal phase of the WCK01 and WCK23 clock inputs after internal divide‐by‐2 shall be inverted, corresponding to a 2 U.I. phase shift. The bits are used in conjunction with WCK2CK training mode. RDQS Mode Bit A5 enables the RDQS mode of the GDDR5 SGRAM. In this mode the EDC pins will act as a READ strobe (RDQS). No CRC is supported in RDQS mode, and all related bits in MR4 will be ignored. A detailed description of the RDQS mode can be found in the section entitled OPERATION. DRAM Info Bits A6 and A7 enable the DRAM Info mode which is provided to output the Vendor ID, or the current junction temperature. The Vendor ID identifies the manufacturer of the GDDR5 SGRAM, and provides the die revision, memory density and FIFO depth. The Temperature Readout provides the SGRAM’s junction temperature. The on‐chip temperature sensor is enabled in advance by bit A6 in MR7. WCK Termination Bits A8 and A9 define the termination value for the on‐die termination (ODT) for the WCK01, WCK01#, WCK23 and WCK23# pins in combination with the driver strength setting. The termination can be set to a value of ZQ/2 which is intended for a single loaded system, or ZQ which is intended for double load configurations with two devices sharing the WCK clocks. The WCK termination may also be turned off. Bank Groups Bit A11 enables the bank groups feature. With A11 set to ‘1’, the bank groups feature is enabled and tCCDL is 3tCK.

responsability for use of circuits described. No patent licenses are implied. and BA3=0. Bits A0‐A3 (EDC Hold Pattern) of this register are initialized with ’1111’. Figure 28. Mode Register 4 (MR4) Definition output timing is the same as of a READ burst. those bursts, provided CRC is enabled for those bursts.

0000 P a t t e r n

1111 P a t t e r n

01000 EDC

000 N / A

0 EDC hold pattern not

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 53 H5GQ1H24AFR The EDC hold pattern will not be transmitted when the device is in address training mode, in WCK2CK training mode, in RDQS mode, in self refresh mode, in reset state, in power‐down state with the LP2 bit set, or in scan mode. With register bit A11 set High, EDC1 and EDC3 will transmit the inverted EDC hold pattern, resulting in a pseudo‐differential pattern. Please note that this function is not available in x16 configuration. Bit A11 is ignored for READ, WRITE and RDTR CRC bursts and the clock phase information in WCK2CK training mode. CRC Write Latency (CRCWL) The value of the CRC write latency is loaded into register bits A4‐A6. If the DRAM vendor does not support the Mode Register definition of CRCWL, the Mode Register settings will be ignored. In that case the valid fixed latency is given with the DRAM vendor’s specification. The user must set the CRCWL Mode Register bits. Speed Allowable Operating Frequency (Gbps) CRCWL14 CRCWL13 CRCWL12 CRCWL11 CRCWL10 CRCWL9 CRCWL8 6.0Gbps 5.5Gbps 5.0Gbps 4.5Gbps 4.0Gbps CRC Read Latency (CRCRL) The value of the CRC read latency is loaded into register bits A7‐A8. If the DRAM vendor does not support the Mode Register definition of CRCRL, the Mode Register settings will be ignored. In that case the valid fixed latency is given with the DRAM vendor’s specification. The user must set the CRCRL Mode Register bits. Speed RDBI ON/OFF Allowable Operating Frequency (Gbps) CRCRL3 CRCRL2 CRCRL1 CRCRL0 6.0Gbps OFF ON 5.5Gbps OFF ON 5.0Gbps OFF ON 4.5Gbps OFF ON 4.0Gbps OFF ON

Rev. 1.0 /Nov. 2009 54 H5GQ1H24AFR Read CRC Bit A9 controls the CRC calculation for READ bursts. When enabled, the calculated CRC pattern will be transmitted on the EDC pins with the latency as programmed in the CRCRL field of this register. With Read CRC being off, no CRC will be calculated for READ bursts, and the EDC hold pattern will be transmitted instead. Write CRC Bit A10 controls the CRC calculation for WRITE bursts. When enabled, the calculated CRC pattern will be transmitted on the EDC pins with the latency as programmed in the CRCWL field of this register. With Write CRC being off, no CRC will be calculated for WRITE bursts, and the EDC hold pattern will be trans‐ mitted instead.

responsability for use of circuits described. No patent licenses are implied. Mode Register 5 defines digital RAS, PLL band‐width and low power modes as shown in Figure 29. Figure 29. Mode Register 5 (MR5) Definition

01010 R F U P L L Bandwidth LP3 LP2 RFU

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 56 H5GQ1H24AFR Low Power Modes (LP2, LP3) Bits A1‐A2 control several low power modes of the GDDR5 SGRAM. The modes are independent of each other. When bit A1 (LP2) is set, the WCK receivers may be turned off during power‐down. When bit A2 (LP3) is set, RDTR, WRTR and LDFF commands are not allowed while a REF command is being executed. PLL Bandwidth The PLL bandwidth may optionally be configured to match system characteristics. Each setting defines a unique combination of ‐3dB corner frequency, peaking frequency and peaking magnitude.

responsability for use of circuits described. No patent licenses are implied. source, level, offsets, VREFD Merge and VREFD Auto Calibration mode, as shown in Figure 30. Figure 30. Mode Register 6 (MR6) Definition

01100 VREFD Offset

0 PD inside

responsability for use of circuits described. No patent licenses are implied. separate VREFD pins for the required external Vref. configured with bits A1‐A3 and bit A7 in MR7 all set to ’0’. Figure 31. VREFD Options Low, and the EDC pins will resume transmitting the EDC hold pattern. offset step values may be non‐linear and will vary across PVT.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 59 H5GQ1H24AFR The vendors may optionally support the offset capability to be applied to the external Vref (not shown in Figure 31). The optional Auto setting for VREFD enables the GDDR5 SGRAM to search for its own optimal internal Vref. There is no offset from this internally determined value (see also Auto VREFD Training).

responsability for use of circuits described. No patent licenses are implied. VDD Range and DCC as shown in Figure 32. Figure 32. Mode Register 7 (MR7) Definition

01 D C C start

10 D C C reset l

01110 D C C R F U Half

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 61 H5GQ1H24AFR Data Preamble When enabled by bit A5, non‐gapless READ bursts will be preceded by a fixed data preamble on the DQ and DBI# pins of 4 U.I. duration. The programmed READ latency does not change when the Data Preamble is enabled. The pattern is not encoded with RDBI, however, if RDBI is disabled, the DBI# pins will not toggle and drive a HIGH. Temperature Sensor The on‐chip temperature sensor is enabled by bit A6. A detailed description of the Temperature Sensor can be found in the VENDOR ID, TEMP SENSOR and SCAN section. Half VREFD This mode allows users to adjust the Vref level in case the GDDR5 SGRAM is operated without termination: when bit A7 is set to’1’, a Vref level of nominally 0.5 * VDDQ is expected at the VREFD pin or being generated internally (see Figure 31). Duty Cycle Correction (DCC) Bits A10 and A11 control the operation of the duty cycle corrector (DCC). The DCC can be used to cancel out a static duty cycle error on the WCK clocks. For more details see Duty Cycle Correction (DCC) in the section entitled OPERATION. VREFD Selection Options Summary The following table summarizes the complete set of VREFD selection options. Table 15 VREFD Selection Options MR6 MR7 DescriptionA3 Internal VREFD Half VREFD

00 E x t e r n a l

01 E x t e r n a l

10 I n t e r n a l 0.7 * VDDQ 11 I n t e r n a l 0.5 * VDDQ

responsability for use of circuits described. No patent licenses are implied. address training (ADT) has not taken place and the integrity of DDR addresses may not be guaranteed. and the Mode Register address (BA0‐BA3). Figure 33. Mode Register 15 (MR15) Definition Address training mode is enabled and disabled with bit A10. Mode Register 15 (this register) are not affected and will always be executed. without the use of a CS# pin.

1 Disabled

11110 R F U A D T MRE

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 63 H5GQ1H24AFR 5. OPERATION 5.1. COMMANDS Notes: 1) H = Logic High Level; L = Logic Low Level; X = Don’t care: signal may be H or L, but not floating 2) Addresses shown are logical addresses; physical addresses are inverted when address bus inversion (ABI) is activated and ABI#=L 3) BA0‐BA3 provide the Mode Register address (MRA), A0‐A11 the opcode to be loaded 4) BA0‐BA3 provide the bank address (BA), A0‐A11 (A12) provide the row address (RA). 5) BA0‐BA3 provide the bank address, A0‐A5 (A6) provide the column address (CA); no sub‐word addressing within a burst of 8. 6) The command is Refresh when CKE#(n) = L and Self Refresh Entry when CKE#(n) = H. 7) BA0‐BA3 and CA are used to select burst location and data respectively 8) DESELECT and NOP are functionally interchangeable 9) In address training mode READ is decoded from the commands pins only with RAS# = H, CAS# = L, WE# = H Table 16 Truth Table ‐ Commands Operation Symbol CKE# CS# RAS# CAS# WE# BA A11 A10 A8 A6, A7, A9, (A12) A0‐ (A6) Notes Previous cycle Current cycle DESELECT (NOP) D E S L X HX XXXXXX X X 1 , 2, 8 NO OPERATION (NOP) N O P L X LHHHXXXX X X 1 , 2, 8 MODE REGISTER SET MRS L L L L L L MRA Opcode 1, 2, 3 ACTIVE (Select bank & activate row) ACT L L L L H H BA RA 1, 2, 4 READ (Select bank and column, & start burst) R D L L LHLH B A LLL X C A 1 , 2, 5, READ with Autoprecharge RDA L L L H L H BA L L H X CA 1, 2, 5 Load FIFO L D F F L L LHLH X HLL X X 1 , 2, 7 READ Training R D T R L L LHLH X H HL X X 1 , 2 WRITE without Mask (Select bank and column, & start burst) WOM L L L HLL B A LLL X C A 1 , 2, 5 WRITE without Mask with Autoprecharge W O M A L L LHLL B A LLHX C A 1 , 2, 5 WRITE with single‐byte mask WSM L L L H L L BA L H L X CA 1, 2, 5 WRITE with single‐byte mask with Autoprecharge WSMA L L L H L L BA L H H X CA 1, 2, 5 WRITE with double‐byte mask (WDM) WDM L L L H L L BA H L L X CA 1, 2, 5 WRITE with double‐byte mask with Autoprecharge WDMA L L L H L L BA H L H X CA 1, 2, 5 WRITE Training WRTR L L L H L L X H H L X X 1, 2 PRECHARGE (Deactivate row in bank or banks) PRE L L L L H L BA X X L X X 1, 2 PRECHARGE ALL PREALL L L L L H L X X X H X X 1, 2 REFRESH R E F L L L L LHXXXX X X 1 , 6 POWER DOWN ENTRY PDE L H HX XXXXXX X X 1 LHHHXXXX X X 1 POWER DOWN EXIT PDX H L HX XXXXXX X X 1 LHHH SELF REFRESH ENTRY S R E L H L L LHXXXX X X 1 , 6 SELF REFRESH EXIT SRX H L HX XXXXXX X X 1 LHHH

responsability for use of circuits described. No patent licenses are implied. SGRAM. The GDDR5 SGRAM is effectively deselected. Operations already in progress are not affected. tions already in progress are not affected. mand cannot be issued until tMRD is met. Figure 36. MRS Command

responsability for use of circuits described. No patent licenses are implied. Figure 37. Mode Register Set Timings could be issued to that row, subject to the tRCD specification. banks in the same bank group is defined by tRRDL. In all other cases the interval is defined by tRRDS. <Link>Figure shows the tRCD and tRRD definition.

responsability for use of circuits described. No patent licenses are implied. mands may be issued at clocks N+1 through N+9 as illustrated in Figure 40. It is preferable that GDDR5 SGRAMs have no rolling activation window restrictions (tFAW = 4 * tRRD). Figure 40. tRRD and tFAW

responsability for use of circuits described. No patent licenses are implied. Figure 41. t32AW

responsability for use of circuits described. No patent licenses are implied. Figure 42. WRITE Command averaged over one double‐byte. The maximum skew within a double‐byte is defined by tDQDQI. specified for each supported bandwidth. In general tDIVW is smaller than tDIPW.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 71 H5GQ1H24AFR The data input pulse width, tDIPW, defines the minimum positive or negative input pulse width for any one worst‐case channel required for proper propagation of an external signal to the receiver. tDIPW is mea‐ sured at the pins. tDIPW is independent of the PLL mode. In general tDIPW is larger than tDIVW. Upon completion of a burst, assuming no other WRITE data is expected on the bus the GDDR5 SGRAM DQ and DBI# pins will be driven according to the ODT state. Any additional input data will be ignored. Data for any WRITE burst may not be truncated with a subsequent WRITE command. Data from any WRITE burst may be concatenated with data from a subsequent WRITE command. A con‐ tinuous flow of data can be maintained. The first data element from the new burst follows the last element of a completed burst. The new WRITE command should be issued after the previous WRITE command according to the tCCD timing. If that WRITE command is to another bank then an ACTIVE command must precede the WRITE command and tRCDWR also must be met. A READ can be issued any time after a WRITE command as long as the internal turn around time tWTR is met. If that READ command is to another bank, then an ACTIVE command must precede the READ com‐ mand and tRCDRD also must be met. A PRECHARGE can also be issued to the GDDR5 SGRAM with the same timing restriction as the new WRITE command if tRAS is met. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The data inversion flag is received on the DBI# pin to identify whether to store the true or inverted data. If DBI# is LOW, the data will be stored after inversion inside the GDDR5 SGRAM and not inverted if DBI# is HIGH. WRITE Data Inversion can be enabled (A9=0) or disabled (A9=1) using WDBI in MR1. When enabled by the WRCRC flag in MR4, EDC data are returned to the controller with a latency of (WLmrs + CRCWL) * tCK + tWCK2CKPIN + tWCK2CK + tWCK2DQO, where CRCWL is the CRC Write latency programmed in MR4 and tWCK2DQO is the WCK to DQ/DBI#/EDC phase offset at the DRAM pins.

responsability for use of circuits described. No patent licenses are implied. Figure 43. WRITE Timings 1) WLmrs is the WRITE latency programmed in Mode Register MR0. tWCK2CKPIN and tWCK2CK ranges. the actual tWCK2DQI value for stable WRITE operation. 5) Data Read timings are used for CRC return timing from WRITE commands with CRC enabled.

responsability for use of circuits described. No patent licenses are implied. Figure 44. Single WRITE without EDC

1. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
2. Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
3. WLmrs = 3 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
4. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
5. tWCK2DQI = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied. Figure 45. Single WRITE with EDC

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
3. Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
4. WLmrs = 3 and CRCWL = 8 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
5. tWCK2DQI, tWCKDQO = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied. Figure 46. Non-Gapless WRITEs

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
3. Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
4. WLmrs = 5 and tRCDWR = 3 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
5. EDC may be on or off. See Figure 4 for EDC Timing.
6. tWCK2DQI = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied. Figure 47. Gapless WRITEs

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. WLmrs = 2 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
3. EDC may be on or off. See Figure 4 for EDC Timing.
4. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
5. Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
6. tCCD = tCCDS when bank groups is disabled or the second WRITE is to a different bank group, otherwise tCCD=tCCDL.
7. tWCK2DQI = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied. Figure 48. WRITE to READ

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. WLmrs = 3 and CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
3. EDC may be on or off. See Figure 4 for EDC Timing.
4. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
5. Before the READ and WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD or tRCDWR
6. tWTR = tWTRL when bank groups is enabled and both WRITE and READ access banks in the same bank group, otherwise tWTR=tWTRS.
7. tWCK2DQI, tWCKDQO = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied. Figure 49. WRITE to PRECHARGE

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. WLmrs = 3 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
3. EDC may be on or off. See Figure 4 for EDC Timing.
4. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
5. Before the WRITE command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
6. tWCK2DQI = 0 is shown for illustration purposes.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 79 H5GQ1H24AFR 5.8. WRITE DATA MASK (DM) The traditional method of using a DM pin for WRITE data mask must be abandoned for a new method. Due to the high data rate of GDDR5 SGRAMs, bit errors are expected on the interface and are not recover‐ able when they occur on the traditional DM pin. In GDDR5 the DM is sent to the SGRAM over the address following the bank/column address cycle associ‐ ated with the command, during the NOP/DESELECT commands between the WRITE command and the next command. The DM is used to mask the corresponding data according to the following table. Two additional WRITE commands that augment the traditional WRITE Without Mask (WOM) are required for proper DM support:

• W D M : WRITE‐With‐Doublebyte‐Mask: 2 cycle command where the 1st cycle carries address information and the 2nd cycle carries data mask information (2 byte granularity); Table 17: DM State FUNCTION DM Value DQ Write Enable 0 Valid Write Inhibit 1 X

responsability for use of circuits described. No patent licenses are implied. Figure 50. WRITE-With-Doublebyte-Mask Command

responsability for use of circuits described. No patent licenses are implied. Figure 51. WDM Timing

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. WLmrs = 2 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
3. EDC may be on or off. See Figure 4 for EDC Timing.
4. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
5. Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
6. tCCD = tCCDS when bank groups is disabled or the second WRITE is to a different bank group, otherwise tCCD=tCCDL.
7. tWCK2DQI = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied.

• W S M : WRITE‐With‐Singlebyte‐Mask: 3 cycle command where the 1st cycle carries address information, the 2nd and 3rd cycle carry data mask information

Figure 52. WRITE-With-Singlebyte-Mask Command

responsability for use of circuits described. No patent licenses are implied. Figure 53. WSM Timing

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
3. Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
4. WLmrs = 5 and tRCDWR = 3 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
5. EDC may be on or off. See Figure 4 for EDC Timing.
6. tWCK2DQI = 0 is shown for illustration purposes.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 84 H5GQ1H24AFR Table 18 WDM Mapping for mirrored & non‐mirrored x32 Mode Byte and Burst Position Masked during WDM ADR ADR CK Rising Edge ADR ADR CK# Rising Edge Byte Burst Byte Burst A10 DQ[15:0] 0 A0 DQ[15:0] 4 A9 DQ[15:0] 1 A1 DQ[15:0] 5 BA0 DQ[15:0] 2 A2 DQ[15:0] 6 BA3 DQ[15:0] 3 A3 DQ[15:0] 7 BA2 DQ[31:16] 0 A4 DQ[31:16] 4 BA1 DQ[31:16] 1 A5 DQ[31:16] 5 A11 DQ[31:16] 2 A6 DQ[31:16] 6 A8 DQ[31:16] 3 A7 DQ[31:16] 7 Table 19 WDM Mapping for non‐mirrored x16 Mode Byte and Burst Position Masked during WDM ADR CK Rising Edge ADR ADR CK# Rising Edge ADR Byte Burst Byte Burst A10 DQ[7:0] 0 A0 DQ[7:0] 4 A9 DQ[7:0] 1 A1 DQ[7:0] 5 BA0 DQ[7:0] 2 A2 DQ[7:0] 6 BA3 DQ[7:0] 3 A3 DQ[7:0] 7 BA2 DQ[23:16] 0 A4 DQ[23:16] 4 BA1 DQ[23:16] 1 A5 DQ[23:16] 5 A11 DQ[23:16] 2 A6 DQ[23:16] 6 A8 DQ[23:16] 3 A7 DQ[23:16] 7 Table 20 WDM Mapping for mirrored x16 Mode Byte and Burst Position Masked during WDM ADR CK Rising Edge ADR ADR CK# Rising Edge ADR Byte Burst Byte Burst A10 DQ[15:8] 0 A0 DQ[15:8] 4 A9 DQ[15:8] 1 A1 DQ[15:8] 5 BA0 DQ[15:8] 2 A2 DQ[15:8] 6 BA3 DQ[15:8] 3 A3 DQ[15:8] 7 BA2 DQ[31:24] 0 A4 DQ[31:24] 4 BA1 DQ[31:24] 1 A5 DQ[31:24] 5 A11 DQ[31:24] 2 A6 DQ[31:24] 6 A8 DQ[31:24] 3 A7 DQ[31:24] 7

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 85 H5GQ1H24AFR Table 21 WSM Mapping for mirrored and non‐mirrored x32 Mode Byte and Burst Position Masked During WSM ADR CK 1st rising Edge ADR CK# 1st rising Edge ADR CK 2nd rising Edge ADR CK# 2nd rising Edge ADR Byte Burst ADR Byte Burst ADR Byte Burst ADR Byte Burst A10 DQ[7:0] 0 A0 DQ[7:0] 4 A10 DQ[15:8] 0 A0 DQ[15:8] 4 A9 DQ[7:0] 1 A1 DQ[7:0] 5 A9 DQ[15:8] 1 A1 DQ[15:8] 5 BA0 DQ[7:0] 2 A2 DQ[7:0] 6 BA0 DQ[15:8] 2 A2 DQ[15:8] 6 BA3 DQ[7:0] 3 A3 DQ[7:0] 7 BA3 DQ[15:8] 3 A3 DQ[15:8] 7 BA2 DQ[23:16] 0 A4 DQ[23:16] 4 BA2 DQ[31:24] 0 A4 DQ[31:24] 4 BA1 DQ[23:16] 1 A5 DQ[23:16] 5 BA1 DQ[31:24] 1 A5 DQ[31:24] 5 A11 DQ[23:16] 2 A6 DQ[23:16] 6 A11 DQ[31:24] 2 A6 DQ[31:24] 6 A8 DQ[23:16] 3 A7 DQ[23:16] 7 A8 DQ[31:24] 3 A7 DQ[31:24] 7 Table 22 WSM Mapping for non‐mirrored x16 Mode Byte and Burst Position Masked During WSM ADR CK 1st rising Edge ADR CK# 1st rising Edge ADR CK 2nd rising Edge ADR CK# 2nd rising Edge ADR Byte Burst ADR Byte Burst Byte Burst Byte Burst A10 DQ[7:0] 0 A0 DQ[7:0] 4 ‐ 0 ‐ 4 A9 DQ[7:0] 1 A1 DQ[7:0] 5 ‐ 1 ‐ 5 BA0 DQ[7:0] 2 A2 DQ[7:0] 6 ‐ 2 ‐ 6 BA3 DQ[7:0] 3 A3 DQ[7:0] 7 ‐ 3 ‐ 7 BA2 DQ[23:16] 0 A4 DQ[23:16] 4 ‐ 0 ‐ 4 BA1 DQ[23:16] 1 A5 DQ[23:16] 5 ‐ 1 ‐ 5 A11 DQ[23:16] 2 A6 DQ[23:16] 6 ‐ 2 ‐ 6 A8 DQ[23:16] 3 A7 DQ[23:16] 7 ‐ 3 ‐ 7 Table 23 WSM Mapping for mirrored x16 Mode Byte and Burst Position Masked During WSM ADR CK 1st rising Edge ADR CK# 1st rising Edge ADR CK 2nd rising Edge ADR CK# 2nd rising Edge Byte Burst Byte Burst ADR Byte Burst ADR Byte Burst ‐ 0 ‐ 4 A10 DQ[15:8] 0 A0 DQ[15:8] 4 ‐ 1 ‐ 5 A9 DQ[15:8] 1 A1 DQ[15:8] 5 ‐ 2 ‐ 6 BA0 DQ[15:8] 2 A2 DQ[15:8] 6 ‐ 3 ‐ 7 BA3 DQ[15:8] 3 A3 DQ[15:8] 7 ‐ 0 ‐ 4 BA2 DQ[31:24] 0 A4 DQ[31:24] 4 ‐ 1 ‐ 5 BA1 DQ[31:24] 1 A5 DQ[31:24] 5 ‐ 2 ‐ 6 A11 DQ[31:24] 2 A6 DQ[31:24] 6 ‐ 3 ‐ 7 A8 DQ[31:24] 3 A7 DQ[31:24] 7

responsability for use of circuits described. No patent licenses are implied. Figure 54. READ Command skew within a double‐byte is defined by tDQDQO. cede the READ command and tRCDRD also must be met.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 87 H5GQ1H24AFR A WRITE can be issued any time after a READ command as long as the bus turn around time tRTW is met. If that WRITE command is to another bank, then an ACTIVE command must precede the second WRITE command and tRCDWR also must be met. A PRECHARGE can also be issued to the GDDR5 SGRAM with the same timing restriction as the new READ command if tRAS is met. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The data inversion flag is driven on the DBI# pin to identify whether the data is true or inverted data. If DBI# is HIGH, the data is not inverted, and if LOW it is inverted. READ Data Inversion can be enabled (A8=0) or disabled (A8=1) using RDBI in MR1.

responsability for use of circuits described. No patent licenses are implied. Figure 55. READ Word Lane Timing 1) CLmrs is the CAS latency programmed in Mode Register MR0. tWCK2CKPIN and tWCK2CK ranges. the actual tWCK2DQO value for stable READ operation. pattern, and the data strobe in RDQS mode.

responsability for use of circuits described. No patent licenses are implied. Figure 56. Single READ without EDC

1. Before the READ command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
2. tWCK2DQO = 0 is shown for illustration purposes.
3. CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
4. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

responsability for use of circuits described. No patent licenses are implied. Figure 57. Single READ with EDC

1. Before the READ command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
2. tWCK2DQO = 0 is shown for illustration purposes.
3. CLmrs = 6 and CRCRL = 4 are shown as examples. Actual supported values will be found in the MR and AC timings sections.
4. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

responsability for use of circuits described. No patent licenses are implied. Figure 58. Non-Gapless READs

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. tCCD = tCCDL when bank groups are enabled and both READs access banks in the same bank group; otherwise tCCD=tCCDS.
3. Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
4. CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
5. EDC may be on or off. See Figure 4 for EDC Timing.
6. tWCK2DQI = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied. Figure 59. Gapless READs

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. tCCD = tCCDS when bank groups are disabled or the second READ is to a different bank group; otherwise tCCD=tCCDL.
3. Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
4. CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
5. EDC may be on or off. See Figure 4 for EDC Timing.
6. tWCK2DQI = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied. Figure 60. READ to WRITE

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. WLmrs = 3 and CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
3. EDC may be on or off. See Figure 4 for EDC Timing.
4. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
5. Before the READ and WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD or tRCDWR
6. tWTR = tWTRL when bank groups is enabled and both WRITE and READ access banks in the same bank group, otherwise tWTR=tWTRS.
7. tWCK2DQI, tWCKDQO = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied. Figure 61. READ to PRECHARGE

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. tRTP = tRTPL when bank groups are enabled and the PRECHARGE command accesses the same bank; otherwise tRTP = tRTPS.
3. Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
4. CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
5. EDC may be on or off. See Figure 4 for EDC Timing.
6. tWCK2DQO = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied. DQs for better signal integrity on the initial data of a burst. encoded with RDBI. If RDBI is disabled, then the DBI# pin drives ODT. 1) The number of Max 0’s in the burst is 4 only if RDBI is enabled. Max 0‘s is on a per byte basis and does not include the EDC pin. Figure 62. DQ Preamble Pattern

responsability for use of circuits described. No patent licenses are implied. Figure 63. Preamble Timing Diagram

1. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.
2. DQ6, DQ7 and the DBI# pin are shown to illustrate the DQ preamble pattern. RDBI is Enabled (MR1 A8=0).
3. Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
4. CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
5. EDC may be on or off. See Figure 4 for EDC Timing.
6. tWCK2DQO = 0 is shown for illustration purposes.

responsability for use of circuits described. No patent licenses are implied. Figure 66. DBI Flow Diagram

• P i n drives DBI FIFO data with RDTR command
• D B I # pin FIFO accepts WRTR data with the WRTR command If only DBI READ is enabled:
• D B I # pin drives ODT when not READ or RDTR If only DBI WRITE is enabled:
• P i n always drives ODT (unless RESET) If both DBI READ and DBI WRITE are disabled:
• D B I # pin drives ODT (unless RESET) No Yes Logical output data ’0’ count > 4 ? DBI# = ’L’ Invert data byte DBI# = ’H’ Don’t invert data byte Determine ’0’ count in data byte Logical input data DBI# = ’H’ Don’t invert data byte DBI# = ’L’ Invert data byte Transmitter Receiver

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 99 H5GQ1H24AFR 5.12. ERROR DETECTION CODE (EDC) The GDDR5 SGRAM provides error detection on the data bus to improve system reliability. The device generates a checksum per byte lane for both READ and WRITE data and returns the checksum to the con‐ troller. Based on the checksum, the controller can decide if the data (or the returned CRC) was transmitted in error and retry the READ or WRITE command. The GDDR5 SGRAM itself does not perform any error correction. The features of the EDC are:

• 8 bit checksum on 72 bits (9 channels x 8 bit burst)
• dedicated EDC transfer pin per 9 channels (4x per GDDR5 SGRAM)
• a s y m m e t r i c a l latencies on EDC transfer for Reads and Writes The CRC polynomial used by the GDDR5 SGRAM is an ATM‐8 HEC, X^8+X^2+X^1+1. The starting seed value is set in hardware at “zero”. Table 24 shows the error types that are detectable and the detection rate. The bit ordering calculation for the CRC error detection is optimized for errors in the time burst direction. Figure 67 shows the bit orientation on a byte lane basis. Table 24 Error Correction Details Error Type Detection Rate Random Single Bit 100% Random Double Bit 100% Random Odd Count 100% Burst <= 81 0 0 %

responsability for use of circuits described. No patent licenses are implied. Figure 67. EDC Calculation matrix

• f o r WRITEs, the CRC checksum is calculated on the DQ and DBI# input data before decoding with DBI
• f o r READs, the CRC checksum is calculated on the DQ and DBI# output data after encoding with DBI The bit ordering is optimized for errors in the time burst direction. Figure 67 shows the bit orientation on a byte lane basis. All ʹ1sʹ are assumed in the calculation for the DBI# in burst in case DBI is disabled for WRITEs or READs in the Mode Register. The CRC calculation is also not affected by any data mask sent along with WDM, WDMA, WSM or WSMA commands. The EDC latency is based on the CAS latency for READ data and the WRITE latency for WRITE data. Table 25 shows the 2 timing parameters associated with the EDC scheme. Mode Register 4 is used to determine the functionality of the EDC pin. Register bits A9 and A10 control the GDDR5 SGRAM’s CRC calculation independently for READs and WRITEs. With EDC off, the calculated CRC pattern will be replaced by the EDC hold pattern defined in Mode Register bits A0 ‐ A3. See “Mode Registers on page 39” section for more details. DQ0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DBI0# Burst 8 Ordering (2 tCK)CRC Data Input DQ/DBI# bit ordering 0 1 2 3 4 5 67 CRC Polynomial T0 + 8 U.I.T0 CRC Data Output EDC bit ordering Burst 8 Ordering (2 tCK) X0 X1 X2 X3 X4 X5 X6 X7 T0 + 8 U.I.T0 X8 + X2 + X + 1 = 0 x 83 = ( X + 1) (X7 + X6 + X5 + X4 + X3 + X2 + 1)

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 101 H5GQ1H24AFR Table 25 EDC Timing Description Parameter Value Units EDC READ Latency t EDCRL CL + CRCRL tCK EDC WRITE Latency t EDCWL WL + CRCWL t CK

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 102 H5GQ1H24AFR EDC Pin Special Function Overview The EDC pin is used for many different functions. The behavior of the EDC pin in various modes is sum‐ marized in Table 26. Table 26 EDC Pin Behavior Device Status Condition EDC0‐EDC3 Pin Status Device Power‐up RESET# = LOW Hi ‐Z RESET# = HIGH; no WCK clocks High RESET# = HIGH; stable WCK clocks EDC hold pattern (default = ’1111’) WCK2CK Training WCK is sampled High EDC hold pattern (’1111’) WCK is sampled Low Inverted EDC hold pattern (’0000’) Idle EDC13inv MR4 A11=0 EDC hold pattern EDC13inv MR4 A11=1 EDC0, EDC2: EDC hold pattern EDC1, EDC3: inverted EDC hold pattern WRITE Burst WRCRC on CRC data WRCRC off EDC hold pattern READ or RDTR burst RDCRC on CRC data RDCRC off EDC hold pattern LDFF WRCRC + RDCRC both on or both off EDC hold pattern WRTR burst ‐ EDC hold pattern Power‐Down WCK enabled (MR5 A1=0) EDC hold pattern WCK disabled during Power‐Down using MR5 A1=1 High Self Refresh ‐ High Read Burst in RDQS Mode MR3 A5=1 Fixed ’1010’ strobe pattern with 4 U.I. preamble READ burst in RDQS Mode with RDQS pseudo‐differential MR3 A5=1; EDC13inv MR4 A11=1 EDC0, EDC2: Fixed ’1010’ strobe pattern with 4 U.I. preamble EDC1, EDC3: Fixed ’0101’ strobe pattern with 4 U.I. preamble

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 104 H5GQ1H24AFR 5.14. AUTO PRECHARGE Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. This is accomplished by using A8 (A8 = High), to enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank / row that is addressed with the READ or WRITE command is automatically performed upon completion of the read or write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the OPERATION section of this specification. 5.15. REFRESH The REFRESH command is used during normal operation of the GDDR5 SGRAM. The command is non persistent, so it must be issued each time a refresh is required. A minimum time tRFC is required between two REFRESH commands. The same rule applies to any access command after the refresh operation. All banks must be precharged prior to the REFRESH command. The refresh addressing is generated by the internal refresh controller. This makes the address bits ʺDonʹt Careʺ during a REFRESH command. The GDDR5 SGRAM requires REFRESH cycles at an average peri‐ odic interval of tREFI(max). The values of tREFI for different densities are listed in Table 6. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted to the GDDR5 SGRAM, and the maximum absolute interval between any REFRESH command and the next REFRESH command is 9 * tREFI. During REFRESH, and when bit A2 in MR5 is set to 0, WRTR, RDTR, and LDFF commands are allowed at time tREFTR after the REFRESH command, which enable (incremental) data training to occur in parallel with the internal refresh operation and thus without loss of performance on the interface. See READ Train‐ ing and WRITE Training for details. As impedance updates from the auto‐calibration engine may occur with any REFRESH command, it is safe to only issue NOP commands during tKO period to prevent false command, address or data latching resulting from impedance updates.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 106 H5GQ1H24AFR 5.16. SELF‐REFRESH Self‐Refresh can be used to retain data in the GDDR5 SGRAM, even if the rest of the system is powered down. When in the Self‐Refresh mode, the GDDR5 SGRAM retains data without external clocking. The SELF REFRESH ENTRY command (see Figure 72) is initiated like a REFRESH command except that CKE# is pulled HIGH. SELF REFRESH ENTRY is only allowed when all banks are precharged with tRP satisfied, and when the last data element or CRC data element from a preceding READ or WRITE command have been pushed out (tRDSRE). NOP commands are required until tCKSRE is met after the entering Self‐Refresh. The PLL is automatically disabled upon entering Self‐Refresh and is automatically enabled and reset upon exiting Self‐Refresh. If the GDDR5 SGRAM enters Self‐Refresh with the PLL disabled, it will exit Self‐ Refresh with the PLL disabled. Once the SELF REFRESH ENTRY command is registered, CKE# must be held HIGH to keep the device in Self‐Refresh mode. When the device has entered the Self‐Refresh mode, all external control signals, except CKE# and RESET# are “Don’t care”. For proper Self‐Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VREFC, VREFD) must be at valid levels. The GDDR5 SGRAM initiates a minimum of one internal refresh within tCKE period once it enters Self‐Refresh mode. The address, com‐ mand, data and WCK pins are in ODT state, and the EDC pins drive a HIGH. The clock is internally disabled during Self‐Refresh operation to save power. The minimum time that the GDDR5 SGRAM must remain in Self‐Refresh mode is tCKE. The user may change the external clock fre‐ quency or halt the external CK and WCK clocks tCKSRE after Self‐Refresh entry is registered. However, the clocks must be restarted and stable tCKSRX before the device can exit Self‐Refresh operation. The procedure for exiting Self‐Refresh requires a sequence of events. First, the CK and WCK clocks must be stable prior to CKE# going back LOW. A delay of at least tXSNRW must be satisfied before a valid com‐ mand not requiring a locked PLL can be issued to the device to allow for completion of any internal refresh in progress. Before a command requiring a locked PLL can be applied, a delay of at least tXSRW must be satisfied. During Self‐Refresh the on‐die termination (ODT) and driver will not be auto‐calibrated. Therefore, it is recommended that the ODT and driver be recalibrated by the controller upon exiting Self‐Refresh. Alter‐ natively, if changes in voltage and temperature are tracked or known to be bounded then the provided Voltage and Temperature Variation tables may be consulted to determine if recalibration is necessary. Upon exit from Self‐Refresh, the GDDR5 SGRAM can be put back into Self‐Refresh mode after waiting at least tXSNRW period and issuing one extra REFRESH command.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 108 H5GQ1H24AFR Table 27 Pin States During Self Refresh Pin State EDC High DQ/DBI# ODT ADR/CMD ODT CKE# ODT (Driven High by Controller) WCK/WCK# ODT

responsability for use of circuits described. No patent licenses are implied. has been returned to the controller. vates the input and output buffers, excluding CK, CK#, WCK, WCK#, EDC pins and CKE#. READ or WRITE command can be issued. duration is limited by the refresh requirements of the device. NOP or DESELECT command). A valid executable command may be applied tXPN cycles later. The min. power‐down duration is specified by tPD. Figure 74. Power-Down Entry and Exit

1. Minimum CKE# pulse width must satisfy tCKE.
2. After issuing Power‐Down command, two more NOPs should be issued.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 110 H5GQ1H24AFR 5.18. COMMAND TRUTH TABLES Notes: 1. CKE#n is the logic state of CKE# at clock edge n; CKE#n‐1 was the state of CKE# at the previous clock edge. 2. Current state is the state of the GDDR5 SGRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSRW period. A minimum of tLK is needed for the PLL to lock before applying a READ or WRITE command if the PLL was disabled. Table 28 Pin States During Power Down Pin LP2 State EDC WCK ‘Hold’ no WCK High DQ/DBI# x ODT ADR/CMD x ODT CKE# x ODT (Driven High by Controller) WCK/WCK# x ODT Table 29 Truth Table – CKE# CKE#n‐1 CKE#n CURRENT STATE COMMANDn ACTIONn NOTES HH P o w e r ‐Down X Maintain Power‐Down HH S e l f Refresh X Maintain Self Refresh HL P o w e r ‐Down DESELECT or NOP Exit Power‐Down HL S e l f Refresh DESELECT or NOP Exit Self Refresh 5 LH A l l Banks Idle DESELECT or NOP Precharge Power‐Down Entry LH B a n k ( s ) Active DESELECT or NOP Active Power‐Down Entry LH A l l Banks Idle REFRESH Self Refresh Entry LL See <Link>Table 30 and <Link>Table 31 1, 2, 3

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 111 H5GQ1H24AFR Notes 1. This table applies when CKE#n‐1 was LOW and CKE#n is LOW (see <Link>Table 29) and after tXSNR has been met (if the previous state was self refresh). 2. This table is bank‐specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled. Write: A WRITE burst has been initiated, with auto precharge disabled. 4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and <Link>Table 30, and according to <Link>Table 31. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the “row active” state. Read w/Auto‐Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto‐Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of a REFRESH command and ends when tRC is met. Once tRC is met, the GDDR5 SGRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the GDDR5 SGRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. READ or WRITE: Starts with the registration of the ACTIVE command and ends the last valid data nibble. 6. All states and sequences not shown are illegal or reserved. 7. Not bank‐specific; requires that all banks are idle, and bursts are not in progress. 8. May or may not be bank‐specific; if multiple banks are to be precharged, each must be in a valid state for precharging. Table 30 Truth Table – Current State Bank n – Command To Bank n CURRENT STATE CS# RAS# CAS# WE# COMMAND/ACTION NOTES Any H X X X DESELECT (NOP/continue previous operation) LHHH N O OPERATION (NOP/continue previous operation) Idle LLH H A C T I V E (select and activate row) LLLH R E F R E S H 4 LLLL M O D E REGISTER SET 4 Row Active LHLH R E A D (select column and start READ burst) 6 LHLL WRITE (select column and start WRITE burst) (WOM, WSM or WDM) 6 L L H L PRECHARGE (deactivate row in bank or banks) 5 Read (Auto Precharge Disabled) LHLH R E A D (select column and start new READ burst) 6 LHLL WRITE (select column and start WRITE burst) (WOM, WSM or WDM) 6, 8 L L H L PRECHARGE (only after the READ burst is complete 5 Write (Auto Precharge Disabled) (WOM, WSM or WDM) LHLH R E A D (select column and start READ burst) 6, 7 LHLL WRITE (select column and start new WRITE burst) (WOM, WSM or WDM) 6 L L H L PRECHARGE (only after the WRITE burst is complete) 5, 7

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 112 H5GQ1H24AFR 9. Reads or Writes listed in the Command/Action column include Reads or Writes with auto precharge enabled and Reads or Writes with auto precharge disabled. 10. A WRITE command may be applied after the completion of the READ burst Notes 1. This table applies when CKE#n‐1 was LOW and CKE#n is LOW (see <Link>Table 30) and after tXSNR has been met (if the previous state was self refresh). 2. WRITE in this table refers to both WOM/WOMA, WSM/WSMA and WDM/WDMA commands 3. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 4. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled. Write: A WRITE burst has been initiated, with auto precharge disabled. Read with Auto Precharge Enabled: See following text Write with Auto Precharge Enabled: See following text 4a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was Table 31 Truth Table – Current State Bank n – Command To Bank m CURRENT STATE CS# RAS# CAS# WE# COMMAND/ACTION NOTES Any H X X X DESELECT (NOP/continue previous operation) LHH H NO OPERATION (NOP/continue previous operation) Idle X X X X Any Command Otherwise Allowed to Bank m Row Activating, Active, or Precharging LLHH ACTIVE (select and activate row) LHL H READ (select column and start READ burst) 6 LHL L WRITE (select column and start WRITE burst) (WOM, WSM or WDM) LLH L PRECHARGE Read (Auto Precharge Disabled) LLHH ACTIVE (select and activate row) LHL H READ (select column and start new READ burst) 6 LHL L WRITE (select column and start WRITE burst) (WOM, WSM or WDM) LLH L PRECHARGE Write (Auto Precharge Disabled) LLHH ACTIVE (select and activate row) LHL H READ (select column and start READ burst) 6, 7 LHL L WRITE (select column and start new WRITE burst) (WOM, WSM or WDM) LLH L PRECHARGE Read (With Auto Precharge) LLHH ACTIVE (select and activate row) LHL H READ (select column and start new READ burst) 6 LHL L WRITE (select column and start WRITE burst) (WOM, WSM or WDM) LLH L PRECHARGE Write (With Auto Precharge) LLHH ACTIVE (select and activate row) LHL H READ (select column and start READ burst) 6 LHL L WRITE (select column and start new WRITE burst) (WOM, WSM or WDM) LLH L PRECHARGE

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 113 H5GQ1H24AFR executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). 4b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is summarized below. 5. REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. * CL = CAS latency (CL) BL = Burst length WL = WRITE latency tWTR = tWTRL if Bank Groups enabled and access to the same bank otherwise tWTR=tWTRS Table 32 Minimum Delay Between Commands to Different Banks with Auto Precharge Enabled From Command To Command Minimum delay (with concurrent auto precharge) WRITE with AUTO PRECHARGE (WOMA) READ or READ with AUTO PRECHARGE [WLmrs + (BL/4)] tCK + tWTRL * WRITE or WRITE with AUTO PRECHARGE (WOM/WOMA, WSM/WSMA or WDM/WDMA) 2 * tCK PRECHARGE 1 tCK ACTIVE 1 tCK WRITE with AUTO PRECHARGE (WDMA) READ or READ with AUTO PRECHARGE [WL + (BL/4)] tCK + tWTR *** WRITE or WRITE with AUTO PRECHARGE (WOM/WOMA, WSM/WSMA or WDM/WDMA) 2 * tCK PRECHARGE 2 tCK ACTIVE 2 tCK WRITE with AUTO PRECHARGE (WSMA) READ or READ with AUTO PRECHARGE [WL + (BL/4)] tCK + tWTR *** WRITE or WRITE with AUTO PRECHARGE (WOM/WOMA, WSM/WSMA or WDM/WDMA) 3 * tCK PRECHARGE 3 tCK ACTIVE 3 tCK READ with AUTO PRECHARGE READ or READ with AUTO PRECHARGE 2 * tCK WRITE or WRITE with AUTO PRECHARGE (WOM/WOMA, WSM/WSMA or WDM/ WDMA) [CLmrs + (BL/4) + 2 ‐ WL] * tCK *** PRECHARGE 1 tCK ACTIVE 1 tCK

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 114 H5GQ1H24AFR 5.19. RDQS MODE For device operation at lower clock frequencies the GDDR5 SGRAM may be set into RDQS mode in which a READ DATA STROBE (RDQS) in the style of GDDR4 will be sent on the EDC pins along with the READ data. The controller will use the RDQS to latch the READ data. RDQS mode is entered by setting the RDQS Mode bit A5 in Mode Register 3 (MR3). When the bit is set, the GDDR5 SGRAM will asynchronously terminate any EDC hold pattern and drive a logic HIGH after tMRD at the latest. All features controlled by MR4 are ignored by RDQS mode. READ commands are executed as in normal mode regarding command to data out delay and pro‐ grammed READ latencies. A fixed clock‐like pattern as shown in Figure 75 is driven on EDC pins in phase (edge aligned) with the DQ. Prior to the first valid data element, this fixed clock‐like pattern or READ pre‐ amble is driven for 2 tWCK. No CRC is calculated in RDQS mode, neither for READs nor for WRITEs. The CRC engine is effectively disabled, and the corresponding WRCRC and RDCRC Mode Register bits are ignored. The PLL may be on or off with RDQS mode, depending on system considerations and the PLL’s minimum clock frequency. There is no equivalent WDQS mode; WRITE commands to the GDDR5 SGRAM are not affected by RDQS mode. RDQS mode is exited by resetting the RDQS Mode bit. In this case the GDDR5 SGRAM will asynchro‐ nously start driving the EDC hold pattern after tMRD.

responsability for use of circuits described. No patent licenses are implied. done when the RDQS mode is active. Figure 75. RDQS Mode Timings EDC13Inv field, bit A11 in MR4, as shown in Table 34.

1. MRA = Mode Register address and opcode; BA = bank address; CA = column address
2. Before the READ command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
3. tWCK2DQO = 0 is shown for illustration purposes.
4. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 116 H5GQ1H24AFR 5.20. CLOCK FREQUENCY CHANGE SEQUENCE Step 1) Wait until all commands have finished, all banks are idle. Step 2) Send NOP or DESELECT (must meet setup/hold relative to clock while clock is changing) to GDDR5 SGRAM for the entire sequence unless stated to do otherwise. The user must take care of refresh requirements. Step 3) If the new desired clock frequency is below the min frequency supported by PLL‐on mode, turn the PLL off via an MRS command. Step 4) Change the clock frequency and wait until clock is stabilized. Step 5) If the new clock frequency is within the PLL on range and the PLL on state is desired, enable the PLL via an MRS Command if it is not already enabled. Step 6) Perform address training if required. Step 7) Perform WCK2CK training. As defined in the WCK2CK training process, if the PLL is enabled, then complete steps 7a and 7b: 7a) Reset the PLL by writing to the MRS register. 7b) Wait tLK clock cycles before issuing any commands to the GDDR5 SGRAM. Step 8) Exit WCK2CK training. Step 9) Perform READ and WRITE training, if required. Step 10) GDDR5 SGRAM is ready for normal operation after any necessary interface training.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 117 H5GQ1H24AFR 5.21. DYNAMIC VOLTAGE SWITCHING (DVS) GDDR5 SGRAM’s allow the supply voltage to be changed during the course of normal operation using the GDDR5 Dynamic Voltage Switching (DVS) feature. By using DVS the GDDR5 SGRAM’s power consump‐ tion can be reduced whenever only a fraction of the maximum available bandwidth is required by the cur‐ rent work load. DVS requires the GDDR5 SGRAM to be properly placed into self refresh before the voltage is changed from the exising stable voltage, Voriginal to the new desired voltage Vnew . The DVS procedure may also require changes to the VDD Range mode register using MR7 bits A8 and A9, depending on whether the feature is supported. The datasheet shall be consulted regarding the supported supply voltages for DVS, and any dependencies of AC timing parameters on the selected supply voltage. Clock frequency changes can also take place before or after entering self refresh mode using the standard Clock Frequency Change procedure. A clock frequency change in conjunction with DVS is required if tCK is less than tCKmin supported by Vnew . In this case normal device operation including self refresh exit is not guaranteed without a frequency change. Changing the frequency while in self refresh is the most safe procedure. Once self refresh is entered, tCKSRE must be met before the supply voltage is allowed to transition from Voriginal to Vnew. After VDD and VDDQ are stable at Vnew, tVS must be met to allow for internal voltages in the GDDR5 SGRAM to stabilize before self refresh mode may be exited. During the voltage transition the voltage must not go below Vmin of the lower voltage of either Voriginal or Vnew in order to prevent false chip reset. Vmin is the minimum voltage allowed by VDD or VDDQ in the DC operating conditions table. VREF shall continue to track VDDQ. DVS Procedure Step 1) Complete all operations and precharge all banks. Step 2) Issue an MRS command to set VDD Range to proper values for Vnew. This step is only required when the VDD Range mode register field is supported by the GDDR5 SGRAM. Step 3) Enter self refresh mode. Self refresh entry procedure must be met. Step 4) Wait required time tCKSRE before changing voltage to Vnew. Step 5) Change VDD and VDDQ to Vnew. Step 6) Wait required time tVS for voltage stabilization. Step 7) Exit self refresh. The self refresh exit procedure must be met. Step 8) Issue MRS commands to adjust mode register settings as desired (e.g. latencies, PLL on/off, CRC on/off, RDQS mode on/off). Step 9) Perform any interface training as required. Step 10) Continue normal operation.

responsability for use of circuits described. No patent licenses are implied. Figure 76. DVS Sequence

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 119 H5GQ1H24AFR 5.22. TEMPERATURE SENSOR GDDR5 SGRAMs incorporate a temperature sensor with digital temperature readout function. This func‐ tion allows the controller to monitor the GDDR5 SGRAM die’s junction temperature and use this informa‐ tion to make sure the device is operated within the specified temperature range or to adjust interface timings relative to temperature changes over time. The temperature sensor is enabled by bit A6 in Mode Register 7 (MR7). In this case the temperature read‐ out is valid after tTSEN. Hynix applies 10us to tTSEN. The temperature readout uses the DRAM Info mode feature. The digital value is driven asynchronously on the DQ bus following the MRS command to Mode Register 3 (MR3) that sets bit A7 to 1 and bit A6 to 0. The temperature readout will be continuously driven until an MRS command sets both bits to 0. The GDDR5 SGRAM’s junction temperature is linearly encoded as shown in Table 35. Hynix has the read‐ out to a subset of six digital codes out of Table 35, corresponding to six temperature thresholds. Table 34 Temperature Sensor Readout Pattern Temperature [°C] Binary Temperature Readout MF=0: MF=1: DQ[5:0] DQ[31:26] ＜ 45 000000 55 000001 65 000011 75 000111 85 001111 95 011111 ＞ 95 111111

responsability for use of circuits described. No patent licenses are implied. training and should be run for tDCC in order to effectively correct any error. DCC can correct the duty cycle error within the range of ± 100ps. Figure 77. Timing Diagram of DCC Control Signals

• D C C reset : The DCC reset is used to initialize the DCC code and should be issued anytime before the WCK enables (MRS7 A11:1, A10:0)
• D C C start : The DCC start is used to update the DCC code and should be issued anytime after the WCK is stable (MRS7 A11:0, A10:1)
• D C C stop : The DCC stop is used to make it stop to update the DCC code while the DCC code is held. This should be issued after enough time from DCC start if needs (MRS7 A11:0, A10:0) Table 35 DCC Timings Parameter Symbol Min Max Unit Required time for duty cycle corrector t DCC 150 ‐ tCK Training PLL Reset DCC start DCC stop or not DCC reset Enter WCK2CK Training (reset WCK divide by circuits) Enter WCK2CK Training (sets data synchronizers, resets FIFO pointers) WCK# WCK CK# CK CMD NOP NOP MRS NOP NOP MRSNOP NOP MRS A.C. tWCKTMRS tMRD tWCKTTR tDCC tLK tMRD Start WCK2CK Phase

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 121 H5GQ1H24AFR Table 36 DCC Control Signals A11 A10 DCC 00 n o DCC & DCC stop

10 D C C reset

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 122 H5GQ1H24AFR 6. OPERATING CONDITIONS 6.1. ABSOLUTE MAXIMUM RATINGS Voltage on Vdd Supply Voltage on VddQ Supply Voltage on Vref and Inputs Voltage on I/O Pins *Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. Measurement procedures for each parameter must follow standard procedures defined in the current JEDEC JESD‐51 standard. 2. Theta_JA measured with the low and high thermal conductivity test board defined in JESD51‐9 Table 37 Capacitance PARAMETER SYMBOL MIN MAX UNITS NOTES Delta Input/Output Capacitance: DQs, DBI#, EDC, WCK, WCK# DCio 0 0.5 pF Delta Input Capacitance: Command and Address DCi 1 00 . 5p F Delta Input Capacitance: CK, CK# DCi 2 00 . 3p F Input/Output Capacitance: DQs, DBI#, EDC, WCK, WCK# Cio 1.2 1.9 pF Input Capacitance: Command and Address Ci 1 0.9 1.6 pF Input Capacitance: CK, CK#, WCK, WCK# Ci 2 0.9 1.6 pF Input Capacitance: CKE# Ci 3 0.9 1.6 pF Table 38 Thermal Characteristics Parameter Description Value Units Notes Theta_JA Thermal resistance junction to ambient 45 oC/W 1,2,4,5 33 oC/W 1,4,5 (at Tc 115oC) 2s2p 30 oC/W 1,2,4,5 Theta_JB Thermal resistance junction to board 12 oC/W 1,3 Theta_JC Thermal resistance junction to case 3 oC/W 1,6

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 123 H5GQ1H24AFR 3. Theta_JB measured with the special boundary condition defined in JESD51‐8 4. Theta_JA should only be used for comparing the thermal performance of single package and not for system related junction. 5. Theta_JA is the natural convection junction‐to‐ambient air thermal resistance measured in one cubic foot sealed enclosure as decribed in JESD 51‐2. The environment is sometimes refered to as “still‐air” although natural convection causes the air to move. 6. Theta_JC case surface is defined as the “outside surface of the package (case) closest to the chip mounting area when that same surface is properly hear sunk” so as to minimize temperature variation across that surface.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 124 H5GQ1H24AFR 6.2. AC & DC CHARACTERISTICS All GDDR5 SGRAMs are designed for 1.5V typical voltage supplies. The interface of GDDR5 with 1.5V VDDQ will follow the POD15 specification. All AC and DC values are measured at the ball. Notes: 1. VDD/VDDQ 1.6V is for 6Gbps 2. GDDR5 SGRAMs are designed to tolerate PCB designs with separate VDD and VDDQ power regulators. 3. AC noise in the system is estimated at 50mV pk‐pk for the purpose of DRAM design. 4. Source of Reference Voltage and control of Reference Voltage for DQ and DBI# pins is determined by VREFD, Half VREFD, Auto VREFD, VREFD MERGE and VREFD Offsets mode registers. 5. VREFD Offsets are not supported with VREFD2. 6. External VREFC is to be provided by the controller as there is no other alternative supply. 7. DQ/DBI# input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and VIHD(AC) or VILD(AC) or VREFD2 crossing and VIHD2(AC) or VILD2(AC). 8. ADR/CMD input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIHA(AC) or VILA(AC). 9. VIHX and VILX define the voltage levels for the receiver that detects x32 or x16 mode with RESET# going High. Table 39 DC Operating Conditions Parameter Symbol Min Typ Max Unit Note Device Supply Voltage VDD 1.452 1.6 1.648 V 1 Output Supply Voltage VDDQ 1.452 1.6 1.648 V 1 Device Supply Voltage VDD 1.455 1.5 1.545 V 2 Output Supply Voltage VDDQ 1.455 1.5 1.545 V 2 Reference Voltage for DQ and DBI# pins VREFD 0.69 * VDDQ 0.71 * VDDQ V 3, 4 Reference Voltage for DQ and DBI# pins VREFD2 0.49 * VDDQ 0.51 * VDDQ V 3, 4, 5 External Reference Voltage for address and command VREFC 0.69 * VDDQ 0.71 * VDDQ V 6 DC Input Logic HIGH Voltage for address and command VIHA (DC) VREFC + 0.15 V DC Input Logic LOW Voltage for address and command VILA (DC) VREFC ‐ 0.15 V DC Input Logic HIGH Voltage for DQ and DBI# pins with VREFD VIHD (DC) VREFD + 0.10 V DC Input Logic LOW Voltage for DQ and DBI# pins with VREFD VILD (DC) VREFD ‐ 0.10 V DC Input Logic HIGH Voltage for DQ and DBI# pins with VREFD2 VIHD2 (DC) VREFD2 + 0.30 V DC Input Logic LOW Voltage for DQ and DBI# pins with VREFD2 VILD2 (DC) VREFD2 ‐ 0.30 V Input Logic HIGH Voltage for RESET#, SEN, MF VIHR VDDQ ‐ 0.50 V Input Logic LOW Voltage for RESET#, SEN, MF VILR 0.30 V Input logic HIGH voltage for EDC1/2 (x16 mode detect) VIHX VDDQ ‐ 0.3 V 9 Input logic LOW voltage for EDC1/2 (x16 mode detect) VILX 0.30 V 9 Input Leakage Current Any Input 0V <= VIN <= VDDQ (All other pins not under test = 0V) Il 10 μA Output Leakage Current (DQs are disabled; 0V <= Vout <= VDDQ) Ioz 10 μA Output Logic LOW Voltage VOL (DC) 0.62 V

responsability for use of circuits described. No patent licenses are implied. Figure 78. Voltage Waveform VREFD2, or VREFC) is being used.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 126 H5GQ1H24AFR Notes: 1. This provides a minimum of 0.9V to a maximum of 1.2V, and is nominally 70% of VDDQ with POD15. DRAM timings relative to CK cannot be guaranteed if these limits are exceeded. 2. For AC operations, all DC clock requirements must be satisfied as well. 3. The value of VIXCK and VIXWCK is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same. 4. VIDCK is the magnitude of the difference between the input level in CK and the input level on CK#. The input reference level for signals other than CK and CK# is VREFC. 5. VIDWCK is the magnitude of the difference between the input level in WCK and the input level on WCK#. The input reference level for signals other than WCK and WCK# is either VREFD, VREFD2 or the internal VREFD. 6. The CK and CK# input reference level (for timing referenced to CK and CK#) is the point at which CK and CK# cross. Please refer to the applicable timings in the AC timings table (Table 44). 7. The WCK and WCK# input reference level (for timing referenced to WCK and WCK#) is the point at which WCK and WCK# cross. Please refer to the applicable timings in the AC Timings table (Table 44). 8. VREFD is either VREFD, VREFD2 or the internal VREFD. 9. The slew rate is measured between VREFC crossing and VIXCK(AC). 10. The slew rate is measured between VREFD crossing and VIXWCK(AC). 11. Figure illustrates the exact relationship between (CK‐CK#) or (WCK‐WCK#) and VID(AC), VID(DC) and tDVAC 12. Ringback below VID(DC) is not allowed. 13. tDVAC is not measured in and of itself as a compliance specification, but is relied upon in measurement of clock operating conditions and clock related parameters. Table 41 Clock Input Operating Conditions POD15 Parameter Symbol Min Max Unit Note Clock Input Mid‐Point Voltage; CK and CK# VMP (DC) VREFC ‐ 0.10 VREFC + 0.10 V 1, 6 Clock Input Differential Voltage; CK and CK# VIDCK (DC) 0.22 V 4, 6 Clock Input Differential Voltage; CK and CK# VIDCK (AC) 0.40 V 2, 4, 6 Clock Input Differential Voltage; WCK and WCK# VIDWCK (DC) 0.20 V 5, 7 Clock Input Differential Voltage; WCK and WCK# VIDWCK (AC) 0.30 2, 5, 7 Clock Input Voltage Level; CK, CK#, WCK and WCK# single ended VIN ‐0.30 VDDQ + 0.30 CK/CK# Single ended slew rate CKslew 3 V/ns 9 WCK/WCK# Single ended slew rate WCKslew 3 V/ns 10 Clock Input Crossing Point Voltage; CK and CK# VIXCK (AC) VREFC ‐ 0.12 VREFC + 0.12 V 2, 3, 6 Clock Input Crossing Point Voltage; WCK and WCK# VIXWCK (AC) VREFD ‐ 0.10 VREFD + 0.10 V 2, 3, 7, Allowed time before ringback of CK/WCK below VIDCK/WCK(AC) tDVAC ps 11, 12,

responsability for use of circuits described. No patent licenses are implied. Figure 79. Clock Waveform

responsability for use of circuits described. No patent licenses are implied. Figure 80. Definition of differential ac-swing and “time above ac-level” tDV AC

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 129 H5GQ1H24AFR NOTE: Min tRC or tRFC for IDD measurements is the smallest multiple of tCK that meets the minimum of the absolute value for the respective parameter. Common Test conditions: 1) Device is configured to x32 mode 2) ABI and DBI are enabled 3) All ODTs are enabled with ZQ/2 4) PLLs are enabled unless otherwise noted 5) CRC is enabled for READs and WRITEs, and the EDC hold pattern is programmed to’1010’ 6) Bank groups are enabled if required for device operation at tCK(min) 7) Address inputs include ABI# pin 8) Each data byte consists of eight DQs and one DBI# pin 9) DESELECT condition during idle command cycles Table 42 IDD Specifications and Test Conditions PARAMETER/CONDITION SYMBOL NOTES One Bank Activate Precharge Current: tCK = tCK(min); tWCK = tWCK(min); tRC = tRC(min); CKE# = LOW; DQ, DBI# are HIGH; random bank and row addresses (4 address inputs set LOW) with ACT command IDD0 1 One Bank Activate Read Precharge Current: tCK = tCK (min); tWCK = tWCK(min); tRC = tRC(min); CKE# = LOW; one bank activated; single read burst with 50% data toggle on each data transfer, with 4 outputs per data byte driven LOW; otherwise DQ, DBI# are HIGH; random bank, row and column addresses (4 address inputs set LOW) with ACT and READ commands; IOUT = 0mA IDD1 1 Precharge Power‐down Current: tCK = tCK (min); tWCK = tWCK(min); all banks idle; CKE# = HIGH; all other inputs are HIGH; PLLs are off IDD2P Precharge Standby Current: tCK = tCK (min); tWCK = tWCK(min); all banks idle; CKE# = LOW; all other inputs are HIGH IDD2N Active Power‐down Current: tCK = tCK (min); tWCK = tWCK(min); one bank active; CKE# = HIGH; all other inputs are HIGH IDD3P Active Standby Current: tCK = tCK (min); tWCK = tWCK(min); one bank active; CKE# = LOW; all other inputs are HIGH IDD3N Read Burst Current: tCK = tCK (min); tWCK = tWCK(min); CKE# = LOW; one bank in each of the 4 bank groups activated; continuous read burst across bank groups with 50% data toggle on each data transfer, with 4 outputs per data byte driven LOW; random bank and column addresses (4 address inputs set LOW) with READ command; IOUT = 0mA IDD4R Write Burst Current: tCK = tCK (min); tWCK = tWCK(min); CKE# = LOW; one bank in each of the 4 bank groups activated; continuous write burst across bank groups with 50% data toggle on each data transfer, with 4 inputs per data byte set LOW; random bank and column addresses (4 address inputs set LOW) with WRITE command; no data mask IDD4W Refresh Current: tCK = tCK (min); tWCK = tWCK(min); tRFC = tRFC(min); CKE# = LOW; DQ, DBI# are HIGH; address inputs are HIGH IDD5 1 Self Refresh Current: CKE# = HIGH; all other inputs are HIGH IDD6 Four Bank Interleave Read Current: tCK = tCK(min); tWCK = tWCK(min); CKE# = LOW; one bank in each of the 4 bank groups activated and precharged at tRC(min); continuous read burst across bank groups with 50% data toggle on each data transfer, with 4 outputs per data byte driven LOW; random bank, row and column addresses (4 address inputs set LOW) with ACT and READ/ READA commands; IOUT = 0mA IDD7

Table 43. IDD SPECIFICATIONS AND CONDITIONS

Table 44. AC Timings (@1.5V)

Table 44. AC Timings (@1.35V)

a. All parameters assume proper device initialization. voltage and temperature range specified. DRAM pins is within tWCK2CKSYNC or tWCK2CK for pin mode and no phase search in WCK2CK training is performed. f. Parameter fCKRDQS applies when RDQS mode is enabled in AR3, bit A5. g. Parameter fCKBREFD2 applies when the data input reference voltage in MR7, bit A7 (Half VREFD) is set to VREFD2. h. Parameter fCKAUTOSYNC applies when WCK2CK Auto Synchronization is enabled in MR7, bit A4. i. Parameter fCKLF applies when Low Frequency Mode is enabled in MR7, bit A3. j. By definition the norminal WCK clock cycle time always is 1/2 of the CK clock cycle time (not including jitter).

Rev. 1.0 /Nov. 2009 151 H5GQ1H24AFR l. The phase relationship between WCK/WCK# and CK/CK# clocks must meet the tWCK2CK specification. m. Command and address input timings are referenced to VREFC. n. Command and address input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIHA(AC) or VILA(AC). o. Command and address input pulse widths are design targets. The value will be characterized but not tested on each device. p. Address input timings are only valid with ABI beging enabled and a maximum of 4 address input driven LOW. q. Parameter may be specified as a combination of tCK and ns. r. Parameters tWCKHTR and tWCKLTR specify the max. allowed WCK clock-to-clock phase shift during WCK2CK training. For READ and WRITE bursts use tWCKH and tWCKL. s. Parameter tWCK2CKPIN defines the WCK2CK phase offset range at the CK and WCK pins for ideal (phase= 0 °) clock alignment at the GDDR5 SGRAM’s phase detector (when the alignment point in MR6, bit A0 is set to “at phase detector”), or at the WCK and CK pins (when the alignment in MR6, bit A0 is set to “at pins”). The minimum and maximum values could be negative or positive numbers, depending on the selected WCK2CK alignment point, PLL-on or PLL-off mode and design implementation. t. Parameter tWCK2CKSYNC defines the max. phase offset from the ideal (phase = 0 °) clock alignment at the GDDR5 SGRAM’s phase detector (when the alignment point in MR6, bit A0 is set to “at the phase detector”), or at the WCK and CK pins (when the alignment point in MR6, bit A0 is set to “at pins”), where the internal logic synchronizes the CK and WCK clocks; it is expected to be a fraction of tWCK2CK. u. Parameter tWCK2CK defines the max. phase offset from the ideal (phase = 0 °) clock alignment at the GDDR5 SGRAM’s phase detector (when the alignment point in MR6, bit A0 is set to “at phase detector”) or at the WCK and CK pins (when the alignment point in MR6, bit A0 is set to “at pins”), for stable device operation. v. Parameter tWCK2DQI defines the WCK to DQ/DBI# time delay range for WRITEs for PLL-on and PLL-off mode. The minimum and maximum values could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT. Data training is required to determine the actual tWCK2DQI value for reliable WRITE operation. w. Parameter tWCK2DQO defines the WCK to DQ/DBI# time delay range for READs for PLL-on and PLL-off mode. The minimum and maxium values could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT. Data training is required to determind the actual tWCK2DQO value for reliable READ operation. x. Outputs measured with equivalent load terminated with 60 Ohms to VDDQ y. DQ/DBI# input timings are valid only with DBI being enabled and a maximum of 4 data inputs per byte driven LOW. z. Data input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between V REFD crossing and VIHD(AC) or VILD(AC). aa. The data input pulse width, tDIPW, defines the minimum positive or negative input pulse width for any worst-case channel required for proper propagation of an external signal to the receiver. tDIPW is measured at the pins. tDIPW is independent of the PLL mode. In general tDIPW is larger than tDIVW ab. The data input valid width, tDIVW, defines the time region where input data must be valid for reliable data capture at the receiver for any one worst case channel. It accounts for jitter between data and clock at the latching point introduced in the path between DARM pads and the latching point. Any additional jitter introduced into the source signals (e.g. within the system before the DRAM pad) must be accounted for in the final timing budget together with the chosen PLL mode and bandwidth. tDIVW is measured at the pins. tDIVW is defined for PLL off and on mode separately. In the case of PLL on, tDIVW must be specified for each supported bandwidth. In general, tDIVW is smaller than tDIPW. ac. tDQDQI defines the maximum skew among all DQ/DBI# inputs of a double byte (when configured to ×3 2 mode) or a single byte (when configured to ×1 6 mode) under worst case conditions. Parameter tWCK2DQI defines the mean value of the earliest and latest DQ/DBI# pin, tDQDQI(min) the negative offset to tWCK2DQI for the earliest DQ/DBI# pin and tDQDQI(max) the positive offset to tWCK2DQI for the latest DQ/DBI# pin. ad. tDQDQO defines the maximum skew among all DQ/DBI# outputs of a double byte (when configured to × 32mode) or a single byte (when configured to ×1 6 mode) under worst case conditions. Parameter tWCK2DQO defines the mean value of of the earliest and latest DQ/DBI# /EDC pin, tDQDQO(min) the negative offset to tWCK2DQO for earliest DQ/DBI#/EDC pin and tDQDQO(max) the positive offset to tWCK2DQO for the latest DQ/DBI#/EDC pin. ae. For READs and WRITEs with AUTO PRECHARGE enabled the device will hold off the internal PRECHARGE until tRAS(min) has been satisfied. af. Parameter applies when bank groups are enabled and consecutive commands access the same bank group. ag. Parameter applies when bank groups are disabled or consecutive commands access different bank group. ah. Not more than 4 ACTIVE commands are allowed within period. ai. Not more than 32 ACTIVE commands are allowed within t32AW period. The parameter need not to be specified in case t32AW(min) would not be greater than 8*tFAW(min). aj. Parameter applies when bank groups are enabled and READ and PRECHARGE commands access the same bank. ak. Parameter applies when bank groups are disabled or READ and PRECHARGE commands access the same bank. al. tDAL = (tWR/tCK) + ( tRP/tCK). For each of the terms, if not already an integer, round up to the next integer. am. tCCDL is either for gapless consecutive READ or gapless consecutive WRITE commands an. tCCDS is either for gapless consecutive READ or RDTR (any combination), gapless consecutive WRITE, or gapless consecutive WRTR commands. ao. The min. value does not exceed 8 tCK ap. tRTW is not a device limit but determined by the system bus turnaround time. The difference between tWCK2DQO and tWCK2DQI shall be considered in the calculation of the bus turnaround time.

Rev. 1.0 /Nov. 2009 152 H5GQ1H24AFR aq. The WRITE latency WLmrs cna be set to 3 to 7 clocks. When the WRITE latency is set to small values (3 ~ 4 clocks), the input buffers are always on, reducing the latency but adding power. When the WRITE latency is set to larger values (5 ~ 7 clocks), the input buffers are turned on with the WRITE command, thus saving power. ar. Read data including CRC data must have been clocked out before entering self refresh or power down mode. as. Write data must have been written to the memory core and CRC data must have been clocked out before entering self refresh or power down mode. at. Time for WCK2CK training and data training not included. au. A maximum of 8 consecutive REFRESH commands can be posted to a GDDR5 SGRAM device, meaning that the maximum absolute interv al between any REFRESH command and the next REFRESH command is 9*tREFI. av. Replaces parameter tLK when PLL Fast Lock has been neabled prior to the PLL enable or reset. aw. Replaces parameter tLK when PLL Standby has been enabed and the WCK clock frequency has not charged while in standby mode. ax. The PLL standby time tSTDBY ismeasured from self refresh entry until after self refresh exit a subsequent PLL reset is given (with PLL Standby enabled)

changes in voltage or temperature) allowing the controller to take corrective action if necessary (e.g. slopes) does not lead to time delay errors in excess of the 5% of one UI. Tables 45, 46, and 47 below describe the minimum set of defined zones.

6.3 CLOCK-TO-DATA TIMING SENSITIVITY

Table 45. VDDQ Voltage Zone Table 46. VDD Voltage Zone a. Tcase(max) is the maximum specified operating temperature. Table 47. Tcase Temperature Zone

responsability for use of circuits described. No patent licenses are implied. Table 48. WCK-to-Data READ Timing Sensitivity to VDDQ = (tWCK2DQO(VDDQ(max)) ‐ tWCK2DQO(VDDQ(min))) / (VDDQ(max) ‐ VDDQ(min)). b. VDD(typ), Tcase = 85°C, worst‐case process corner. Table 49. WCK-to-Data READ Timing Sensitivity to VDD = (tWCK2DQO(VDD(max)) ‐ tWCK2DQO(VDD(min))) / (VDD(max) ‐ VDD(min)). b. VDDQ(typ), Tcase = 85°C, worst‐case process corner. Table 50. WCK-to-Data READ Timing Sensitivity to Tcase = (tWCK2DQO(Tcase(max)) ‐ tWCK2DQO(Tcase(min))) / (Tcase(max) ‐ Tcase(min)). b. VDDQ(typ), VDD(typ), worst‐case process corner.

responsability for use of circuits described. No patent licenses are implied. Tables 51, 52 and 53 below provide information for WRITE timings. Table 51. WCK-to-Data WRITE Timing Sensitivity to VDDQ = (tWCK2DQI(VDDQ(max)) ‐ tWCK2DQI(VDDQ(min))) / (VDDQ(max) ‐ VDDQ(min)). b. VDD(typ), Tcase = 85°C, worst‐case process corner. Table 52. WCK-to-Data WRITE Timing Sensitivity to VDD = (tWCK2DQI(VDD(max)) ‐ tWCK2DQI(VDD(min))) / (VDD(max) ‐ VDD(min)). b. VDDQ(typ), Tcase = 85°C, worst‐case process corner. Table 53. WCK-to-Data WRITE Timing Sensitivity to Tcase = (tWCK2DQI(Tcase(max)) ‐ tWCK2DQI(Tcase(min))) / (Tcase(max) ‐ Tcase(min)). b. VDDQ(typ), VDD(typ), worst‐case process corner.

responsability for use of circuits described. No patent licenses are implied. Figure 81. GDDR5 SGRAM 170ball BGA Ball-out MF=0

responsability for use of circuits described. No patent licenses are implied. Figure 82. GDDR5 SGRAM 170ball BGA Ball-out MF=1

responsability for use of circuits described. No patent licenses are implied. Table 54. Ball-out Description edge of CK. Address inputs are latched on the rising edge of CK and the rising edge of CK#. All latencies are referenced to CK. CK and CK# are externally terminated. data output. WCK01/WCK01# is associated with DQ0‐DQ15, DBI0#, DBI1#, EDC0 and EDC1. WCK23/WCK23# is associated with DQ16‐DQ31, DBI2#, DBI3#, EDC2 and EDC3. ACTIVE in any bank). CKE# must be maintained LOW throughout read and write accesses. value of the address and command inputs. with multiple ranks. CS# is considered part of the command code. sampled with the rising edge of CK#. DBI#2 is associated with DQ16‐DQ23, DBI#3 is associated with DQ24‐DQ31. DQ16‐DQ23, EDC3 is associated with DQ24‐DQ31. VddQ Supply I/O Power Supply. Isolated on the die for improved noise immunity. VssQ Supply I/O Ground: Isolated on the die for improved noise immunity. Vrefd Supply Reference Voltage for DQ, DBI#, and EDC pins. Vrefc Supply Reference Voltage for address and command pins. MF Reference Mirror Function: VDDQ CMOS input. Must be tied to power or ground.

responsability for use of circuits described. No patent licenses are implied. SEN Input Scan enable. VDDQ CMOS input. Must be tied to the ground when not in use. RESET# Low all ODTs are disabled.

responsability for use of circuits described. No patent licenses are implied. Figure 83. Byte Orientation in Clamshell Topology

responsability for use of circuits described. No patent licenses are implied. “Yes” indicates whether the mode register field controls termination for the signal. Table 55. Signals Affected by Termination Control Registers

responsability for use of circuits described. No patent licenses are implied. Figure 84. Package Dimensions Table 56. Package Height Parameters

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 163 H5GQ1H24AFR 7.4. MIRROR FUNCTION (MF) ENABLE and x16 MODE ENABLE The GDDR5 SGRAM provides a mirror function (MF) pin to change the physical location of the command, address, data, and WCK pins assisting in routing devices back to back. The MF ball should be tied directly to VSSQ or VDDQ depending on the control line orientation desired. The GDDR5 SGRAM can operate in a x32 mode or a x16 mode to allow a clamshell configuration with a point to point connection on the high speed data signal. The disabled pins in x16 mode should all be in a Hi‐Z state, non‐terminating. The x16 mode is detected at power up on the pin at location C‐13 which is EDC1 when configured to MF=0 and EDC2 when configured to MF=1. For x16 mode this pin is tied to VSSQ; the pin is part of the two bytes that are disabled in this mode and therefore not needed for EDC functionality. For x32 mode this pin is active and always terminated to VDDQ in the system or by the controller. The configuration is set with RESET# going High. Once the configuration has been set, it cannot be changed during normal operation. Usually the configuration is fixed in the system. Details of the x16 mode detection are depicted in Figure . A comparison of x32 mode and x16 mode systems is shown in Figure .

responsability for use of circuits described. No patent licenses are implied. Figure 85. Enabling x16 mode

responsability for use of circuits described. No patent licenses are implied. Figure 87. Example Channel Topologies

responsability for use of circuits described. No patent licenses are implied. Note 1: 32bit channel is shown as an example. Also applies with x16 on a 16bit channel. Figure 88. Example GDDR5 PCB Layout Topologies

responsability for use of circuits described. No patent licenses are implied. pin, SEN which is located at J‐10 of the 170 ball package. unwanted access commands are being executed prior to scan mode. has to make sure to mask those bits in the test program which are not wired in the system. occurs through device power‐down and then power‐up. mode (RESET#, MF, EDC0 and CS#) will be operating as normal when SEN is deasserted. Note: When the device is in scan mode, mirror function is disabled (MF=0) and none of the pins are remapped. Table 58. Boundary Scan Exit Order

10 H ‐42 2P ‐43 4 P ‐13 46 H ‐10 58 A ‐2

11 J ‐52 3 P ‐53 5 N ‐11 47 F ‐13 59 B ‐4

12 J ‐42 4 R ‐23 6 N ‐13 48 F ‐11 60 B ‐2

responsability for use of circuits described. No patent licenses are implied.

1. When SEN is asserted, no commands are to be executed by the GDDR5 SGRAM. This applies to both user

commands and manufacturing commands which may exist while RESET# is deasserted.

1. All scan functionality is valid only after the appropriate power‐up (Steps 1‐4 of initialization sequence).
2. In scan mode, all ODT will be disabled.

Table 59. Scan Pin Description and shift the data on the chain at logic HIGH. C‐2S O U T E D C 0 O u t p u t S c a n Output. disabled at logic LOW. Must be tied to VSSQ when not in use. required input logic level in scan mode. Table 60. Scan AC Electrical Characteristics

responsability for use of circuits described. No patent licenses are implied.

1. The parameter applies only when SEN is asserted.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 171 H5GQ1H24AFR Figure. 90 Scan Shift Timing tSES tSCS tSCS tSAC Scan Out bit 1 Scan Out bit 2 Scan Out bit 3 Scan Out bit 4 tSOH SCK SEN SOUT SSH SOE#

responsability for use of circuits described. No patent licenses are implied. Figure 91. Scan Initialization Sequence

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 173 H5GQ1H24AFR Figure. 92 Internal Block Diagram DQ2 Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D DQ1 DQ3 WCK01# SSH, Scan Shift Pin RESET# SCK, Scan Clock Pin CS# SOUT, Scan Out Pin EDC0 SEN, Scan Enable Pin SEN SOE#, Scan Output Enable Pin MF Pins under test Dedicated Scan D FF per signal under test Signals in scan chain: DQ[31:0], EDC[3:1], DBI#[3:0], WCK01, WCK01#, WCK23, WCK23#, RAS#, CAS#, WE#, CKE#, ABI#, A[7:0]*, CK, CK#, ZQ Note: A[7:0]* are multiplexed pins and represent A[12:8] and BA[3:0] Signals not in the scan chain: VDDQ, VSSQ, VDD, VSS, VREFx