H57V2562GFR-60C

H57V2562GFR-60C HYNIX | Alldatasheet

Document overview

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Technical content

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Aug. 2009 1 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O 256M (16Mx16bit) Hynix SDRAM Memory Memory Cell Array - Organized as 4banks of 4,194,304 x 16

Rev 1.0 / Aug. 2009 2 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series H57V2562GFR Document Title 256Mbit (16M x16) Synchronous DRAM

Revision History

Revision No. History Draft Date Remark 0.1 Preliminary Jun. 2009 1.0 Release Aug. 2009

Rev 1.0 / Aug. 2009 3 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series

DESCRIPTION

The Hynix H57V2562GFR Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for the con- sumer memory applications wh ich requires large memory density and high bandwidth. It is organized as 4banks of 4,194,304 x 16 I/O. Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK. The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randon-access operation. Read and write accesses to the Hynix Synchronous DRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. All inputs are LVTTL compatible. Devices will have a VDD and VDDQ supply of 3.3V (nominal).

Rev 1.0 / Aug. 2009 4 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series 256Mb Synchronous DRAM(16M x 16) FEATURES

• Standard SDRAM Protocol
• Internal 4bank operation
• Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V
• All device pins are compatible with LVTTL interface
• Low Voltage interface to reduce I/O power
• 8,192 Refresh cycles / 64ms
• Programmable CAS latency of 2 or 3
• Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
• Commercial Temp : 0oC ~ 70oC Operation
• Package Type : 54ball, 0.8mm pitch FBGA
• This product is in compliance with the directive pertaining of RoHS.

ORDERING INFORMATION

Note: 1. H57V2562GFR-XXC Series: Normal power & Commercial temp. 2. H57V2562GFR-XXL Series: Low Power & Commercial temp. Part Number Clock Frequency CAS Latency Power Voltage Organization Interface H57V2562GFR-60C 166MHz 3 Normal 3.3V 4Banks x 4Mbits x16 LVTTL H57V2562GFR-75C 133MHz 3 H57V2562GFR-60L 166MHz 3 Low PowerH57V2562GFR-75L 133MHz 3

Rev 1.0 / Aug. 2009 5 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series BALL CONFIGURATION

54 Ball

0.8mm Ball Pitch <Bottom View> 9 8 7 3 21 A B C D E F G H J 0.8mm Ball Pitch <Bottom View> 9 8 7 3 21 A B C D E F G H J H J B C D A G F E VSS DQ14 DQ12 DQ10 DQ8 UDQM A12 VSS DQ15 DQ13 DQ11 DQ9 NC CLK A11 VSSQ VDDQ VSSQ VDDQ VSS CKE VDDQ VSSQ VDDQ VSSQ VDD /CAS BA0 DQ0 DQ2 DQ4 DQ6 LDQM /RAS BA1 VDD DQ1 DQ3 DQ5 DQ7 /WE /CS A10 VDD 1 2 3 7 8 9 < Top View >

Rev 1.0 / Aug. 2009 6 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series 54_TSOPII Pin DESCRIPTIONS SYMBOL TYPE DESCRIPTION CLK INPUT Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE INPUT Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS INPUT Chip Select: Enables or disables all inputs except CLK, CKE and DQM BA0, BA1 INPUT Bank Address: Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A12 INPUT Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8 Auto-precharge flag: A10 RAS, CAS, WE INPUT Command Inputs: RAS, CAS and WE define the operation Refer function truth table for details LDQM, UDQM I/O Data Mask: Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ15 I/O Data Input / Output: Multiplexed data input / output pin VDD / VSS SUPPLY Power supply for internal circuits and input buffers VDDQ / VSSQ SUPPLY Power supply for output buffers NC - No connection : These pads should be left unconnected

Rev 1.0 / Aug. 2009 7 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 16 I/O Synchronous DRAM Internal Row Counter Column Pre Decoder Column Add Counter Self refresh logic & timer Sense AMP & I/O Gate I/O Buffer & Logic Address Register Burst Counter Mode Register State Machine Address Buffers Bank Select Column Active Row Active CAS Latency CLK CKE CS RAS CAS WE LDQM, UDQM BA1 BA0 A12 Row Pre Decoder Refresh DQ0 DQ15 X Decorders X Decoders X Decorders X Decorders Y decoerders 4M x16 Bank0 4M x16 Bank1 4M x16 Bank2 4M x16 Bank3 Memory Cell Array Data Out Control Burst Length Pipe Line Control

Rev 1.0 / Aug. 2009 8 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series ABSOLUTE MAXIMUM RATING Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION Note: 1. All voltages are referenced to VSS = 0V. 2. VIH(Max) is acceptable VDDQ + 2V for a pulse width with <= 3ns of duration. 3. VIL(min) is acceptable -2.0V for a pulse width with <= 3ns of duration. AC OPERATING TEST CONDITION (TA= 0 to 70oC, VDD=3.3±0.3V / VSS=0V) Note: 1. See Next Page Parameter Symbol Rating Unit Ambient Temperature T A 0 ~ 70 oC Storage Temperature T STG -55 ~ 125 oC Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current I OS 50 mA Power Dissipation P D 1W Parameter Symbol Min Max Unit Note Power Supply Voltage V DD, VDDQ 3.0 3.6 V 1 Input High Voltage V IH 2.0 V DDQ + 0.3 V 1, 2 Input Low Voltage V IL -0.3 0.8 V 1, 3 Parameter Symbol Value Unit Note AC Input High / Low Level Voltage V IH / VIL 2.4 / 0.4 V Input Timing Measurement Reference Level Voltage V trip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage V outref 1.4 V Output Load Capacitance for Access Time Measurement CL 50 pF 1

Rev 1.0 / Aug. 2009 9 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series CAPACITANCE (f=1MHz) DC CHARACTERRISTICS I (TA= 0 to 70oC) Note: 1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6 Parameter Pin Symbol Min Max Unit Input capacitance CLK CI1 2.0 4.0 pF A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE CI2 2.0 4.0 pF LDQM, UDQM CI3 2.0 4.0 pF Data input / output capacitance DQ0 ~ DQ15 CI/O 3.5 6.5 pF Parameter Symbol Min Max Unit Note Input Leakage Current I LI -1 1 uA 1 Output Leakage Current I LO -1 1 uA 2 Output High Voltage V OH 2.4 - V IOH = -4mA Output Low Voltage V OL - 0.4 V IOL = +4mA Z0 = 50 Ohom 50pF RT = 50 Ohom VTT = 1.4V Output AC Output Load Circuit 50pF RT = 50 Ohom VTT = 1.4V Output DC Output Load Circuit

Rev 1.0 / Aug. 2009 10 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series DC CHARACTERISTICS II (TA= 0 to 70oC) Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. H57V2562GFR-XXC Series: Normal, H57V2562GFR-XXL Series: Low Power Parameter Symbol Test Condition Speed (MHz) Unit Note 166 133 Operating Current IDD1 Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA 90 70 mA 1 Precharge Standby Current in Power Down Mode I DD2P CKE ≤ VIL(max), tCK = 15ns 2 mA IDD2PS CKE ≤ VIL(max), tCK = ∞ 2m A Precharge Standby Current in Non Power Down Mode I DD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V mA IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 8 Active Standby Current in Power Down Mode IDD3P CKE ≤ VIL(max), tCK = 15ns 5 mA IDD3PS CKE ≤ VIL(max), tCK = ∞ 5 Active Standby Current in Non Power Down Mode IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V mA IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 20 Burst Mode Op- erating Current IDD4 tCK ≥ tCK(min), IOL=0mA All banks active 100 80 mA 1 Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 160 140 mA 2 Self Refresh Current IDD6 CKE ≤ 0.2V Normal 2 mA 3 Low Power 1

Rev 1.0 / Aug. 2009 11 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. to the parameter. Parameter Speed (MHz) 166 133 Unit Note Min Max Min Max System Clock Cycle Time CL = 3 t CK3 6.0 1000 7.5 1000 ns CL = 2 t CK2 - 1000 10 1000 ns Clock High Pulse Width t CHW 2.5 - 2.5 - ns 1 Clock Low Pulse Width t CLW 2.5 - 2.5 - ns 1 Access Time From Clock CL = 3 t AC3 -5 . 4-5 . 4 ns 2 CL = 2 t AC2 ---6 ns 2 Data-out Hold Time t OH 2.0 - 2.5 - ns Data-Input Setup Time t DS 1.5 - 1.5 - ns 1 Data-Input Hold Time t DH 0.8 - 0.8 - ns 1 Address Setup Time t AS 1.5 - 1.5 - ns 1 Address Hold Time t AH 0.8 - 0.8 - ns 1 CKE Setup Time t CKS 1.5 - 1.5 - ns 1 CKE Hold Time t CKH 0.8 - 0.8 - ns 1 Command Setup Time t CS 1.5 - 1.5 - ns 1 Command Hold Time t CH 0.8 - 0.8 - ns 1 CLK to Data Output in Low-Z Time t OLZ 1.0 - 1.0 - ns CLK to Data Output in High-Z Time CL = 3 t OHZ3 2 . 75 . 42 . 75 . 4 n s CL = 2 t OHZ2 --3 6 n s

Rev 1.0 / Aug. 2009 12 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Note: 1. A new command can be given tRC after self refresh exit. Parameter Speed (MHz) 166 133 Unit Note Min Max Min Max RAS Cycle Time Operation t RC 60 - 63 - ns Auto Refresh t RRC 60 - 63 - ns RAS to CAS Delay t RCD 18 - 20 - ns RAS Active Time t RAS 42 100K 42 100K ns RAS Precharge Time t RP 18 - 20 - ns RAS to RAS Bank Active Delay t RRD 12 - 15 - ns CAS to CAS Delay t CCD 1-1- C L K Write Command to Data-In Delay t WTL 0 - 0 - CLK Data-in to Precharge Command t DPL 2-2- C L K Data-In to Active Command t DAL tDPL + tRP DQM to Data-Out Hi-Z t DQZ 2-2- C L K DQM to Data-In Mask t DQM 0-0- C L K MRS to New Command t MRD 2-2- C L K Precharge to Data Output High-Z CL = 3 t PROZ3 3-3- C L K CL = 2 t PROZ2 --2- C L K Power Down Exit Time t DPE 1-1- C L K Self Refresh Exit Time t SRE 1-1- C L K 1 Refresh Time t REF -6 4-6 4 m s

Rev 1.0 / Aug. 2009 13 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series BASIC FUNCTIONAL DESCRIPTION Mode Register B A 1 B A 0 A 1 2 A 1 1 A 1 0 A 9 A 8A 7A 6A 5A 4A 3A 2A 1A 0 0 0 0 0 0 OP Code 0 0 CAS Latency BT Burst Length OP Code A9 Write Mode 0B u r s t R e a d a n d B u r s t W r i t e

1 Burst Read and Single Write

A3 = 0 A3=1 00 0 1 1 00 1 2 2 01 0 4 4 01 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full page Reserved CAS Latency A6 A5 A4 CAS Latency 0 0 0 R e s e r v e d 0 0 1 R e s e r v e d 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 R e s e r v e d 1 1 0 R e s e r v e d 1 1 1 Reserved

Rev 1.0 / Aug. 2009 14 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series COMMAND TRUTH TABLE Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. see to Next page (DQM TRUTH TABLE) Function CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10 /AP BA Note Mode Register Set H X L L L L X Op Code No Operation H X L H H H X X Device Deselect H X H X X X X X Bank Active H X L L H H X Row Address V Read H X L H L H Col- umn L V Read with Autoprecharge H X L H L H X Col- umn H V Write H X L H L L X Col- umn L V Write with Autoprecharge H X L H L L X Col- umn H V Precharge All Banks H X L L H L X X H X Precharge selected Bank H X L L H L X X L V Burst stop H X L H H L X X DQM H X X V X 2 Auto Refresh H H L L L H X X Burst-Read Single-Write H X L L L H X A9 Pin High (Other Pins OP code) Self Refresh Entry H L L L L H X X Self Refresh Exit L H HX XX XX1 LHHH Precharge Power Down Entry HL HX XX XX LHHH Precharge Power Down Exit L H HX XX XX LHHH Clock Suspend Entry H L HX XX XX LVVV Clock Suspend Exit L H X X X

Rev 1.0 / Aug. 2009 15 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series DQM TRUTH TABLE Note 1. H: High Level, L: Low Level, X: Don't Care 2. Write DQM Latency is 0 CLK and Read DQM Latency is 2 CLK Function CKEn-1 CKEn LDQM UDQM Data Write/Output enable H X L L Data Mask/Output disable H X H H Lower byte write/Output enable, Upper byte mask/Output disable HXLH Lower byte Mask/Output disable, Upper byte write/Output enable HXHL

Rev 1.0 / Aug. 2009 16 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series CURRENT STATE TRUTH TABLE (Sheet 1 of 4) Current State Command Action Notes CS RAS CAS WE BA0/ BA1 Amax-A0 Description idle L L L L OP CODE Mode Register Set Set the Mode Register L L L H X X Auto or Self Refresh Start Auto or Self Refresh 5 L L H L BA X Precharge No Operation L L H H BA Row Add. Bank Activate Activate the specified bank and row LHL L B A Col Add. A10 Write/WriteAP ILLEGAL 4 LHLH B A Col Add. A10 Read/ReadAP ILLEGAL 4 L H H H X X No Operation No Operation 3 H X X X X X Device Deselect No Operation or Power Down 3 Row Active L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge Precharge 7 L L H H BA Row Add. Bank Activate ILLEGAL 4 LHL L B A Col Add. A10 Write/WriteAP Start Write : optional AP(A10=H) 6 LHLH B A Col Add. A10 Read/ReadAP Start Read : optional AP(A10=H) 6 L H H H X X No Operation No Operation H X X X X X Device Deselect No Operation Read L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 LLHL B A X P r e c h a r g e Termination Burst: Start the Precharge L L H H BA Row Add. Bank Activate ILLEGAL 4 LHL L B A Col Add. A10 Write/WriteAP Termination Burst: Start Write(optional AP) 8,9 LHLH B A Col Add. A10 Read/ReadAP Termination Burst: Start Read(optional AP) 8 L H H H X X No Operation Continue the Burst

Rev 1.0 / Aug. 2009 17 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series CURRENT STATE TRUTH TABLE (Sheet 2 of 4) Current State Command Action Notes CS RAS CAS WE BA0/ BA1 Amax-A0 Description Read H X X X X X Device Deselect Continue the Burst Write L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 LLHL B A X P r e c h a r g e Termination Burst: Start the Precharge 10 L L H H BA Row Add. Bank Activate ILLEGAL 4 LHL L B A Col Add. A10 Write/WriteAP Termination Burst: Start Write(optional AP) 8 LHL H B A Col Add. A10 Read/ReadAP Termination Burst: Start Read(optional AP) 8,9 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst Read with Auto Precharge L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 12 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst Write with Auto Precharge L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 12 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst

Rev 1.0 / Aug. 2009 18 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series CURRENT STATE TRUTH TABLE (Sheet 3 of 4) Current State Command Action Notes CS RAS CAS WE BA0/ BA1 Amax-A0 Description Precharging L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 LLHL B A X P r e c h a r g e No Operation: Bank(s) idle after tRP L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,12 LHHH X X N o O p e r a t i o n No Operation: Bank(s) idle after t RP H X X X X X Device Deselect No Operation: Bank(s) idle after tRP Row Activating L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,11,1 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,12 LHHH X X N o O p e r a t i o n No Operation: Row Active after t RCD H X X X X X Device Deselect No Operation: Row Active after tRCD Write Recovering L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,13 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP Start Write: Optional AP(A10=H) L H L H BA Col Add. A10 Read/ReadAP Start Read: Optional AP(A10=H) 9 LHHH X X N o O p e r a t i o n No Operation: Row Active after t DPL

Rev 1.0 / Aug. 2009 19 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series CURRENT STATE TRUTH TABLE (Sheet 4 of 4) Current State Command Action Notes CS RAS CAS WE BA0/ BA1 Amax-A0 Description Write Recovering H X X X X X Device Deselect No Operation: Row Active after tDPL Write Recovering with Auto Precharge L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,13 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,9,12 LHHH X X N o O p e r a t i o n No Operation: Precharge after t DPL H X X X X X Device Deselect No Operation: Precharge after tDPL Refreshing L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 13 L L H H BA Row Add. Bank Activate ILLEGAL 13 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 13 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 13 LHHH X X N o O p e r a t i o n No Operation: idle after t RC H X X X X X Device Deselect No Operation: idle after tRC Mode Register Accessing L L L L OP CODE Mode Register Set ILLEGAL 13 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 13 L L H H BA Row Add. Bank Activate ILLEGAL 13 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 13 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 13 LHHH X X N o O p e r a t i o n No Operation: idle after 2 clock cycles H X X X X X Device Deselect No Operation: idle after 2 clock cycles

Rev 1.0 / Aug. 2009 20 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if t RCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don 't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks.

Rev 1.0 / Aug. 2009 21 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series CKE Enable(CKE) Truth TABLE (Sheet 2 of 1) Current State CKE Command Action NotesPrevious Cycle Current Cycle CS RAS CAS WE BA0, BA1 ADDR Self Refresh H X XX XXX X I N V A L I D 1 LH H X X X X X Exit Self Refresh with Device Deselect 2 LH L H H H X X Exit Self Refresh with No Operation 2 LH L H H L X X I L L E G A L 2 LH L H L X X X I L L E G A L 2 LH L L X X X X I L L E G A L 2 L L XX XXX X M a i n t a i n S e l f R e f r e s h Power Down H X XX XXX X I N V A L I D 1 LH HX XXX X Power Down mode exit, all banks idle 2 LHHHX X LH L LX X X X ILLEGAL 2XL X X X XXLX X L L XX XXX X M a i n t a i n P o w e r D o w n M o d e All Banks Idle HH H X X X Refer to the idle State section of the Current State Truth Table HH L H X X 3 HH L L H X 3 HH L L L H X X A u t o R e f r e s h H H L L L L OP CODE Mode Register Set 4 HL H X X X Refer to the idle State section of the Current State Truth Table HL L H X X 3 HL L L H X 3 HL L L L H X X E n t r y S e l f R e f r e s h 4 H L L L L L OP CODE Mode Register Set L X XX XXX X P o w e r D o w n 4

Rev 1.0 / Aug. 2009 22 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series CKE Enable(CKE) Truth TABLE (Sheet 2 of 2) Note : 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200usec. Current State CKE Command Action NotesPrevious Cycle Current Cycle CS RAS CAS WE BA0, BA1 ADDR Any State other than listed above H H XX XXX X Refer to operations of the Current State Truth Table H L XX XXX X Begin Clock Suspend next cycle L H XX XXX X Exit Clock Suspend next cycle L L XX XXX X M a i n t a i n C l o c k S u s p e n d

Rev 1.0 / Aug. 2009 23 111 Synchronous DRAM Memory 256Mbit H57V2562GFR Series

PACKAGE INFORMATION

54 Ball FBGA 0.8mm pitch (Size 8.0mm x 8.0mm) Unit [mm]0.8±0.1 Bottom View 0.35 +0.025/- 0.05 0.80 Typ. 0.80 Typ. 1.0 max 0.45 +/- 0.05 A1 INDEX MARK 1.60 8.00 Typ. 0.8± 0.1 8.00 Typ. 6.4 6.4