H57V1262GFR-50X

H57V1262GFR-50X HYNIX | Alldatasheet

Document overview

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Technical content

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Aug. 2009 1 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM

Revision History

Revision No. History Draft Date Remark 0.1 Initial Draft Jul. 2009 Preliminary 1.0 Release Aug. 2009

Rev. 1.0 / Aug. 2009 2 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series

DESCRIPTION

The Hynix H57V1262GFR series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applica- tions which require wide data I/O and high bandwidth. H57V1262GFR series is organized as 4banks of 2,097,152 x 16. H57V1262GFR is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), an d the burst count sequence(se- quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re- stricted by a '2N' rule)

FEATURES

• This product is in compliance with the directive pertaining of RoHS.

ORDERING INFORMATION

1. H57V1262GFR-XXC Series: Normal power, Commercial Temp.(0oC to 70oC) 2. H57V1262GFR-XXI Series: Normal power, Industrial Temp. (-40oC to 85oC) 3. H57V1262GFR-XXL Series: Low power, Commercial Temp.(0oC to 70oC) 4. H57V1262GFR-XXJ Series: Low power, Industrial Temp. (-40oC to 85oC) Part No. Clock Frequency Organization Interface Package H57V1262GFR-50X 200MHz 4Banks x 2Mbits x16 LVTTL 54 Ball FBGA H57V1262GFR-60X 166MHz H57V1262GFR-70X 143MHz H57V1262GFR-75X 133MHz

• Voltage: VDD and VDDQ 3.3V supply voltage
• All device pins are compatible with LVTTL interface
• 54 Ball FBGA (Lead or Lead Free Package)
• All inputs and outputs refere nced to positive edge of system clock
• Data mask function by UDQM, LDQM
• Internal four banks operation
• Auto refresh and self refresh
• 4096 Refresh cycles / 64ms
• Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency; 2, 3 Clocks
• Burst Read Single Write operation
• Operation temperature HY5V26F(L)F(P)-XX Series: 0 ~ 70oC HY5V26F(L)F(P)-X(I) Series: -40 ~ 85oC

Rev. 1.0 / Aug. 2009 3 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series BALL CONFIGURATION

54 Ball

0.8mm Ball Pitch <Bottom View> 9 8 7 3 21 A B C D E F G H J 0.8mm Ball Pitch <Bottom View> 9 8 7 3 21 A B C D E F G H J H J B C D A G F E VSS DQ14 DQ12 DQ10 DQ8 UDQM NC VSS DQ15 DQ13 DQ11 DQ9 NC CLK A11 VSSQ VDDQ VSSQ VDDQ VSS CKE VDDQ VSSQ VDDQ VSSQ VDD /CAS BA0 DQ0 DQ2 DQ4 DQ6 LDQM /RAS BA1 VDD DQ1 DQ3 DQ5 DQ7 /WE /CS A10 VDD 1 2 3 7 8 9 < Top View >

Rev. 1.0 / Aug. 2009 4 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Synchronous DRAM Internal Row Counter Column Pre Decoder Column Add Counter Self refresh logic & timer Sense AMP & I/O Gate I/O Buffer & Logic Address Register Burst Counter Mode Register State Machine Address Buffers Bank Select Column Active Row Active CAS Latency CLK CKE CS RAS CAS WE U/LDQM BA1 BA0 A11 Row Pre Decoder Refresh DQ0 DQ15 X-Decoder X-Decoder X-Decoder X-Decoder Y-Decoder 2Mx16 BANK 0 2Mx16 BANK 1 2Mx16 BANK 2 2Mx16 BANK 3 Memory Cell Array Data Out Control Pipe Line Control

Rev. 1.0 / Aug. 2009 5 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0000 O P C o d e 00 C A S L a t e n c y B T B u r s t L e n g t h

0B u r s t R e a d a n d B u r s t W r i t e

1 Burst Read and Single Write

0 Sequential

1 Interleave

A3 = 0 A3=1 00 0 11 00 1 22 01 0 4 4 01 1 88 10 0 Reserved Reserved 10 1 Reserved Reserved 1 10 Reserved Reserved 1 11 Full Page Reserved CAS Latency A6 A5 A4 CAS Latency 0 0 0 R e s e r v e d 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 R e s e r v e d 1 1 0 R e s e r v e d 1 1 1 Reserved

Rev. 1.0 / Aug. 2009 6 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series ABSOLUTE MAXIMUM RATING Notes: 1. Commercial (0 ~ 70oC) 2. Industrial (-40 ~ 85oC) DC OPERATING CONDITION Notes: 1. All voltages are referenced to VSS = 0V 2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration AC OPERATING TEST CONDITION (VDD=3.3±0.3V, VSS=0V) Note: 1. Parameter Symbol Rating Unit Note Ambient Temperature T A 0 ~ 70oC oC 1 -40 ~ 85oC oC 2 Storage Temperature T STG -55 ~ 125 oC Voltage on Any Pin relative to VSS V IN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS V DD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current I OS 50 mA Power Dissipation P D 1W Soldering Temperature / Time T SOLDER 260 / 10 oC / Sec Parameter Symbol Min. Typ Max Unit Note Power Supply Voltage V DD, VDDQ 3.0 3.3 3.6 V 1 Input High Voltage V IH 2.0 3.0 V DDQ + 0.3 V 1, 2 Input Low Voltage V IL -0.3 - 0.8 V 1, 3 Parameter Symbol Value Unit Note AC Input High / Low Level Voltage V IH / VIL 2.4 / 0.4 V Input Timing Measurement Reference Level Voltage V trip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage V outref 1.4 V Output Load Capacitance for Access Time Measurement CL 50 pF 1 Z0 = 50 Output Output Vtt = 1.4V 50pF RT = 50 Vtt = 1.4V 50pF DC Output Load Circuit AC Output Load Circuit RT = 500 Ω Ω Ω

Rev. 1.0 / Aug. 2009 7 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series CAPACITANCE (f=1MHz, VDD=3.3V) DC CHARACTERISTICS I Notes: 1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6 Parameter Pin Symbol Min Max Unit Input capacitance CLK CI1 2.0 4.0 pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, LDQM, UDQM CI2 2.0 4.0 pF Data input / output capacitance DQ0 ~ DQ15 CI/O 3.0 5.5 pF Parameter Symbol Min Max Unit Note Input Leakage Current I LI -1 1 uA 1 Output Leakage Current I LO -1 1 uA 2 Output High Voltage V OH 2.4 - V I OH = -2mA Output Low Voltage V OL -0 . 4 V I OL = +2mA

Rev. 1.0 / Aug. 2009 8 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series DC CHARACTERISTICS II Notes: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. H57V1262GTR-XXC Series: Normal Power H57V1262GTR-XXL Series: Low Power Parameter Symbol Test Condition Speed Unit Note 5 6 7 H Operating Current I DD1 Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA 1 0 0 8 07 07 0 m A1 Precharge Standby Current in Power Down Mode IDD2P CKE ≤ VIL(max), tCK = 15ns 2 mA IDD2PS CKE ≤ VIL(max), tCK = ∞ 2m A Precharge Standby Current in Non Power Down Mode IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ V DD-0.2V or ≤ 0.2V mA IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. Active Standby Current in Power Down Mode IDD3P CKE ≤ VIL(max), tCK = 15ns 5 mA IDD3PS CKE ≤ VIL(max), tCK = ∞ 5 Active Standby Current in Non Power Down Mode IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ V DD-0.2V or ≤ 0.2V mA IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. Burst Mode Operating Cur- rent IDD4 tCK ≥ tCK(min), IOL=0mA All banks active 120 100 100 100 mA 1 Auto Refresh Current I DD5 tRC ≥ tRC(min), All banks active 210 200 190 190 mA 2 Self Refresh Current I DD6 CKE ≤ 0.2V Normal 2 mA 3Low power 800 uA

Rev. 1.0 / Aug. 2009 9 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Notes: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Parameter Sym- bol 5 6 7 H Unit Note Min Max Min Max Min Max Min Max System Clock Cycle Time CL = 3 t CK3 5.0 1000 6.0 1000 7.0 1000 7.5 1000 ns CL = 2 t CK2 --- 1 0 ns Clock High Pulse Width t CHW 1 . 7 5 -2 . 0-2 . 0-2 . 5- ns 1 Clock Low Pulse Width t CLW 1 . 7 5 -2 . 0-2 . 0-2 . 5- ns 1 Access Time From Clock CL = 3 t AC3 -4 . 5-5 . 4-5 . 4-5 . 4 ns Data-out Hold Time t OH 2.0 - 2.0 - 2.5 - 2.7 - ns Data-Input Setup Time t DS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Data-Input Hold Time t DH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 Address Setup Time t AS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Address Hold Time t AH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 CKE Setup Time t CKS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 CKE Hold Time t CKH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 Command Setup Time t CS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Command Hold Time t CH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 CLK to Data Output in Low-Z Time t OLZ 1.0 - 1.0 - 1.5 - 1.5 - ns CLK to Data Output in High-Z Time CL = 3 t OHZ3 -4 . 5-5 . 4-5 . 4-5 . 4 n s

Rev. 1.0 / Aug. 2009 10 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Note: 1. A new command can be given tRRC after self refresh exit. Parameter Symbol 5 6 7 H Uni t Not eMin Max Min Max Min Max Min Max RAS Cycle Time Operation t RC 55 - 60 - 63 - 63 - ns RAS Cycle Time Auto Refresh tRRC 55 - 60 - 63 - 63 - ns RAS to CAS Delay t RCD 15 - 18 - 20 - 20 - ns RAS Active Time t RAS 38.7 100K 42 100K 42 100K 42 120 K ns RAS Precharge Time t RP 15 - 18 - 20 - 20 - ns RAS to RAS Bank Active Delay t RRD 10 - 12 - 14 - 15 - ns CAS to CAS Delay t CCD 1-1-1-1 - C L K Write Command to Data-In Delay tWTL 0 -0 -0 -0 - C L K Data-in to Precharge Command t DPL 2-2-2-2 - C L K Data-In to Active Command t DAL tDPL + tRP DQM to Data-Out Hi-Z t DQZ 2-2-2-2 - C L K DQM to Data-In Mask t DQM 0-0-0-0 - C L K MRS to New Command t MRD 2-2-2-2 - C L K Precharge to Data Output High-Z CL = 3 t PROZ3 3-3-3-3 - C L K Power Down Exit Time t DPE 1-1-1-1 - C L K Self Refresh Exit Time t SRE 1-1-1-1 - C L K 1 Refresh Time t REF -6 4-6 4-6 4- 6 4 m s

Rev. 1.0 / Aug. 2009 11 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series COMMAND TRUTH TABLE Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/AP BA Note Mode Register Set H X L L L L X OP code No Operation H X HX XX XX LHHH Bank Active H X L L H H X RA V Read HX L H L H X C A L V Read with Autoprecharge H Write HX L H L L X C A L V Write with Autoprecharge H Precharge All Banks HX L L H L X X HX Precharge selected Bank LV Burst Stop H X L H H L X X DQM H X V X Auto Refresh H H L L L H X X Burst-Read-Single-WRITE H X L L L L X A9 ball High (Other balls OP code) MRS Mode Self Refresh1 Entry H L L L L H X X Exit L H HX XX X LHHH Precharge power down Entry H L HX XX X X LHHH Exit L H HX XX X LHHH Clock Suspend Entry H L HX XX X XLVVV Exit L H X X

Rev. 1.0 / Aug. 2009 12 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series

PACKAGE INFORMATION

54 Ball FBGA 8.0mm x 8.0mm Unit [mm]0.8±0.1 Bottom View 0.35 +0.025/- 0.05 0.80 Typ. 0.80 Typ. 1.0 max 0.45 +/- 0.05 A1 INDEX MARK 1.60 8.00 Typ. 0.8± 0.1 8.00 Typ. 6.4 6.4