H55S2562JFR-75M

H55S2562JFR-60M HYNIX | Alldatasheet

Document overview

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Technical content

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.1 / July. 2009 1 256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256M (16Mx16bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x16

Rev 1.1 / July. 2009 2 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Document Title 4Bank x 4M x 16bits Synchronous DRAM

Revision History

Revision No. History Draft Date Remark

0.1 Initial Draft May 2008 Preliminary

0.2 IDD Specification updated May 2008 Preliminary

1.0 The final version Nov. 2008 1.1 Omit a typo in package information July. 2009

Rev 1.1 / July. 2009 3 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series

DESCRIPTION

The Hynix H55S2562JFR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. The Hynix 256M Mobile SDRAM is 268,435,456-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 4,194,304x16. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK. The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is ini- tiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random- access operation. Read and write accesses to the Hynix Mobile SDRAMs are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule). The Hynix Mobile SDR also provides for special programmable options including Partial Array Self Refresh of full array, half array, quarter array Temperature Compensated Self Refresh of 45 or 85 degrees oC. The Hynix Mobile SDR has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically adjust refresh rate according to temperature without external EMRS command. Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power reduction by removing power to the memory array within each Mobile SDR. By using this feature, the system can cut off almost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility. All inputs are LV-CMOS compatible. Devices will have a V DD and V DDQ supply of 1.8V (nominal).

Rev 1.1 / July. 2009 4 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series INFORMATION for Hynix KNOWN GOOD DIE With the advent of Multi-Chip package (MCPs), Package on Package (PoP) and system in a package (SiP) applications, customer demand for Known Good Die (KGD) has increased. Requirements for smaller form factors and higher memory densities are fueling the need for Wafer-level memory solu- tions due to their superior flexibility. Hynix Known Good Die (KGD) products can be used in packaging technologies such as systems-in-a-package (SIPs) and multi-chip packages (MCPs) to reduce the board area required, making them ideal for hand-held PCs, and many other portable digital applications. Hynix Mobile DRAM will be able to continue its constant effort of enabling the Advanced package products of all appli- cation customers. - Please Contact Hynix Office for Hynix KGD product availability and informations.

Rev 1.1 / July. 2009 5 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series

FEATURES

• Standard SDRAM Protocol
• Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)
• MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write operation, a different bank is activated and burst Read or Write for that bank is performed - During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
• Power Supply Voltage: V DD = 1.8V, V DDQ = 1.8V
• LVCMOS compatible I/O Interface
• Low Voltage interface to reduce I/O power
• Programmable burst length: 1, 2, 4, 8 or full page
• Programmable Burst Type: sequential or interleaved
• Programmable CAS latency of 3 or 2
• Programmable Drive Strength
• Low Power Features - Programmable PASR(Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - Programmable DS (Drive Strength) - Deep Power Down Mode
• Operating Temperature - Mobile Temp.: -30 oC ~ 85 oC
• Package Type - 54ball FBGA, 0.8mm pitch, 8mm x 8mm, t=1.0mm max
• This product is in compliance with the directive pertaining of RoHS.

Rev 1.1 / July. 2009 6 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series 256Mb Mobile SDR SDRAM ORDERING INFORMATION Part Number Clock Frequency CAS Latency Organization Interface Operating temperature 54Ball FBGA H55S2562JFR-60M 166MHz 3 4banks x 4Mb x 16 LVCMOS Mobile Temp (-30 oC ~ 85 oC) Lead & Halogen Free H55S2562JFR-75M 133MHz 3 H55S2562JFR-A3M 105MHz 3

Rev 1.1 / July. 2009 7 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series BALL DESCRIPTION 91 2 3 4 6 7 8 TOP VIEW VSS DQ15 VSSQ VDDQ DQ0 VDD DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 DQ8 NC VSS VDD LDQM DQ7 UDQM CLK CKE /CAS /RAS /WE A12 A11 A9 BA0 BA1 /CS A8 A7 A6 A0 A1 A10 VSS A5 A4 A3 A2 VDD A B C D E F G H J Top view

Rev 1.1 / July. 2009 8 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series BALL DESCRIPTION SYMBOL TYPE DESCRIPTION CLK INPUT Clock: The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE INPUT Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one of the states among (deep) power down, suspend or self refresh CS INPUT Chip Select: Enables or disables all inputs except CLK, CKE, UDQM and LDQM BA0, BA1 INPUT Bank Address: Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A12 INPUT Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8 Auto-precharge flag: A10 RAS , CAS , WE INPUT Command Inputs: RAS , CAS and WE define the operation Refer function truth table for details UDQM, LDQM INPUT Data Mask: Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ15 I/O Data Input/Output: Multiplexed data input/output pin VDD /V SS SUPPLY Power supply for internal circuits VDDQ /V SSQ SUPPLY Power supply for output buffers NC - No connection

Rev 1.1 / July. 2009 9 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series ABSOLUTE MAXIMUM RATING DC OPERATING CONDITION (T A= -30 to 85 oC) Note: 1. All Voltages are referenced to V SS = 0V 2. V DDQ must not exceed the level of V DD AC OPERATING TEST CONDITION (TA= -30 to 85 oC, V DD = 1.8V, V SS = 0V) Parameter Symbol Rating Unit Ambient Temperature TA -30 ~ 85 oC Storage Temperature TSTG -55 ~ 125 oC Voltage on Any Pin relative to V SS VIN , V OUT -1.0 ~ 2.6 V Voltage on V DD relative to V SS VDD -1.0 ~ 2.6 V Voltage on V DDQ relative to V SS VDDQ -1.0 ~ 2.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Soldering Temperature . Time TSOLDER 260 . 20 oC . Sec Parameter Symbol Min Typ Max Unit Note Power Supply Voltage VDD 1.7 1.8 1.95 V 1 Power Supply Voltage VDDQ 1.7 1.8 1.95 V 1, 2 Input High Voltage VIH 0.8*V DDQ - VDDQ+ 0.3 V 1, 2 Input Low Voltage V IL -0.3 - 0.3 V 1, 2 Parameter Symbol Value Unit AC Input High/Low Level Voltage VIH / V IL 0.9*V DDQ /0.2 V Input Timing Measurement Reference Level Voltage Vtrip 0.5*V DDQ V Input Rise/Fall Time tR / t F 1 ns Output Timing Measurement Reference Level Voltage Voutref 0.5*V DDQ V Output Load Capacitance for Access Time Measurement CL 30 pF

Rev 1.1 / July. 2009 10 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series CAPACITANCE (T A= 25 oC, f=1MHz ) DC CHARACTERRISTICS I (T A= -30 to 85 oC) Note: 1. V IN = 0 to 1.8V. All other pins are not tested under VIN =0V. 2. D OUT is disabled. V OUT = 0 to 1.95V. 3. I OUT = - 0.1mA 4. I OUT = + 0.1mA Parameter Pin Symbol 6/H Unit Min Max Input capacitance CLK CI1 2 4.0 pF A0~A12, BA0, BA1, CKE, CS , RAS , CAS , WE , UDQM, LDQM CI2 2 4.0 pF Data input/output capacitance DQ0 ~ DQ15 CI/O 2.0 4.5 pF Parameter Symbol Min Max Unit Note Input Leakage Current ILI -1 1 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH VDDQ -0.2 - V 3 Output Low Voltage VOL - 0.2 V 4

Rev 1.1 / July. 2009 11 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series DC CHARACTERISTICS II (TA= -30 to 85 oC) Note: 1. I DD1 and I DD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. See the tables of next page for more specific I DD6 current values. Parameter Symbol Test Condition Speed Unit Note 166MHz 133MHz 105MHz Operating Current I DD1 Burst length=1, One bank active t RC ≥ t RC (min), I OL =0mA 50 40 40 mA 1 Precharge Standby Current in Power Down Mode I DD2P CKE ≤ V IL (max), t CK = min 0.3 mA I DD2PS CKE ≤ V IL (max), t CK = ∞ 0.3 mA Precharge Standby Current in Non Power Down Mode I DD2N CKE ≥ V IH (min), CS ≥ V IH (min), tCK = min, Input signals are changed one time during 2clks. All other pins ≥ V DD -0.2V or ≤ 0.2V mA I DD2NS CKE ≥ V IH (min), t CK = ∞ Input signals are stable. 1 Active Standby Current in Power Down Mode I DD3P CKE ≤ V IL (max), t CK = min 3 mA I DD3PS CKE ≤ V IL (max), t CK = ∞ 3 Active Standby Current in Non Power Down Mode I DD3N CKE ≥ V IH (min), CS ≥ V IH (min), tCK = min, Input signals are changed one time during 2clks. All other pins ≥ V DD -0.2V or ≤ 0.2V mA I DD3NS CKE ≥ V IH (min), t CK = ∞ Input signals are stable. 5 Burst Mode Operating Current I DD4 t CK ≥ t CK (min), I OL =0mA All banks active 55 45 45 mA 1 Auto Refresh Current I DD5 tRFC ≥ t RFC (min), 70 mA Self Refresh Current I DD6 CKE ≤ 0.2V See Next Page mA 2 Standby Current in Deep Power Down Mode I DD7 See p.50~51 10 uA 3

Rev 1.1 / July. 2009 12 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series DC CHARACTERISTICS III - Low Power (I DD6 ) Notes: 1. VDD / VDDQ = 1.8V 2. Related numerical values in this 45 oC are examples for reference sample value only. 3. With a on-chip temperature sensor of Mobile memory, auto temperature compensated self refresh will automatically adjust the in- terval of self-refresh operation according to ambient temperature variations. Temp. (oC) Memory Array Unit

4 Banks 2 Banks 1 Bank

Rev 1.1 / July. 2009 13 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Note: 1. Assume t R / t F (input rise and fall time) is 1ns. If t R & t F> 1ns, then [(t R+t F)/2-1]ns should be added to the parameter. to the parameter. 3. Output Load: 30pF+No termination

• AC high level input voltage / low level input voltage: 1.6 / 0.2V
• Input timing measurement reference level: 0.9V
• Transition time (input rise and fall time): 0.5ns
• Output timing measurement reference level: 0.9V
• Output load: CL = 30pF Parameter Symbol 166MHz 133MHz 105MHz Unit Note Min Max Min Max Min Max System Clock Cycle Time CAS Latency=3 t CK3 6.0 1000 7.5 1000 9.5 1000 ns CAS Latency=2 t CK2 12 1000 12 1000 15 1000 ns Clock High Pulse Width t CHW 2.0 - 2.5 - 3.0 - ns 1 Clock Low Pulse Width t CLW 2.0 - 2.5 - 3.0 - ns 1 Access Time From Clock CAS Latency=3 t AC3 - 5.4 - 5.4 - 5.4 ns 2, 3 CAS Latency=2 t AC2 - 6.0 - 8.0 - 10 ns 2, 3 Data-out Hold Time t OH 2.6 - 2.6 - 2.6 - ns 3 Data-Input Setup Time t DS 2.0 - 2.0 - 3.0 - ns 1 Data-Input Hold Time t DH 1.0 - 1.0 - 1.5 - ns 1 Address Setup Time t AS 2.0 - 2.0 - 3.0 - ns 1 Address Hold Time t AH 1.0 - 1.0 - 1.5 - ns 1 CKE Setup Time t CKS 2.0 - 2.0 - 3.0 - ns 1 CKE Hold Time t CKH 1.0 - 1.0 - 1.5 - ns 1 Command Setup Time t CS 2.0 - 2.0 - 3.0 - ns 1 Command Hold Time t CH 1.0 - 1.0 - 1.5 - ns 1 CLK to Data Output in Low-Z Time t OLZ 1.0 - 1.0 - 1.0 - ns CLK to Data Output in High-Z Time CAS Latency=3 t OHZ3 5.4 6.0 7.0 ns CAS Latency=2 t OHZ2 6.0 8.0 10 ns Output Z = 50 ΩΩ ΩΩ 30pF Output Load Output tOH tAC tSETUP tHOLD tCH tCL tCK 1.6V 0.9V 0.2V 1.6V 0.9V 0.2V Input CLK

Rev 1.1 / July. 2009 14 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter Symbol 166MHz 133MHz 105MHz Unit Note Min Max Min Max Min Max RAS Cycle Time t RC 60 - 72.5 - 90 - ns RAS to CAS Delay t RCD 18 - 22.5 - 28.5 - ns RAS Active Time t RAS 50 100K 50 100K 60 100K ns RAS Precharge Time t RP 18 - 22.5 - 28.5 - ns RAS to RAS Bank Active Delay t RRD 12 - 15 - 19 - ns AUTO REFRESH Period t RFC 72 - 72 - 72 - ns CAS to CAS Delay t CCD 1 - 1 - 1 - CLK Write Command to Data-In Delay t WTL 0 - 0 - 0 - CLK Data-in to Precharge Command t DPL 2 - 2 - 2 - CLK Data-In to Active Command t DAL tDPL +t RP DQM to Data-Out Hi-Z t DQZ 2 - 2 - 2 - CLK DQM to Data-In Mask t DQM 0 - 0 - 0 - CLK MRS to New Command t MRD 2 - 2 - 2 - CLK Precharge to Data Output High-Z CAS Latency=3 t PROZ3 3 - 3 - 3 - CLK CAS Latency=2 t PROZ2 2 - 2 - 2 - CLK Power Down Exit Time t DPE 1CLK tCKS 1CLK tCKS 1CLK tCKS - CLK Self Refresh Exit Time t XSR 112.5 - 112.5 - 112.5 - ns Refresh Time t REF - 64 - 64 - 64 ms

Rev 1.1 / July. 2009 15 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 16 I/O Mobile Synchronous DRAM Sense AMP & I/O Gate Output Buffer & Logic Address Register Mode Register State MachineAddress Buffers Bank Select Row Active CAS Latency CLK CKE /CS /RAS /CAS /WE LDQM, UDQM BA1 BA0 A12 Refresh DQ0 DQ15 Data Out Control Burst Length Extended Mode Register Self refresh logic & timer Internal Row Counter Row Pre Decoder Column Pre Decoder Column Add Counter Burst Counter Column Active Row decoders Row decoders Column decoders 4Mx16 Bank0 4Mx16 Bank1 4Mx16 Bank2 4Mx16 Bank3 Memory Cell Array Row decoders PASR

Rev 1.1 / July. 2009 16 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 OP Code 0 0 CAS Latency BT Burst Length OP Code A9 Write Mode

0 Burst Read and Burst Write

1 Burst Read and Single Write

0 Sequential

1 Interleave

A3 = 0 A3=1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full page Reserved CAS Latency A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved

Rev 1.1 / July. 2009 17 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series BASIC FUNCTIONAL DESCRIPTION (Continued) Extended Mode Register BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 0 0 0 0 DS 0 0 PASR DS (Driver Strength) A7 A6 A5 Driver Strength 0 0 0 Full 0 0 1 1/2 Strength 0 1 0 1/4 Strength 0 1 1 Reserved 1 0 0 3/4 Strength PASR (Partial Array Self Refresh) A2 A1 A0 Self Refresh Coverage 0 0 0 All Banks 0 0 1 Half of Total Bank (BA1=0 or Bank 0,1) 0 1 0 Quarter of Total Bank (BA1=BA0=0 or Bank 0) 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Half of Bank 0(Bank 0 and Row Address MSB=0) 1 1 0 Quarter of Bank 0(Bank 0 and Row Address 2 MSBs=0) 1 1 1 Reserved

Rev 1.1 / July. 2009 18 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series COMMAND TRUTH TABLE Note: 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set. Function CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10 /AP BA Note Mode Register Set H X L L L L X Op Code 2 Extended Mode Register Set H X L L L L X Op Code 2 No Operation H X L H H H X X Device Deselect H X H X X X X X Bank Active H X L L H H X Row Address V Read H X L H L H Column L V Read with Autoprecharge H X L H L H X Column H V Write H X L H L L X Column L V Write with Autoprecharge H X L H L L X Column H V Precharge All Banks H X L L H L X X H X Precharge selected Bank H X L L H L X X L V Burst stop H X L H H L X X Data Write/Output Enable H X X X X Data Mask/Output Disable H X X V X Auto Refresh H H L L L H X X Self Refresh Entry H L L L L H X X Self Refresh Exit L H H X X X X X 1 L H H H Precharge Power Down Entry H L H X X X X X L H H H Precharge Power Down Exit L H H X X X X X L H H H Clock Suspend Entry H L H X X X X X L V V V Clock Suspend Exit L H X X X Deep Power Down Entry H L L H H L X X Deep Power Down Exit L H X X X

Rev 1.1 / July. 2009 19 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series CURRENT STATE TRUTH TABLE (Sheet 1 of 4) Current State Command Action Notes CS RAS CAS WE BA0/ BA1 Amax -A0 Description Idle L L L L OP CODE Mode Register Set Set the Mode Register 14 L L L H X X Auto or Self Refresh Start Auto or Self Refresh 5 L L H L BA X Precharge No Operation L L H H BA Row Add. Bank Activate Activate the specified bank and row L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4 L H H H X X No Operation No Operation 3 H X X X X X Device Deselect No Operation or Power Down 3 Row Active L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge Precharge 7 L L H H BA Row Add. Bank Activate ILLEGAL 4 L H L L BA Col Add. A10 Write/WriteAP Start Write: optional AP(A10=H) 6 L H L H BA Col Add. A10 Read/ReadAP Start Read: optional AP(A10=H) 6 L H H H X X No Operation No Operation H X X X X X Device Deselect No Operation Read L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge Termination Burst: Start the Precharge L L H H BA Row Add. Bank Activate ILLEGAL 4 L H L L BA Col Add. A10 Write/WriteAP Termination Burst: Start Write(optional AP) 8,9 L H L H BA Col Add. A10 Read/ReadAP Termination Burst: Start Read(optional AP) 8 L H H H X X No Operation Continue the Burst

Rev 1.1 / July. 2009 20 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series CURRENT STATE TRUTH TABLE (Sheet 2 of 4) Current State Command Action Notes CS RAS CAS WE BA0/ BA1 Amax -A0 Description Read H X X X X X Device Deselect Continue the Burst Write L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge Termination Burst: Start the Precharge 10 L L H H BA Row Add. Bank Activate ILLEGAL 4 L H L L BA Col Add. A10 Write/WriteAP Termination Burst: Start Write(optional AP) 8 L H L H BA Col Add. A10 Read/ReadAP Termination Burst: Start Read(optional AP) 8,9 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst Read with Auto Precharge L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 12 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst Write with Auto Precharge L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 12 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst

Rev 1.1 / July. 2009 21 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series CURRENT STATE TRUTH TABLE (Sheet 3 of 4) Current State Command Action Notes CS RAS CAS WE BA0/ BA1 Amax -A0 Description Precharging L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge No Operation: Bank(s) idle after t RP L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,12 L H H H X X No Operation No Operation: Bank(s) idle after t RP H X X X X X Device Deselect No Operation: Bank(s) idle after t RP Row Activating L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Add. Bank Activate ILLEGAL 4,11,1 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,12 L H H H X X No Operation No Operation: Row Active after t RCD H X X X X X Device Deselect No Operation: Row Active after t RCD Write Recovering L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,13 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP Start Write: Optional AP(A10=H) L H L H BA Col Add. A10 Read/ReadAP Start Read: Optional AP(A10=H) 9 L H H H X X No Operation No Operation: Row Active after t DPL

Rev 1.1 / July. 2009 22 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series CURRENT STATE TRUTH TABLE (Sheet 4 of 4) Current State Command Action Notes CS RAS CAS WE BA0/ BA1 Amax -A0 Description Write Recovering H X X X X X Device Deselect No Operation: Row Active after t DPL Write Recovering with Auto Precharge L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,13 L L H H BA Row Add. Bank Activate ILLEGAL 4,12 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 4,12 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 4,9,12 L H H H X X No Operation No Operation: Precharge after t DPL H X X X X X Device Deselect No Operation: Precharge after t DPL Refreshing L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 13 L L H H BA Row Add. Bank Activate ILLEGAL 13 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 13 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 13 L H H H X X No Operation No Operation: idle after t RC H X X X X X Device Deselect No Operation: idle after t RC Mode Register Accessing L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 13 L L H H BA Row Add. Bank Activate ILLEGAL 13 L H L L BA Col Add. A10 Write/WriteAP ILLEGAL 13 L H L H BA Col Add. A10 Read/ReadAP ILLEGAL 13 L H H H X X No Operation No Operation: idle after 2 clock cycles H X X X X X Device Deselect No Operation: idle after 2 clock cycles

Rev 1.1 / July. 2009 23 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Note: 1. H: Logic High, L: Logic Low, X: Don 't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if t RCD is not satisfied. 7. Illegal if t RAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don 't satisfy t DPL . 11. Illegal if t RRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1.

Rev 1.1 / July. 2009 24 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series CKE Enable(CKE) Truth TABLE (Sheet 2 of 1) Current State CKE Command Action Notes Previous Cycle Current Cycle CS RAS CAS WE BA0, BA1 Amax - Self Refresh H X X X X X X X INVALID 1 L H H X X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X X Exit Self Refresh with No Operation 2 L H L H H L X X ILLEGAL 2 L H L H L X X X ILLEGAL 2 L H L L X X X X ILLEGAL 2 L L X X X X X X Maintain Self Refresh Power Down H X X X X X X X INVALID 1 L H H X X X X X Power Down mode exit, all banks idle 2 L H H H X X L H L L X X X X ILLEGAL 2X L X X X X X L X X L L X X X X X X Maintain Power Down Mode Deep Power Down H X X X X X X X INVALID 1 L H X X X X X X Deep Power Down mode exit 5 L L X X X X X X Maintain Deep Power Down Mode

Rev 1.1 / July. 2009 25 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series CKE Enable(CKE) Truth TABLE (Sheet 2 of 2) Note: 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200usec. Current State CKE Command Action Notes Previous Cycle Current Cycle CS RAS CAS WE BA0, BA1 Amax - All Banks Idle H H H X X X Refer to the idle State section of the Current State Truth Table H H L H X X 3 H H L L H X 3 H H L L L H X X Auto Refresh H H L L L L OP CODE Mode Register Set 4 H L H X X X Refer to the idle State section of the Current State Truth Table H L L H X X 3 H L L L H X 3 H L L L L H X X Entry Self Refresh 4 H L L L L L OP CODE Mode Register Set L X X X X X X X Power Down 4 Any State other than listed above H H X X X X X X Refer to operations of the Current State Truth Table H L X X X X X X Begin Clock Suspend next cycle L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend

Rev 1.1 / July. 2009 26 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Mobile SDR SDRAM OPERATION State Diagram ACT : Active DPDS : Enter Deep Power-Down DPDSX : Exit Deep Power- DownEMRS EMRS : Ext. Mode Reg. Set MRS : Mode Register Set PRE : Precharge PREALL : Precharge All Banks REFA : Auto Refresh REFS : Enter Self Refresh REFSX : Exit Self Refresh READ : Read w/o Auto Precharge READA : Read with Auto Precharge WRITE : Write w/o Auto Precharge WRITEA : Write with Auto Precharge IDLE DEEP POWER DOWN Power Down ROW ACTIVE ACT WRITE READ Active Power Down WRITE with AP READ with AP Write Read READ SUSPEND READA SUSPEND WRITE SUSPEND WRITEA SUSPEND Read Write WRIT EAREADA Precharge All Automatic Sequence Manual input CKE High CKE Low CKE Low CKE High CKE High CKE Low CKE Low CKE High CKE Low CKE High Self Refresh (EXTENDED) Mode Register Set Auto Refresh Precharge All Bank Power On REFA REFS REFX (E)MRS DP DS DPDSX PRE PR E PRE CKE Low CKE High

Rev 1.1 / July. 2009 27 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series DESELECT The DESELECT function (CS = High) prevents new commands from being executed by the Mobile SDRAM, the Mobile SDRAM ignore command input at the clock. However, the internal status is held. The Mobile SDRAM is effectively dese- lected. Operations already in progress are not affected. NO OPERATION The NO OPERATION (NOP) command is used to perform a NOP to a Mobile SDRAM that is selected (CS = Low, RAS = CAS = WE = High). This command is not an execution command. However, the internal operations continue. This pre- vents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. (see to next figure) ACTIVE The Active command is used to activate a row in particular bank for a subsequent Read or Write access. The value of the BA0,BA1 inputs selects the bank, and the address provided on A0-A12(or the highest address bit) selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. (see to next fig- ure) CS A0~A12 WE CAS RAS Don't Care CLK CKE High BA0,1 CS A0~A12 WE Bank Address CAS RAS Row Address Don't Care CLK CKE High RA BA BA0,1 NOP command ACTIVATING A SPECIFIC ROW IN A SPECIFIC BANK

Rev 1.1 / July. 2009 28 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series READ / WRITE COMMAND Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACT) command. An interval of tRCD is required between the bank active command input and the follow- ing read/write command input. The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and address inputs select the starting column location. The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued. The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank and address inputs select the starting column location. The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access. READ / WRITE COMMAND C S A 0 ~ A 8 W E C AS R AS D on't C are C LK C K E High CA BA BA0 ,1 H ig h to Enable Au to P recharge Low to D isable Au to P recharge R ead C om m and O peration W rite C om m and O peration A 10 C S A 0 ~ A 8 W E C AS R AS C LK C K E High CA BA B A0 ,1 A 10

Rev 1.1 / July. 2009 29 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series READ A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation. The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the suc- cessive burst-length data has been output. The /CAS latency and burst length must be specified at the mode register. Read Burst Showing CAS Latency CLK tCK Command DQ Undefined REA D NOP NOP Do0 Do1 Do2 Do3 tOH tLZ tAC CL = 2 REA D NOP NOP NOP Do0 Do1 Do2 Do3 tOH tLZ tAC CL = 3 Command DQ Don't Care

Rev 1.1 / July. 2009 30 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series READ to READ Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. When another read command is executed at the same ROW address of the same bank as the preceding read com- mand execution, the second read can be performed after an interval of no less than 1 clock. Even when the first com- mand is a burst read that is not yet finished, the data read by the second command will be valid. Consecutive Read Bursts A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are shown in Figure. Full-speed random read accesses within a page or pages can be performed as shown in Fig. CLK Do a0 READ CL =3 CL =2 Don't Care Command Address DQ DQ Do a1 Do b0 Do b1 Do a0 Do a1 Do b0 READ ’ BA, Col b BA, Col a NOP NOP

Rev 1.1 / July. 2009 31 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Non-Consecutive Read Bursts Random Read Bursts CLK Do n Do n READ READ BA, Col n CL =3 CL =2 Don't Care 1) Do n (or b): Data out from column n 2) BA, Col n (b) = Bank A, Column n (b) 3) Burst Length = 4 : 3 subseqnent elements of Data Out appear in the programmed order following Do n (b) Command Address DQ DQ BA, Col b Do b Do b Do g CLK CL =3 CL =2 Don't Care DQ DQ READ READ READ READ Command BA, Col nAddress BA, Col b BA, Col x BA, Col g Do n Do bDo n' Do x Do x' Do b' Do g Do g' Do x'Do n Do n' Do x Do b Do b' Do g’ 1) Do n, etc: Data out from column n, etc n', x', etc : Data Out elements, accoding to the programmd burst order 2) BA, Col n = Bank A, Column n 3) Burst Length = 1, 2, 4, 8 or full page in cases shown 4) Read are to active row in any banks

Rev 1.1 / July. 2009 32 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series READ BURST TERMINATE Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ com- mand where X equals the desired data-out element. Terminating a Read Burst CLK CL =3 CL =2 Don't Care DQ DQ READ BURST Command BA, Col n Address Do n Do n' Do n Do n' 1) Do n : Data out from column n 2) BA, Col n = Bank A, Column n 3) Cases shown are bursts of 4, 8, or full page terminated after 2 data elements

Rev 1.1 / July. 2009 33 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series READ to WRITE Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If trun- cation is necessary, the BURST TERMINATE command must be used, as shown in next fig. Read to Write Note: 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preced- ing read command, the write command can be performed after an interval of no less than 1 clock. However, DQM must be set High so that the output buffer becomes High-Z before data input. 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is nec- essary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before data input. CLK CL =3 CL =2 Don't Care DQ DQ READ BURST WRITE Command BA, Col n Address Do n Do n' Do n Do n' BA, Col b DIb0 DIb1 DIb2 DIb3 DIb0 DIb1 DIb2 DIb3 1) DO n = Data Out from column n; DI b = Data In to column b

Rev 1.1 / July. 2009 34 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series READ to PRECHARGE Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto pre- charge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to trun- cate fixed-length or full-page bursts. READ to PRECHARGE CLK CL =3 CL =2 Don't Care DQ DQ READ PRE ACT Command BA, Col nAddress Bank A, All BA, Row Do n tRP Do n 1) DO n = Data Out from column n 2) Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks. 3) The ACTIVE command may be applied if tRC has been met.

Rev 1.1 / July. 2009 35 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Write Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory; if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subse- quent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored. A full-page burst will continue until terminated. Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. Basic Write timing parameters for Write Burst Operation Note: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority. 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is nec- essary to separate the two write commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority. CLK Don't Care DQ WRITE Command BA, Col bAddress DIb0 DQ DIb0 DIb1 DQ DIb0 DIb1 DIb2 DIb3 DQ DIb0 DIb1 DIb2 DIb3 DIb4 DIb6 DIb7 CL = 2 or 3 BL = 1 BL = 2 BL = 4 BL = 8 DIb5

Rev 1.1 / July. 2009 36 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series WRITE to WRITE Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of the clock following the previous WRITE command. The first data-in element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of desired data-in element. Concatenated Write Bursts Random Write Cycles CLK Don't Care WRITE WRITE Command BA, Col b Address DQ DIb0 DIb1 DIb2 DIb3 DIn0 DIn2 DIn3 CL = 2 or 3 DIn1 BA, Col n DM CLK Don't Care WRITE WRITE WRITE WRITE WRITE NOP Command BA, Col bAddress DQ DIb DIb' DIx DIx’ DIn DIa CL = 2 or 3 DIn’ BA, Col n BA, Col x BA, Col a BA, Col g DIa’ DIg DIg’ DM

Rev 1.1 / July. 2009 37 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series WRITE to READ The preceding burst write operation can be aborted and a new burst read operation can be started by inputting a new read command in the write cycle. The data of the read command (READ) is output after the lapse of the /CAS latency. The preceding write operation (WRIT) writes only the data input before the read command. The data bus must go into a high-impedance state at least one cycle before output of the latest data. Note: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preced- ing write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed. 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is nec- essary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address). CLK Don't Care DQ WRITE READ Command BA, Col b Address DQ DIb0 DIb1 DO n0 DO n2 DO n3 BL = 4DO n1 DIb0 DIb1 BL = 4CL = 3 BA, Col n CL = 2 DO n0 DO n2 DO n3DO n1

Rev 1.1 / July. 2009 38 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series WRITE to PRECHARGE Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto Precharge was not activated). When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL. To follow a WRITE without truncating the WRITE burst, tDPL should be met as shown in Fig. Non-Interrupting Write to Precharge Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure. Note that only data-in that are registered prior to the t DPL period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent com- mand to the same bank cannot be issued until tRP is met. Interrupting Write to Precharge CLK WRITE PRE Command BA, Col b Address DQ DIb0 DIO b2 BL = 4DIb1 CL = 2 or 3 tDPL DIb3 CLK DQ WRITE PRE Command BA, Col bAddress DIb0 DIO b2 BL = 4DIb1 CL = 2 or 3 tDPL

Rev 1.1 / July. 2009 39 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series BURST TERMINATE The BURST TERMINATE command is used to truncate read bursts or write bursts (with auto precharge disabled). The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this datasheet. The BURST TERMINATE command is not bank specific. BURST TERMINATE COMMAND CS A0~A12 WE CAS RAS Don't Care CLK CKE High BA0, 1

Rev 1.1 / July. 2009 40 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. Another command to the same bank (or banks) being precharged must not be issued until the precharge time (t RP ) is completed. If one bank is to be precharged, the particular bank address needs to be specified. If all banks are to be precharged, A10 should be set high along with the PRECHARGE command. If A10 is high, BA0 and BA1 are ignored. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. PRECHARGE command AUTO PRECHARGE Auto Precharge is a feature which performs the same individual bank precharge function as described above, but with- out requiring an explicit command. This is accomplished by using A10 (A10=high), to enable auto precharge in conjunction with a specific Read or Write command. This precharges the bank/row after the Read or Write burst is complete. Auto precharge is non persistent, so it should be enabled with a Read or Write command each time auto precharge is desired. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (t RP ) is completed. Don't Care CS A0~A9 A11, A12 WE CAS RAS CKE High BA BA0,1 A10 Bank Address A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write command, auto- precharge function is enabled. While A10 = Low, auto- precharge function is disabled.

Rev 1.1 / July. 2009 41 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series AUTO REFRESH AND SELF REFRESH Mobile SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode: - AUTO REFRESH. This command is used during normal operation of the Mobile SDRAM. It is non persistent, so must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller.The Mobile SDRAM requires AUTO REFRESH commands at an average periodic interval of t REF . To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8*t REF . -SELF REFRESH. This state retains data in the Mobile SDRAM, even if the rest of the system is powered down. Note refresh interval tim- ing while in Self Refresh mode is scheduled internally in the Mobile SDRAM and may vary and may not meet tREF time. After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF (max.) period on the condition 1 and 2 below. 1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. 2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below* after exiting from self-refresh mode. Note: tREF (max.) / refresh cycles. The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra AUTO REFRESH command is recom- mended. In the self refresh mode, two additional power-saving options exist. They are Temperature Compensated Self Refresh and Partial Array Self Refresh and are described in the Extended Mode Register section. The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode regis- ters. The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Tempera- ture Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(I DD6 ) by using these two modes.

Rev 1.1 / July. 2009 42 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series AUTO REFRESH COMMAND SELF REFRESH ENTRY COMMAND Note 1: If all banks are in the idle status and CKE is inactive (low level), the self refresh mode is set. Function CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/AP BA Auto Refresh H H L L L H X X Self Refresh Entry H L L L L H X X CS A0~A12 WE CAS RAS Don't Care CLK CKE BA0, 1 CS A0~A12 WE CAS RAS Don't Care CLK CKE High BA0, 1

Rev 1.1 / July. 2009 43 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series MODE REGISTER SET The mode registers are loaded via the address bits. BA0 and BA1 are used to select between the Mode Register and the Extended Mode Register. See the Mode Register description in the register definition section. The MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until t MRD is met. MODE REGISTER SET COMMAND Note: BA0=BA1=Low loads the Mode Register, whereas BA0=Low and BA1=High loads the Extended Mode Register. Code = Mode Register / Extended Mode Register selection (BA0, BA1) and op-code (A0 - An) tMRD DEFINITION MRS NOP Valid Code Valid tMRD CLK Command Address Don't Care CS A0~A12 WE CAS RAS Don't Care CLK CKE BA0, 1 Code Code High

Rev 1.1 / July. 2009 44 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series POWER DOWN Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in progress. If power down occurs when all banks are idle, it is Precharge Power Down. If Power down occurs when one or more banks are Active, it is referred to as Active power down. The device cannot stay in this mode for longer than the refresh requirements of the device, without losing data. The power down state is exited by setting CKE high while issuing a Device Deselect or NOP command. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. DEEP POWER-DOWN The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the Mobile SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and the Extended Mode Register is lost. Next Figure, DEEP POWER-DOWN COMMAND shows the DEEP POWER-DOWN command All banks must be in idle state with no activity on the data bus prior to entering the DPD mode. While in this state, CKE must be held in a constant low state. To exit the DPD mode, CKE is taken high after the clock is stable and NOP command must be maintained for at least 200 us. After 200 us a complete re-initialization routing is required defined for the initialization sequence. CS A0~A12 WE CAS RAS Don't Care CLK CKE BA0, 1 POWER-DOWN COMMAND CS A0~A12 WE CAS RAS Don't Care CLK CKE BA0, 1 DEEP POWER-DOWN COMMAND

Rev 1.1 / July. 2009 45 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series CLK CKE COMMAND NOP NOP ACTIVE Input buffers gated off tRCD tRAS tRC Enter power-down mode. Exit power-down mode. All banks idle DON ’ T CARE CLK CKE COMMAND Pre-charge all Deep Power down entry DON ’ T CARE NOP APCG NOP NOP PCG Input buffers gated off 200us (min) tCKS tCKS Deep Power down Exit

Rev 1.1 / July. 2009 46 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Power-up and Initialization Like a Synchronous DRAM, Low Power SDRAM(Mobile SDRAM) must be powered up and initialized in a predefined man- ner. Power must be applied to V DD and V DDQ (simultaneously). The clock signal must be started at the same time. After power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile SDRAM. Then, 2 or more Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will be issued to program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR). The fol- lowing these cycles, the Mobile SDRAM is ready for normal operation. Programming the registers Mode Register The mode register contains the specific mode of operation of the Mobile SDRAM. This register includes the selection of a burst length(1, 2, 4, 8, Full Page), a cas latency(2 or 3), a burst type. The mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command. Extended Mode Register The extended mode register contains the specific features of self refresh operation of the Mobile SDRAM. This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.). The extended mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of extended mode register set command. Bank(Row) Active The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS , RAS and deasserting CAS , WE at the positive edge of the clock. The value on the BA1 and BA0 selects the bank, and the value on the A0-A12 selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write operations can only be initiated on this activated bank after the min- imum t RCD time is passed from the activate command. Read The READ command is used to initiate the burst read of data. This command is initiated by activating CS , CAS , and deasserting WE , RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Pre- charge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and the CAS latency will be determined by the values programmed during the MRS command. Write The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS , CAS , WE and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Pre- charge is not selected, the row will remain active for subsequent accesses.

Rev 1.1 / July. 2009 47 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Precharge The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open row in a particular bank will be precharged. The bank(s) will be available when the minimum t RP time is met after the precharge command is issued. Auto Precharge The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated. Burst Termination The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the bank open. Data Mask The Data Mask command is used to mask READ or WRITE data. During a READ operation, When this command is is- sued, data outputs are disabled and become high impedance after two clock delay. During a WRITE operation, When this command is issued, data inputs can't be written with no clock delay. If data mask is initiated by asserting low on DQM during the read cycle, the data outputs are enabled. If DQM is asserted to High. the data outputs are masked (disabled) and become Hi-Z state after 2 cycle later. During the write cycle, DQM mask data input with zero latency DM CMD CK D0 D1DQ Data Masking

0 Latency Hi-Z

DIN0 D0 D1 D0 D1DIN2 D0 D1 WRIT MK MK Data Masking

0 Latency

2 Latency

DOUT0 D0 D1DOUT1 D0 D1DDOT2 D0 D1 READ M K Read Data Masking

Rev 1.1 / July. 2009 48 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Clock Suspend The Clock Suspend command is used to suspend the internal clock of Mobile SDRAM. The clock suspend operation stops transmission of the clock to the internal circuits of the device during burst transfer of data to stop the operation of the device. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends data Read and Write operations. (See examples in next Figures) CLK CKE Q1 Q2 Q3 Q4 RD Internal CLK Clock Suspend Mode WR D1 D2 D3 D4 Clock Suspend Mode DQ Command CKE Command Internal CLK DQ Frozen Int. CLK by CKE (CKE = Fixed Low) Masked by CKE Masked by CKE Frozen Int. CLK by CKE (CKE = Fixed Low)

Rev 1.1 / July. 2009 49 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Power Down The Power Down command is used to reduce stand-by current. Before this command is issued, all banks must be pre- charged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping CKE low, all of the input buffer except CKE are gated off. Auto Refresh The Auto Refresh command is used during normal operation and is similar to C BR refresh in Conventional DRAMs. This command must be issued each time a refresh is required. When an Auto Refresh command is issued, the address bits is ''Don't care'', because the specific address bits is generated by internal refresh address counter. Self Refresh The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode registers. The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(I DD6 ) by using these two modes. Deep Power Down The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory array of the devices. For more information, see the special operation for Low Power consumption of this data sheet.

Rev 1.1 / July. 2009 50 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Special Operation for Low Power Consumption Deep Power Down Mode Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. Full initialization is required when the device exits from Deep Power Down Mode. Truth Table Deep Power Down Mode Entry The Deep Power Down Mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of the clock, while CKE is low. The following diagram illustrates deep power down mode entry. Current State Command CKE n-1 CKE n CS RAS CAS WE Idle Deep Power Down Entry H L L H H L Deep Power Down Deep Power Down Exit L H X X X X CKE CS RAS CAS WE Pre-charge if needed tRP Deep Power Down Entry

Rev 1.1 / July. 2009 51 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Deep Power Down Mode (Continued) Deep Power Down Mode Exit Sequence The Deep Power Down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command. 1. Maintain NOP input conditions for a minimum of 200usec 2. Issue precharge commands for all banks of the device 3. Issue 2 or more auto refresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register The following timing diagram illustrates deep power down mode exit sequence. CKE CLK CS RAS CAS WE 200us tRP tRC Deep Power Down Exit All Banks Precharge Auto Refresh Auto Refresh Mode Register Set Extended Mode Register Set New Command Accepted Here

Rev 1.1 / July. 2009 52 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series

PACKAGE INFORMATION

54 Ball FBGA 0.8mm pitch (8.0mm x 8.0mm, t=1.0mm max) Unit [mm]0.80 Bottom View 0.34 +/- 0.05 0.80 Typ. 0.80 Typ. 1.00 max 3.20 1.60 0.45 +/- 0.05 A1 INDEX MARK 1.375 8.00 Typ. 0.80 8.00 Typ.