GMS90C3X HYNIX | Alldatasheet
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HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS GMS90C3X GMS90C5X GMS97C5X User’s Manual (Ver. 3.1a)
Version 3.1a Published by ÓÓÓÓ 2001 Hynix semiconductor All right reserved. Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Representatives listed at address directory. Hynix semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconduc- tor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
Oct. 2000 Ver 3.1a Device Naming Structure GMS90X5X Frequency Package Type Blank: 24: 40: 12MHz 24MHz 40MHz Blank: PL: 40PDIP 44PLCC 44MQFP ROM Code serial No. ROM size 4k bytes 8k bytes 16k bytes 24k bytes 32k bytes Operating Voltage 4.25~5.5V 2.7~3.6V Hynix semiconductor MCU -G B X X XX XX X GMS97X5X Frequency Package Type Blank: 12/24(5V),12MHz(3V) 33MHz Blank: PL: 40PDIP 44PLCC 44MQFP ROM size 4k bytes 8k bytes 16k bytes 24k bytes 32k bytes Operating Voltage 4.25~5.5V 2.7~3.6V Hynix semiconductor MCU XXX Mask ROM versionOTP version 16: 16MHz
Oct. 2000 Ver 3.1a G M S 9 0S e r i e sS e l e c t i o nG u i d e Operating Voltage(V) ROM size (bytes) RAM size (bytes) Device Name Operating Frequency (MHz)MASK OTP 4.25~5.5 ROM-less 128 256 GMS90C31 GMS90C32 12/24/40 12/24/40 16K 24K 32K 128 256 256 256 256 GMS90C51 GMS90C52 GMS90C54 GMS90C56 GMS90C58 12/24/40 12/24/40 12/24/40 12/24/40 12/24/40 16K 16K 24K 24K 32K 32K 128 128 256 256 256 256 256 256 256 256 GMS97C51 GMS97C51H GMS97C52 GMS97C52H GMS97C54 GMS97C54H GMS97C56 GMS97C56H GMS97C58 GMS97C58H 2.7~3.6 ROM-less 128 256 GMS90L31 GMS90L32 16K 24K 32K 128 256 256 256 256 GMS90L51 GMS90L52 GMS90L54 GMS90L56 GMS90L58 16K 24K 32K 128 256 256 256 256 GMS97L51 GMS97L52 GMS97L54 GMS97L56 GMS97L58
Oct. 2000 Ver 3.1a 1 GMS90C31/51, 97C51 GMS90L31/51, 97L51 (Low voltage versions)
- Fully compatible to standard MCS-51 microcontroller
- Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
- 4 K· 8 (EP)ROM
- 1 2 8· 8R A M
- 64K external program memory space
- 64K external data memory space
- Four 8-bit ports
- Two 16-bit Timers / Counters
- USART
- Five interrupt sources, two priority levels
- Power saving Idle and power down mode
- Quick pulse programming algorithm (in the OTP devices)
- 2-level program memory lock (in the OTP devices)
- 2.7Volt low voltage version available
- P-DIP-40, P-LCC-44, P-MQFP-44 package Block Diagram RAM 128 · 8 PORT 0 PORT 1 PORT 3 PORT 2 8-BIT USART ROM / EPROM 4K · 8 CPU I/O I/O I/O I/O
2 Oct. 2000 Ver 3.1a GMS90C32/52, 97C52 GMS90L32/52, 97L52 (Low voltage versions)
- Fully compatible to standard MCS-51 microcontroller
- Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
- 8 K· 8 (EP)ROM
- 2 5 6· 8R A M
- 64K external program memory space
- 64K external data memory space
- Four 8-bit ports
- Three 16-bit Timers / Counters (Timer2 with up/down counter feature)
- USART
- Six interrupt sources, two priority levels
- Power saving Idle and power down mode
- Quick pulse programming algorithm (in the OTP devices)
- 2-level program memory lock (in the OTP devices)
- 2.7Volt low voltage version available
- P-DIP-40, P-LCC-44, P-MQFP-44 package Block Diagram RAM 256 · 8 PORT 0 PORT 1 PORT 3 PORT 2 8-BIT USART ROM / EPROM 8K · 8 CPU I/O I/O I/O I/O
Oct. 2000 Ver 3.1a 3 GMS90C54/56/58, 97C54/56/58 GMS90L54/56/58, 97L54/56/58 (Low voltage versions)
- Fully compatible to standard MCS-51 microcontroller
- Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
- 16K/24K/32K bytes (EP)ROM
- 2 5 6· 8R A M
- 64K external program memory space
- 64K external data memory space
- Four 8-bit ports
- Three 16-bit Timers / Counters (Timer2 with up/down counter feature)
- USART
- One clock output port
- Programmable ALE pin enable / disable
- Six interrupt sources, two priority levels
- Power saving Idle and power down mode
- Quick pulse programming algorithm (in the OTP devices)
- 2-level program memory lock (in the OTP devices)
- 2.7Volt low voltage version available
- P-DIP-40, P-LCC-44, P-MQFP-44 package Block Diagram RAM 256 · 8 PORT 0 PORT 1 PORT 3 PORT 2 8-BIT USART ROM / EPROM GMS9XX54: 16K · 8 CPU I/O I/O I/O I/O GMS9XX56: 24K · 8 GMS9XX58: 32K · 8
4 Oct. 2000 Ver 3.1a PIN CONFIGURATION 44-PLCC Pin Configuration (top view) P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA /VPP N.C.* ALE / PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 P1.5 P1.6 P1.7 RESET RxD / P3.0 N.C.* TxD / P3.1 INT0 /P 3 . 2 INT1 /P 3 . 3 T0 / P3.4 T1 / P3.5 WR /P 3 . 6 RD /P 3 . 7 XTAL2 XTAL1 VSS N.C.* P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 P1.4 P1.3 P1.2 P1.1 / T2EX P1.0 / T2 N.C.* V CC P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 INDEX CORNER N.C.: Do not connect.
Oct. 2000 Ver 3.1a 5 40-PDIP Pin Configuration (top view) P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA /VPP ALE / PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 V CC T2EX / P1.1 P1.2 P1.3 P1.4 T2 / P1.0 P1.5 P1.6 P1.7 RESET RxD / P3.0 TxD / P3.1 INT0 /P 3 . 2 INT1 /P 3 . 3 T0 / P3.4 T1 / P3.5 WR /P 3 . 6 RD /P 3 . 7 XTAL2 XTAL1 V SS
6 Oct. 2000 Ver 3.1a 44-MQFP Pin Configuration (top view) P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA /VPP N.C.* ALE / PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 P1.5 P1.6 P1.7 RESET RxD / P3.0 N.C.* TxD / P3.1 INT0 /P 3 . 2 INT1 /P 3 . 3 T0 / P3.4 T1 / P3.5 WR /P 3 . 6 RD /P 3 . 7 XTAL2 XTAL1 VSS N.C.* P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 P1.4 P1.3 P1.2 P1.1 / T2EX P1.0 / T2 N.C.* V CC P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 N.C.: Do not connect.
Oct. 2000 Ver 3.1a 7 Logic Symbol XTAL1 XTAL2 RESET Port 0 8-bit Digital I/O Port 1 8-bit Digital I/O Port 2 8-bit Digital I/O Port 3 8-bit Digital I/O EA /VPP ALE/PROG PSEN VCC VSS
8 Oct. 2000 Ver 3.1a PIN DEFINITIONS AND FUNCTIONS Symbol Pin Number Input/ Output FunctionPLCC- PDIP- MQFP- P1.0-P1.7 2-9 1-8 40-44, 1-3 I/O Port1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the pulls-ups (I IL, in the DC characteristics). Pins P1.0 and P1.1 also. Port1 also receives the low-order address byte during program memory verification. Port1 also serves alternate functions of Timer 2. P1.0 / T2 : Timer/counter 2 external count input P1.1 / T2EX : Timer/counter 2 trigger input In GMS9XC54/56/58: P1.0 / T2, Clock Out : Timer/counter 2 external count input, Clock Out P3.0-P3.7 11, 13-19 10-17 5, 7-13 I/O Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 3 pins that are externally pulled low will source current because of the pulls-ups (I IL, in the DC characteristics). Port 3 also serves the special features of the 80C51 family, as listed below. P3.0 / RxD P3.1 / TxD P3.2 /INT0 P3.3 / INT1 P3.4 /T0 P3.5 /T1 P3.6 / WR P3.7 /RD receiver data input (asynchronous) or data input output(synchronous) of serial interface 0 transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 interrupt 0 input/timer 0 gate control interrupt 1 input/timer 1 gate control counter 0 input counter 1 input the write control signal latches the data byte from port 0 into the external data memory the read control signal enables the external data memory to port 0 XTAL2 20 18 14 O XTAL2 Output of the inverting oscillator amplifier.
Oct. 2000 Ver 3.1a 9 XTAL1 21 19 15 I XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits.To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed. P2.0-P2.7 24-31 21-28 18-25 I/O Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 2 pins that are externally pulled low will source current because of the pulls-ups (I IL, in the DC characteristics).Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 special function register. PSEN 32 29 26 O The Program Store Enable The read strobe to external program memory when the device is executing code from the external program memory. PSEN is activated twice each machine cycle, except that two PSENactivations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. RESET 10 9 4 I RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC . Symbol Pin Number Input/ Output FunctionPLCC- PDIP- MQFP-
10 Oct. 2000 Ver 3.1a ALE / PROG 33 30 27 O The Address Latch Enable / Program pulse Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG )d u r i n g EPROM programming. In GMS9XC54/56/58: If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH . With this bit set, the pin is weakly pulled high. The ALE disable feature will be terminated by reset. Setting the ALE-disable bit has no affect if the microcontroller is in external execution mode. EA /VPP 35 31 29 I External Access Enable / Program Supply Voltage EA must be external held low to enable the device to fetch code from external program memory locations 0000H to FFFFH .I fE A is held high, the device executes from internal program memory unless the program counter contains an address greater than its internal memory size. This pin also receives the 12.75V programming supply voltage (VPP )d u r i n g EPROM programming. Note; however, that if any of the Lock bits are programmed, EA will be internally latched on reset. P0.0-P0.7 36-43 32-39 30-37 I/O Port 0 Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the GMS97X5X. External pull-up resistors are required during program verification. V SS 22 20 16 - Circuit ground potential VCC 44 40 38 - Supply terminalfor all operating modes N.C. 1,12 23,34 -6 , 1 7 28,39 - No connection Symbol Pin Number Input/ Output FunctionPLCC- PDIP- MQFP-
12 Oct. 2000 Ver 3.1a CPU The GMS90 series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0ms (40MHz: 300ns). Special Function Register PSW Reset value of PSW is 00H . Bit Function CY Carry Flag AC Auxiliary Carry Flag(for BCD operations) F0 General Purpose Flag RS1 RS0 Register Bank select control bits Bank 0 selected, data address 00 H -0 7H Bank 1 selected, data address 08H -0 FH Bank 2 selected, data address 10H -1 7H Bank 3 selected, data address 18H -1 FH OV Overflow Flag F1 General Purpose Flag P Parity Flag Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. CY AC F0 RS1 RS0 OV F1 P 76543210 LSBMSB Bit No. Addr. D0H PSW
and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in Table 1, Table 1, and Table 3. refer to the functional blocks of the GMS90 series. Table 3 illustrates the contents of the SFRs. Table 1. Special Function Registers in Numeric Order of their Addresses 1) Bit-addressable Special Function Register. 2) X means that the value is indeterminate and the location is reserved. 3) The GMS9XX54/56/58 have the AUXR0 register at address 8EH .
Table 1. Special Function Registers in Numeric Order of their Addresses(cont’d)
1) Bit-addressable Special Function Register. 2) X means that the value is indeterminate and the location is reserved. 3) Address C9H is configured as below.
Table 2. Special Function Registers - Functional Blocks Serial Channel 0 Control Reg. 4) The AUXR0 is in the GMS9XX54/56/58 only.
† indicates resident in the GMS9XX54/56/58, not in 9XX51/52. Table 3. Contents of SFRs, SFRs in Numeric Order
† indicates resident in the GMS9XX54/56/58, not in 9XX51/52. Table 3. Contents of SFRs, SFRs in Numeric Order(cont’d)
pulse width measurements. Figure 2 illustrates the input clock logic. Figure 2. Timer/Counter 0 and 1 Input Clock Logic Table 4. Timer/Counter 0 and 1 Operating Modes
counter which is selected by bit C/T2(T2CON.1). It has three operating modes as shown in Table 5. Table 5. Timer/Counter 2 Operating Modes
as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 7. Table 6. USART Operating Modes Serial data enters and exits through RxD. Table 7. Formulas for Calculating Baud rates
Figure 3. Interrupt Request Sources
terrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. sequence as shown in Table 9. Table 8. Interrupt Sources and their Corresponding Interrupt Vectors Table 9. Interrupt Priority-Within-Level
Two power down modes are available, the Idle Mode and Power Down Mode. the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview of the power saving modes. Table 10. Power Saving Modes Overview redefinition of SFR contents).
Oct. 2000 Ver 3.1a 25
ELECTRICAL CHARACTERISTICS
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the de- vice. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat- ing conditions for longer periods may affect device reliability. During overload conditions (VIN >V CC or VIN <V SS ) the Voltage on VCC pins with respect to ground (VSS ) must not exceed the values defined by the absolute maxi- mum ratings.
26 Oct. 2000 Ver 3.1a DC Characteristics DC Characteristics for GMS90C31/32, GMS90C51/52/54/56/58 V CC =5 V+1 0 % ,- 1 5 % ;VSS=0V; T A =0 °Ct o7 0°C Parameter Symbol Limit Values Unit Test Conditions Min. Max. Input low voltage (except EA, RESET) VIL -0.5 0.2VCC -0 . 1 V- Input low voltage (EA)V IL1 -0.5 0.2VCC -0 . 3 V- Input low voltage (RESET) V IL2 -0.5 0.2VCC +0 . 1 V- Input high voltage (except XTAL1, EA, RESET) VIH 0.2VCC +0 . 9 V CC +0 . 5 V- Input high voltage to XTAL1 VIH1 0.7VCC VCC +0 . 5 V- Input high voltage to EA, RESET VIH2 0.6VCC VCC +0 . 5 V- Output low voltage (ports 1, 2, 3) VOL -0 . 4 5 V IOL =1 . 6 m A1) Output low voltage ( p o r t0 ,A L E ,P S E N) VOL1 -0 . 4 5 V IOL =3 . 2 m A1) Output high voltage (ports 1, 2, 3) VOH 2.4 0.9VCC -V IOH =- 8 0mA IOH =- 1 0mA Output high voltage (port 0 in external bus mode, ALE, PSEN VOH1 2.4 0.9VCC -V IOH =- 8 0 0mA 2) IOH =- 8 0mA 2) Logic 0 input current (ports 1, 2, 3) IIL -10 -50 mA VIN=0 . 4 5 V Logical 1-to-0 transition cur- rent (ports 1, 2, 3) ITL -65 -650 mA VIN=2 . 0 V Input leakage current (port 0, EA) ILI - –1 mA 0.45< VIN < VCC Pin capacitance C IO -1 0 p F fC =1 M H z TA=2 5°C Power supply current: Active mode, 12MHz3) Idle mode, 12MHz3) Active mode, 24 MHz3) Idle mode, 24MHz3) Active mode, 40 MHz3) Idle mode, 40 MHz3) Power Down Mode 3) ICC ICC ICC ICC ICC ICC IPD 4.8 36.2 8.2 58.5 12.5 mA mA mA mA mA mA mA V CC =5 V4) VCC =5 V5) VCC =5 V4) VCC =5 V5) VCC =5 V4) VCC =5 V5) VCC =5 V6)
Oct. 2000 Ver 3.1a 27 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 tran- sitions during bus operation. In the worst case (capacitive loading:> 50pF at 3.3V,> 100pF at 5V), the noise pulse on ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the V OH on ALE and PSEN to momentarily fall below the 0.9VCC specifica- tion when the address lines are stabilizing. 3) ICC Max at other frequencies is given by: active mode: ICC =1 . 2 7· fOSC +5 . 7 3 idle mode: ICC =0 . 2 8· fOSC + 1.45 (except OTP devices) where fOSC is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC =5 V . 4) ICC (active mode) is measured with: XTAL1 driven with tCLCH ,tCHCL =5 n s ,VIL=V SS +0 . 5 V ,VIH =V CC - 0.5V; XTAL2 = N.C.; EA = Port0 = RESET = VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (appr. 1mA). 5) ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH ,tCHCL =5 n s ,VIL=V SS +0 . 5 V ,VIH =V CC - 0.5V; XTAL2 = N.C.; R E S E T=E A=V SS ;P o r t 0=VCC ; all other pins are disconnected; 6) IPD (Power Down Mode) is measured under following conditions: EA =P o r t 0=VCC ; RESET = VSS ; XTAL2 = N.C.; XTAL1 = VSS ; all other pins are disconnected.
28 Oct. 2000 Ver 3.1a DC Characteristics for GMS97C51/52/54/56/58 (H) V CC =5 V+1 0 % ,- 1 5 % ;VSS=0V; T A =0 °Ct o7 0°C Parameter Symbol Limit Values Unit Test Conditions Min. Max. Input low voltage (except EA, RESET) VIL -0.5 0.2VCC -0 . 1 V- Input low voltage (EA)V IL1 -0.5 0.2VCC -0 . 3 V- Input low voltage (RESET) V IL2 -0.5 0.2VCC +0 . 1 V- Input high voltage (except XTAL1, EA, RESET) VIH 0.2VCC +0 . 9 V CC +0 . 5 V- Input high voltage to XTAL1 VIH1 0.7VCC VCC +0 . 5 V- Input high voltage to EA, RESET VIH2 0.6VCC VCC +0 . 5 V- Output low voltage (ports 1, 2, 3) VOL -0 . 4 5 V IOL =1 . 6 m A1) Output low voltage ( p o r t0 ,A L E ,P S E N) VOL1 -0 . 4 5 V IOL =3 . 2 m A1) Output high voltage (ports 1, 2, 3) VOH 2.4 0.9VCC -V IOH =- 8 0mA IOH =- 1 0mA Output high voltage (port 0 in external bus mode, ALE, PSEN VOH1 2.4 0.9VCC -V IOH =- 8 0 0mA 2) IOH =- 8 0mA 2) Logic 0 input current (ports 1, 2, 3) IIL -10 -50 mA VIN=0 . 4 5 V Logical 1-to-0 transition cur- rent (ports 1, 2, 3) ITL -65 -650 mA VIN=2 . 0 V Input leakage current (port 0, EA) ILI - –1 mA 0.45< VIN < VCC Pin capacitance C IO -1 0 p F fC =1 M H z TA=2 5°C Power supply current: Active mode, 12MHz3) Idle mode, 12MHz3) Active mode, 24 MHz3) Idle mode, 24MHz3) Active mode, 33 MHz3) Idle mode, 33 MHz3) Power Down Mode 3) ICC ICC ICC ICC ICC ICC IPD 4.8 36.2 8.2 mA mA mA mA mA mA mA V CC =5 V4) VCC =5 V5) VCC =5 V4) VCC =5 V5) VCC =5 V4) VCC =5 V5) VCC =5 V6)
Oct. 2000 Ver 3.1a 29 DC Characteristics for GMS90L31/32, GMS90L51/52/54/56/58 V CC = 3.3V + 0.3V, -0.6V; VSS=0V; T A =0 °Ct o7 0°C Parameter Symbol Limit Values Unit Test Conditions Min. Max. Input low voltage V IL -0.5 0.8 V - Input high voltage V IH 2.0 VCC +0 . 5 V- Output low voltage (ports 1, 2, 3) VOL - 0.45 0.30 V IOL =1 . 6 m A1) IOL =1 0 0mA 1) Output low voltage ( p o r t0 ,A L E ,P S E N) VOL1 - 0.45 0.30 V IOL =3 . 2 m A1) IOL =2 0 0mA 1) Output high voltage (ports 1, 2, 3) VOH 2.0 0.9VCC -V IOH =- 2 0mA IOH =- 1 0mA Output high voltage (port 0 in external bus mode, ALE, PSEN) VOH1 2.0 0.9VCC -V IOH =- 8 0 0mA 2) IOH =- 8 0mA 2) Logic 0 input current (ports 1, 2, 3) IIL -1 -50 mA VIN=0 . 4 5 V Logical 1-to-0 transition cur- rent (ports 1, 2, 3) ITL -25 -250 mA VIN=2 . 0 V Input leakage current (port 0, EA) ILI - –1 mA 0.45< VIN < VCC Pin capacitance C IO -1 0 p F fC =1 M H z TA=2 5°C Power supply current: Active mode, 16 MHz3) Idle mode, 16MHz3) Power Down Mode 3) ICC ICC IPD mA mA mA VCC =3 . 6 V4) VCC =2 . 6 V5) VCC =2~ 5.5V6)
30 Oct. 2000 Ver 3.1a DC Characteristics for GMS97L51/52/54/56/58 V CC = 3.3V + 0.3V, -0.6V; VSS=0V; T A =0 °Ct o7 0°C Parameter Symbol Limit Values Unit Test Conditions Min. max. Input low voltage V IL -0.5 0.8 V - Input high voltage V IH 2.0 VCC +0 . 5 V- Output low voltage (ports 1, 2, 3) VOL - 0.45 0.30 V IOL =1 . 6 m A1) IOL =1 0 0mA 1) Output low voltage ( p o r t0 ,A L E ,P S E N) VOL1 - 0.45 0.30 V IOL =3 . 2 m A1) IOL =2 0 0mA 1) Output high voltage (ports 1, 2, 3) VOH 2.0 0.9VCC -V IOH =- 2 0mA IOH =- 1 0mA Output high voltage (port 0 in external bus mode, ALE, PSEN) VOH1 2.0 0.9VCC -V IOH =- 8 0 0mA 2) IOH =- 8 0mA 2) Logic 0 input current (ports 1, 2, 3) IIL -1 -50 mA VIN=0 . 4 5 V Logical 1-to-0 transition cur- rent (ports 1, 2, 3) ITL -25 -250 mA VIN=2 . 0 V Input leakage current (port 0, EA) ILI - –1 mA 0.45< VIN < VCC Pin capacitance C IO -1 0 p F fC =1 M H z TA=2 5°C Power supply current: Active mode, 12MHz3) Idle mode, 12MHz3) Power Down Mode 3) ICC ICC IPD mA mA mA VCC =3 . 6 V4) VCC =2 . 6 V5) VCC =2~ 5.5V6)
Oct. 2000 Ver 3.1a 31 AC Characteristics Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a ‘t’ (stand for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. AC Characteristics for GMS90 series (12MHz version) External Program Memory Characteristics VCC =5 V: VCC =5 V+ 10%, - 15%; VSS =0 V ; TA=0 °Ct o7 0°C (CL for port 0. ALE and PSENoutputs = 100pF; CL for all other outputs = 80pF) VCC =3 . 3 V: VCC =3 . 3 V+ 0.3V,- 0.6V; VSS =0 V ; TA=0 °Ct o7 0°C (CL f o rp o r t0 .A L Ea n dP S E Noutputs = 50pF; CL for all other outputs = 50pF) Variable clock :Vcc = 5V : 1/tCLCL =3 . 5M H zt o1 2M H z Vcc = 3.3V : 1/tCLCL =1M H zt o1 2M H z Parameter Symbol
12 MHz Oscillator Variable Oscillator
1/tCLCL =3 . 5t o1 2 M H zUnit Min. Max. Min. Max. ALE pulse width tLHLL 127 - 2t CLCL -40 - ns Address setup to ALE tAVLL 43 - t CLCL -40 - ns Address hold after ALE tLLAX 30 - t CLCL -53 - ns ALE low to valid instruction intLLIV -2 3 3 - 4 t CLCL -100 ns ALE to PSEN tLLPL 58 - t CLCL -25 - ns PSEN pulse width tPLPH 215 - 3t CLCL -35 - ns PSEN to valid instruction intPLIV -1 5 0 - 3 t CLCL -100 ns Input instruction hold after PSENtPXIX 0- 0 - n s Input instruction float after PSENtPXIZ † -6 3 -t CLCL -20 ns Address valid after PSEN tPXAV † 75 - t CLCL -8 - ns A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example, t AVLL = Time from Address Valid to ALE Low tLLPL = Time from ALE Low to PSENLow
32 Oct. 2000 Ver 3.1a † Interfacing the GMS90 series to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Address to valid instruction intAVIV -3 0 2 - 5 t CLCL -115 ns Address float to PSEN tAZPL 0- 0 - n s Parameter Symbol 1/tCLCL =3 . 5t o1 2 M H zUnit Min. Max. Min. Max.
Oct. 2000 Ver 3.1a 33 AC Characteristics for GMS90 series (12MHz) External Data Memory Characteristics Advance Information (12MHz) External Clock Drive Parameter Symbol 1/tCLCL =3 . 5t o1 2 M H zUnit Min. Max. Min. Max. RD pulse width tRLRH 400 - 6t CLCL -100 - ns WR pulse width tWLWH 400 - 6t CLCL -100 - ns Address hold after ALE tLLAX2 53 - t CLCL -30 - ns RD to valid data in tRLDV -2 5 2 - 5 t CLCL -165 ns Data hold after RD tRHDX 0- 0 - ns Data float after RD tRHDZ -9 7 - 2 t CLCL -70 ns ALE to valid data in tLLDV -5 1 7 - 8 t CLCL -150 ns Address to valid data in tAVDV -5 8 5 - 9 t CLCL -165 ns ALE to WR or RD tLLWL 200 300 3t CLCL -50 3t CLCL +50 ns Address valid to WRor RD tAVWL 203 - 4t CLCL -130 - ns WR or RDhigh to ALE high tWHLH 43 123 t CLCL -40 t CLCL +40 ns Data valid to WRtransition tQVWX 33 - t CLCL -50 - ns Data setup before WR tQVWH 433 - 7t CLCL -150 - ns Data hold after WR tWHQX 33 - t CLCL -50 - ns Address float after RD tRLAZ -0 - 0 n s Parameter Symbol Variable Oscillator (Freq. = 3.5 to 12MHz) Unit Min. Max. Oscillator period (VCC =5V) Oscillator period (VCC =3.3V) tCLCL tCLCL 83.3 83.3 285.7 1 ns High time tCHCX 20 t CLCL -tCLCX ns Low time tCLCX 20 t CLCL -tCHCX ns Rise time tCLCH -2 0 n s Fall time tCHCL -2 0 ns
34 Oct. 2000 Ver 3.1a AC Characteristics for GMS90 series (16MHz version) V CC =3 . 3 V+0 . 3 V ,-0.6V; VSS=0 V ; TA =0 °Ct o7 0°C (CL for port 0. ALE and PSENoutputs = 50pF; CL for all other outputs = 50pF) External Program Memory Characteristics † Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Parameter Symbol
16 MHz Oscillator Variable Oscillator
1/tCLCL =3 . 5t o1 6 M H zUnit Min. Max. Min. Max. ALE pulse width tLHLL 85 - 2t CLCL -40 - ns Address setup to ALE tAVLL 23 - t CLCL -40 - ns Address hold after ALE tLLAX 23 - t CLCL -40 - ns ALE low to valid instruction intLLIV -1 5 0 - 4 t CLCL -100 ns ALE to PSEN tLLPL 38 - t CLCL -25 - ns PSEN pulse width tPLPH 153 - 3t CLCL -35 - ns PSEN to valid instruction intPLIV -8 8 - 3 t CLCL -100 ns Input instruction hold after PSENtPXIX 0- 0 - n s Input instruction float after PSENtPXIZ † -4 3 -t CLCL -20 ns Address valid after PSEN tPXAV † 55 - t CLCL -8 - ns Address to valid instruction intAVIV -1 9 8 - 5 t CLCL -115 ns Address float to PSEN tAZPL 0- 0 - n s
Oct. 2000 Ver 3.1a 35 AC Characteristics for GMS90 series (16MHz) External Data Memory Characteristics Advance Information (16MHz) External Clock Drive Parameter Symbol 1/tCLCL =3 . 5t o1 6 M H zUnit Min. Max. Min. Max. RD pulse width tRLRH 275 - 6t CLCL -100 - ns WR pulse width tWLWH 275 - 6t CLCL -100 - ns Address hold after ALE tLLAX2 23 - t CLCL -40 - ns RD to valid data in tRLDV -1 8 3 - 5 t CLCL -130 ns Data hold after RD tRHDX 0- 0 - ns Data float after RD tRHDZ -7 5 - 2 t CLCL -50 ns ALE to valid data in tLLDV -3 5 0 - 8 t CLCL -150 ns Address to valid data in tAVDV -3 9 8 - 9 t CLCL -165 ns ALE to WR or RD tLLWL 138 238 3t CLCL -50 3t CLCL +50 ns Address valid to WRor RD tAVWL 120 - 4t CLCL -130 - ns WR or RDhigh to ALE high tWHLH 28 97 t CLCL -35 t CLCL +35 ns Data valid to WRtransition tQVWX 13 - t CLCL -50 - ns Data setup before WR tQVWH 288 - 7t CLCL -150 - ns Data hold after WR tWHQX 23 - t CLCL -40 - ns Address float after RD tRLAZ -0 - 0 n s Parameter Symbol Variable Oscillator (Freq. = 3.5 to 16MHz) Unit Min. Max. Oscillator period tCLCL 62.5 285.7 ns High time tCHCX 17 t CLCL -tCLCX ns Low time tCLCX 17 t CLCL -tCHCX ns Rise time tCLCH -1 7 n s Fall time tCHCL -1 7 ns
36 Oct. 2000 Ver 3.1a AC Characteristics for GMS90 series (24MHz version) V CC =5 V+1 0 % ,-15%; VSS =0 V ; TA =0 °Ct o7 0°C (CL for port 0. ALE and PSENoutputs = 100pF; CL for all other outputs = 80pF) External Program Memory Characteristics † Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Parameter Symbol
24 MHz Oscillator Variable Oscillator
1/tCLCL =3 . 5t o2 4 M H zUnit Min. Max. Min. Max. ALE pulse width tLHLL 43 - 2t CLCL -40 - ns Address setup to ALE tAVLL 17 - t CLCL -25 - ns Address hold after ALE tLLAX 17 - t CLCL -25 - ns ALE low to valid instruction intLLIV -8 0 - 4 t CLCL -87 ns ALE to PSEN tLLPL 22 - t CLCL -20 - ns PSEN pulse width tPLPH 95 - 3t CLCL -30 - ns PSEN to valid instruction intPLIV -6 0 - 3 t CLCL -65 ns Input instruction hold after PSENtPXIX 0- 0 - n s Input instruction float after PSENtPXIZ † -3 2 -t CLCL -10 ns Address valid after PSEN tPXAV † 37 - t CLCL -5 - ns Address to valid instruction intAVIV -1 4 8 -5 t CLCL -60 ns Address float to PSEN tAZPL 0- 0 - n s
Oct. 2000 Ver 3.1a 37 AC Characteristics for GMS90 series (24MHz) External Data Memory Characteristics Advance Information (24MHz) External Clock Drive Parameter Symbol 1/tCLCL =3 . 5t o2 4 M H zUnit Min. Max. Min. Max. RD pulse width tRLRH 180 - 6t CLCL -70 - ns WR pulse width tWLWH 180 - 6t CLCL -70 - ns Address hold after ALE tLLAX2 15 - t CLCL -27 - ns RD to valid data in tRLDV -1 1 8 -5 t CLCL -90 ns Data hold after RD tRHDX 0- 0 - ns Data float after RD tRHDZ -6 3 - 2 t CLCL -20 ns ALE to valid data in tLLDV -2 0 0 - 8 t CLCL -133 ns Address to valid data in tAVDV -2 2 0 - 9 t CLCL -155 ns ALE to WR or RD tLLWL 75 175 3t CLCL -50 3t CLCL +50 ns Address valid to WRor RD tAVWL 67 - 4t CLCL -97 - ns WR or RDhigh to ALE high tWHLH 17 67 t CLCL -25 t CLCL +25 ns Data valid to WRtransition tQVWX 5- t CLCL -37 - ns Data setup before WR tQVWH 170 - 7t CLCL -122 - ns Data hold after WR tWHQX 15 - t CLCL -27 - ns Address float after RD tRLAZ -0 - 0 n s Parameter Symbol Variable Oscillator (Freq. = 3.5 to 24MHz) Unit Min. Max. Oscillator period tCLCL 41.7 285.7 ns High time tCHCX 12 t CLCL -tCLCX ns Low time tCLCX 12 t CLCL -tCHCX ns Rise time tCLCH -1 2 n s Fall time tCHCL -1 2 ns
38 Oct. 2000 Ver 3.1a AC Characteristics for GMS90 series (33MHz version) V CC =5 V+1 0 % ,-15%; VSS =0 V ; TA =0 °Ct o7 0°C (CL for port 0. ALE and PSENoutputs = 100pF; CL for all other outputs = 80pF) External Program Memory Characteristics † Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Parameter Symbol
33 MHz Oscillator Variable Oscillator
1/tCLCL =3 . 5t o3 3 M H zUnit Min. Max. Min. Max. ALE pulse width tLHLL 40 - 2t CLCL -20 - ns Address setup to ALE tAVLL 10 - t CLCL -20 - ns Address hold after ALE tLLAX 10 - t CLCL -20 - ns ALE low to valid instruction intLLIV -5 6 - 4 t CLCL -65 ns ALE to PSEN tLLPL 15 - t CLCL -15 - ns PSEN pulse width tPLPH 80 - 3t CLCL -20 - ns PSEN to valid instruction intPLIV -3 5 - 3 t CLCL -55 ns Input instruction hold after PSENtPXIX 0- 0 - n s Input instruction float after PSENtPXIZ † -2 0 -t CLCL -10 ns Address valid after PSEN tPXAV † 25 - t CLCL -5 - ns Address to valid instruction intAVIV -9 1 - 5 t CLCL -60 ns Address float to PSEN tAZPL 0- 0 - n s
Oct. 2000 Ver 3.1a 39 AC Characteristics for GMS90 series (33MHz) External Data Memory Characteristics Advance Information (33MHz) External Clock Drive Parameter Symbol 1/tCLCL =3 . 5t o3 3 M H zUnit Min. Max. Min. Max. RD pulse width tRLRH 132 - 6t CLCL -50 - ns WR pulse width tWLWH 132 - 6t CLCL -50 - ns Address hold after ALE tLLAX2 10 - t CLCL -20 - ns RD to valid data in tRLDV -8 1 - 5 t CLCL -70 ns Data hold after RD tRHDX 0- 0 - ns Data float after RD tRHDZ -4 6 - 2 t CLCL -15 ns ALE to valid data in tLLDV -1 5 3 -8 t CLCL -90 ns Address to valid data in tAVDV -1 8 3 -9 t CLCL -90 ns ALE to WR or RD tLLWL 71 111 3t CLCL -20 3t CLCL +20 ns Address valid to WRor RD tAVWL 66 - 4t CLCL -55 - ns WR or RDhigh to ALE high tWHLH 10 40 t CLCL -20 t CLCL +20 ns Data valid to WRtransition tQVWX 5- t CLCL -25 - ns Data setup before WR tQVWH 142 - 7t CLCL -70 - ns Data hold after WR tWHQX 10 - t CLCL -20 - ns Address float after RD tRLAZ -0 - 0 n s Parameter Symbol Variable Oscillator (Freq. = 3.5 to 24MHz) Unit Min. Max. Oscillator period tCLCL 30.3 285.7 ns High time tCHCX 11.5 t CLCL -tCLCX ns Low time tCLCX 11.5 t CLCL -tCHCX ns Rise time tCLCH -5 n s Fall time tCHCL -5 ns
40 Oct. 2000 Ver 3.1a AC Characteristics for GMS90 series (40MHz version) V CC =5 V+1 0 % ,- 15%; VSS=0 V ; TA =0 °Ct o7 0°C (CL for port 0. ALE and PSENoutputs = 100pF; CL for all other outputs = 80pF) External Program Memory Characteristics † Interfacing the GMS90 series to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Parameter Symbol
40 MHz Oscillator Variable Oscillator
1/tCLCL =3 . 5t o4 0 M H zUnit Min. Max. Min. Max. ALE pulse width tLHLL 35 - 2t CLCL -15 - ns Address setup to ALE tAVLL 10 - t CLCL -15 - ns Address hold after ALE tLLAX 10 - t CLCL -15 - ns ALE low to valid instruction intLLIV -5 5 - 4 t CLCL -45 ns ALE to PSEN tLLPL 10 - t CLCL -15 - ns PSEN pulse width tPLPH 60 - 3t CLCL -15 - ns PSEN to valid instruction intPLIV -2 5 - 3 t CLCL -50 ns Input instruction hold after PSENtPXIX 0- 0 - n s Input instruction float after PSENtPXIZ † -1 5 -t CLCL -10 ns Address valid after PSEN tPXAV † 20 - t CLCL -5- n s Address to valid instruction intAVIV -6 5 - 5 t CLCL -60 ns Address float to PSEN tAZPL 5- 5 - n s
Oct. 2000 Ver 3.1a 41 AC Characteristics for GMS90 series (40MHz) External Data Memory Characteristics Advance Information (40MHz) External Clock Drive Parameter Symbol at 40 MHz Clock Variable Clock 1/tCLCL =3 . 5t o4 0 M H zUnit Min. Max. Min. Max. RD pulse width tRLRH 120 - 6t CLCL -30 - ns WR pulse width tWLWH 120 - 6t CLCL -30 - ns Address hold after ALE tLLAX2 10 - t CLCL -15 - ns RD to valid data in tRLDV -7 5 - 5 t CLCL -50 ns Data hold after RD tRHDX 0- 0 - ns Data float after RD tRHDZ -3 8 - 2 t CLCL -12 ns ALE to valid data in tLLDV -1 5 0 -8 t CLCL -50 ns Address to valid data in tAVDV -1 5 0 -9 t CLCL -75 ns ALE to WR or RD tLLWL 60 90 3t CLCL -15 3t CLCL +15 ns Address valid to WRor RD tAVWL 70 - 4t CLCL -30 - ns WR or RDhigh to ALE high tWHLH 10 40 t CLCL -15 t CLCL +15 ns Data valid to WRtransition tQVWX 5- t CLCL -20 - ns Data setup before WR tQVWH 125 - 7t CLCL -50 - ns Data hold after WR tWHQX 5- t CLCL -20 - ns Address float after RD tRLAZ -0 - 0 n s Parameter Symbol Variable Oscillator (Freq. = 3.5 to 40MHz) Unit Min. Max. Oscillator period tCLCL 25 285.7 ns High time tCHCX 10 t CLCL -tCLCX ns Low time tCLCX 10 t CLCL -tCHCX ns Rise time tCLCH -1 0 n s Fall time tCHCL -1 0 ns
Figure 4. External Program Memory Read Cycle
Figure 7. AC Testing: Input, Output Waveforms Figure 8. Float Waveforms Figure 9. External Clock Cycle AC Inputs during testing are driven at VCC -0.5V for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made a VIHmin for a logic ‘1’ and VILmax for a logic ‘0’. occurs and begins to float when a 100mV change from the loaded VOH /VOL level occurs.
0.7 VCC
Figure 10. Recommended Oscillator Circuits propriate values of external components. For Ceramic Resonators, contact resonator manufacturer.
Figure 11. OTP ROM Verification Mode 1
Oct. 2000 Ver 3.1a 47 EPROM CHARACTERISTICS The GMS97C5X, 97L5X are programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It dif- fers from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The GMS97C5X, 97L5X contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an manufac- tured by HME. Table 11 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figure 12 and Figure 13. Figure 14 show the circuit configuration for normal pro- gram memory verification. Reading the Signature Bytes : The GMS97X51/52 signature bytes in locations 030 H and 031H , the GMS97X54/56/58 signature bytes in loca- tions 05EH and 07CH . To read these bytes follow the procedure for EPROM verify, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: Quick-pulse programming The setup for microcontroller quick-pulse programming is shown in Figure 13. Note that the GMS97C5X, 97L5X is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 12. The code byte to be programmed into that location is applied to port 0, RST, PSENa n dp i n so fp o r t2a n d3i nT a b l e 11 are held at the "Program Code Data" levels indicated in Table 11. The ALE/PROGis pulsed low 25 times(10 times for 97X54/56/58) as shown Figure 13. To program the encryption table, repeat the 25 pulses (10 pulses for 97X54/56/58) programming sequence for addresses 0 through 1FH (3FH for 97X54/56/58), using the "Program Encryption Table" levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 25 pulses (10 pulses for 97X54/56/58) programming sequence using the "Pgm Security Bit" levels after one security bit is programmed, further programming of the code memory and Device Location Contents Remarks GMS97X51 30 H 31H E0H 73H Manufacturer ID Device ID GMS97X52 30 H 31H E0H 71H Manufacturer ID Device ID GMS97X54 5E H 7C H E0H 54H Manufacturer ID Device ID GMS97X56 5E H 7C H E0H 56H Manufacturer ID Device ID GMS97X58 5E H 7C H E0H 58H Manufacturer ID Device ID
Figure 12. Programming Configuration tion. The address of the program memory location to be read is applied to ports 1 and 2 as shown in Figure 15. table itself cannot be read out.
the program memory against software piracy. byte, creating an Encrypted Verify byte.
- “0” = Valid low for that pin, "1" = valid high for that pin.
- VCC =5 V– 10% during programming and verification.
- ALE/PROG receives 25 (10 for GMS97X54/56/58) programming pulses while VPP is held at 12.75V.
Each programming pulse is low for 100us (– 10us) and high for a minimum of 10ms. Table 11. EPROM programming modes
1 U U No program lock features
2 P U Further programming of the
3 P P S a m ea sm o d e2 ,a l s ov e r i f yi s
Figure 13. PROG Waveform Figure 14. Program Verification
25 PULSES
10 PULSES
Figure 15. EPROM Programming and Verification
52 Oct. 2000 Ver 3.1a Plastic Package P-LCC-44 (Plastic Leaded Chip-Carrier) 0.180 0.165 UNIT: INCH 44PLCC 0.012 0.0075 0.120 0.090 0.032 0.026 0.630 0.590 min. 0.0200.656 0.650 0.695 0.685 0.656 0.650 0.695 0.685
0.050 BSC
0.021 0.013
Oct. 2000 Ver 3.1a 53 Plastic Package P-DIP-40 (Plastic Dual in-Line Package) UNIT: INCH 2.075 2.045 0.200 max. 0.022 0.015 0.065 0.045
0.100 BSC
0.550 0.530
0.600 BSC
0-15° 0.012 0.008 40DIP 0.140 0.120 min. 0.015
54 Oct. 2000 Ver 3.1a Plastic Package P-MPQF-44 (Plastic Metric Quad Flat Package) 2.35 max. SEE DETAIL "A" 1.03 0.73 0-7° 0.25 0.10 1.60 REF DETAIL "A" UNIT: MM 0.45 0.30
0.80 BSC
2.10 1.95 44MQFP 0.13 0.23 10.10 9.90 13.45 12.95 10.10 9.90 13.45 12.95
MASK ORDER & VERIFICATION SHEET GMS90X5X-GB 1. Customer Information Company Name 2. Device Information 3. Marking Specification 4. Delivery Schedule Customer Sample Date Risk Order YYYY MM DD Quantity Hynix Confirmation Application Order Date YYYY MM DD Tel: Fax: Name & Signature: Package HYNIX YYWW KOREA 5. ROM Code Verification Verification Date: YYYY MM DD Approval Date: YYYY MM DD Please confirm our verification data. I agree with your verification data and confirm you to make mask set. Check Sum: Tel: Fax: Name & Signature: Tel: Fax: Name & Signature: Mask Data HitelChollianInternet File Name: ( .HEX) (Please check mark into ) /G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47/G47Hynix semiconductor pcs Check Sum: Customer should write inside thick line box. This box is written after “5.Verification”. ROM size V o l ./F r e q . GMS90 -GB ª SIEMENS ’92 Customer’s part number Without HYNIX YYWW KOREA 90 -GB ª SIEMENS ’92 40PDIP or 44PLCC 44MQFP /G1043/G1044 /G1043/G1044 /G1043 /G1044C: 5V L: 3V ROM size 1: 4K 2: 8K 4: 16K 6: 24K 8: 32K YYYY MM DD pcs 16K 24K 32K 44MQFP 44PLCC 40PDIP 12MHz 24MHz 40MHz 12MHz 16MHz Normal Super ROM: 16,24,32K ROM: 4K,8K ROM Protection