GMS81604 HYNIX | Alldatasheet
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Technical content
Revision History
Rev 1.2 (Dec. 1998) Redraw package dimension on page 5~6. Rev 1.1 (Nov. 1998) Operating Tem perature, -20~80°C is extended with -20~85°C. Add the "Typical Characteristics" on page 16, 17. Add the unused port guidance on page 48. Revision the information for the OTP programming guidance, recommand using "Intelligent Mode" on page 49. Add the chapter for OTP programming specification as an appendix. Rev 1.0 (Nov. 1997) First Edition
1998 LG Semicon Co., Ltd. All right reserved. Additional information of this manual may be served by LG Semicon offices in Korea or Dist ributors and Representatives listed at address directory. LG Semicon reserves the right to make changes to any information here in at any time without n otice. The information, diagrams and other data in this manual are correct and reliable; however, LG Semicon Co,. Ltd. is in no way responsible for any violations of patents or other rights of the third party gene rated by the use of this manual.
- Using the general EPROM(27C256) APPENDIX A. INSTRUCTION SET B. MASK ORDER SHEET
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER OVERVIEW Memory Proliferation Device ROM Bytes RAM Bytes GMS81604 4K 256 GMS81608 8K 256 GMS81608T 8K EPROM 256 Development Tools The GMS800 family is supported by a full-featured macro assembler, an in-circuit emulators CHOICE- Jr.TM , socket adapters for OTP device. The availability of OTP devices are especially useful for customers expecting frequent code changes and updates. The OTP devices, packaged in plastic pack - ages permit the user to program them once. In addition to the program memory, the configuration fuses must be programmed. GMS81604, GMS81608 In-Circuit Emulators CHOICE-Jr. TM OTP devices GMS81608T (40 DIP) GMS81608T K (42 SDIP) GMS81608T PL (44 pin PLCC) Socket Adapters for OTP Devices OA816A-40PD (40 DIP) OA816A-42SD (42 SDIP) OA816A-44PL (44 PLCC) Assembler LGS Macro Assembler 4K/ 8K On-chip Program Memory
256 Bytes of On-Chip Data RAM
Instruction execution time: 0.5us at 8MHz 2.4V to 5.5V Operating Range 1~8 MHz Operating frequency Basic Interval Timer Four 8-Bit Timer/ Counters (can be used as two 16-bit) Four external interrupt ports Two Programmable Clock Out One Buzzer Driving port
31 Programmable I/O, 4 Input pins,
All LED Direct Drive Output Ports 8-Channel 8-Bit On-Chip Analog to Digital Converter Power Fail Processor (Noise immunity circuit) Power Down Mode (Stop Mode)
Description
The GMS81604/08 is a high-performance CMOS 8-bit microcontroller with 4K or 8K bytes of ROM. The device is one of GMS800 family. The LG Semicon GMS81604/08 is a powerful microcontroller which pr ovides a highly flexible and cost effective solution to many embedded control applications. The GMS81604 /08 provides the following standard features: 8K bytes of ROM, 256 bytes of RAM, 35 I/O lines(33 lines for 40PD IP), 16-bit or 8-bit timer/counter, a precision analog to digital converter, on-chip oscillator and clock circuitry. In addition, the GMS81604/08 supports power saving modes to reduce power consumption. The Stop Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardwa re reset or external interrupt. Feature s LG Semicon GMS81604/08
ROM size Package Ordering code 4K bytes 40DIP GMS81604 42SDIP GMS81604 K 44PLCC GMS81604 PL 8K bytes 40DIP GMS81608 42SDIP GMS81608 K 44PLCC GMS81608 PL 8K bytes (OTP) 40DIP GMS81608T 42SDIP GMS81608T K 44PLCC GMS81608T PL GMS81604/08 LG Semicon
Figure 1. Block Diagram
← "X" means 4(4K bytes) or 8(8K bytes).
42 SDIP 40 PDIP
44 PLCC
Figure 2. Pin Connections
UNIT: INCH 1.470 1.450 0.020 0.016 0.045 0.035
0.070 BSC
0.550 0.530
0.600 BSC
0-15° 0.012 0.008 42SDIP 0.140 0.120 min. 0.015 0.190 max. UNIT: INCH 2.075 2.045 0.200 max. 0.022 0.015 0.065 0.045
0.100 BSC
0.550 0.530 0-15° 0.012 0.008 40DIP 0.140 0.120 min. 0.015
0.180 0.165 UNIT: INCH 44PLCC 0.012 0.0075 0.120 0.090 0.032 0.026 0.630 0.590 min. 0.0200.656 0.650 0.695 0.685 0.656 0.650 0.695 0.685
0.050 BSC
VDD : Supply voltage. VSS : Circuit Ground. TEST : For test purposes only. Connect it to V DD . RESET : Reset the MCU. XIN : Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XOUT : Output from the inverting oscillator amplifier. R00~R07 : R0 is an 8-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R0 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R10~R17 : R1 is an 8-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R1 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R40~R47 : R4 is an 8-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R4 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. In addition, Port 4 serves the functions of the various following special features. Port Pin Alternate Function R40 INT0 (External Interrupt 0) R41 INT1 (External Interrupt 1) R42 R43 INT2 (External Interrupt 2) INT3 (External Interrupt 3) R44 R45 EC0 (External Count Input to Timer/ Counter 0) EC2 (External Count Input to Timer/ Counter 2) R46 R47 T1O (Timer 1 Clock-Out) T3O (Timer 3 Clock-Out) R50, R51, R55 : R5 is a 3-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R5 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R50 and R51 differs in having internal pull-ups. Port R55 serves the functions of special features. Port Pin Alternate Function R55 BUZ (Square wave output for Buzzer driving) R60~R67 : R6 is an 8-bit, CMOS, I/O port. R60~R63 can be used as only input, can not be output, R64~R67 are bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R64~R67 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R6 serves the functions of following special features. Port Pin Alternate Function R60 R61 R62 R63 R64 R65 R66 R67 AN0 (ADC input 0) AN1 (ADC input 1) AN2 (ADC input 2) AN3 (ADC input 3) AN4 (ADC input 4) AN5 (ADC input 5) AN6 (ADC input 6) AN7 (ADC input 7) AV DD : Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. LG Semicon GMS81604/08
Port Pin I/O Descriptions Pull-up/ Pull-down RESET STOP ModePrimary Functions Secondary Functions VDD - Power supply to MCU - - - - VSS - Ground - - - - AV DD - Power supply for ADC - - - - TEST I Test mode - - - - RESET I Reset the MCU - Pull-up Low Last state XIN I Oscillation input - - Oscillation Low XOUT O Oscillation output - - Oscillation High R00~R07 I/O General I/O - - Input 3) Last state R10~R17 I/O General I/O - - Input 3) Last state R40/INT0 R41/INT1 R42/INT2 R43/INT3 R44/ EC0 R45/ EC2 R46/T1O R47/T3O I/O I/O I/O I/O I/O I/O I/O I/O General I/O External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External count input 0 External count input 2 Timer 1 output Timer 3 output - Input 3) Last state R50 1) R51 1) R55/BUZ I/O I/O I/O General I/O Buzzer driving output Pull-up 2) Pull-up 2) Input 3) Last state R60/AN0 R61/AN1 R62/AN2 R63/AN3 R64/AN4 R65/AN5 R66/AN6 R67/AN7 I I I I I/O I/O I/O I/O General Input General I/O Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 - Input 3) Last state NOTES: 1. R50 and R51 are not physically served on 40 pin package. 2. When input mode is selected, pull-up is activated. In output mode, pull-up is de-activated . 3. In reset status, status of R50,R51 are weak high (Typ. impedance 50~100k Ω ). Other pin impedance is very high(High-Z). GMS81604/08 LG Semicon
Rd. PROTECT DIODE PROTECT DIODE VSS VDD DIRECTION REG. DATA REG. R00~R07, R10~R17 DATA BUS DATA BUS DATA BUS PMR4 ALTERNATE FUNCTION EX) INT0 Rd. MUX DATA REG. DIRECTION REG. R40/INT0, R41/INT1, R42/INT2, R43/INT3, R44/ EC0 , R45/ EC2 DATA BUS DATA BUS Selection (PMR4 or PMR5) ALTERNATE FUNCTION EX) T1O DIRECTION REG. Rd. DATA REG. DATA BUS MUX MUX R46/T1O, R47/T3O, R55/BUZ LG Semicon GMS81604/08
Rd. Rd. Ch. Select R60/AN0, R61/AN1, R62/AN2, R63/AN3 DATA REG. DIRECTION REG. Rd. MUX DATA BUS DATA BUS DATA BUS TO A/D Converter Ch. Select Rd. 0: Output 1: Reset, Input, AD ch. select R64/AN4, R65/AN5, R66/AN6, R67/AN7 DATA REG. DIRECTION REG. Rd. MUX DATA BUS DATA BUS DATA BUS PULL-UP RESISTOR INPUT MODE: PULL-UP RESISTOR IS ACTIVATED. OUTPUT MODE: PULL-UP RESISTOR IS DE-ACTIVATED. R50, R51 GMS81604/08 LG Semicon
OTP: No P-Ch diode TEST XIN XOUT STOP XIN , X OUT LG Semicon GMS81604/08
ELECTRICAL CHARACTERISTICS
Recommended Operating Conditions Parameter Symbol Condition Specifications Unit Min. Max. Supply Voltage VDD fXIN = 8 MHz fXIN = 4 MHz 4.5 2.4 5.5 5.5 V Operating Frequency fXIN VDD = 4.5~5.5V VDD = 2.4~5.5V
4.2 MHz
Operating Temperature TOPR -20 85 °C Voltage on any pin with Maximum current sunk by (I OL per I/O Pin) . . . . 20 mA Maximum output current sourced Notice: Stresses above those listed under "Absolute Maxi - mum Ratings" may cause permanent damage to the device. This is a stress rating only and func - tional operation of the device at these of any other conditions above those indicated in the op - erational sections of this specification is not im - plied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. GMS81604/08 LG Semicon
DC Characteristics ( 5V ) (V DD = 5.0V ± 10%, V SS = 0V, T A = -20 ~ 85 °C, f XIN = 8 MHz) Parameter Pin Symbol Test Condition Specifications Unit Min. Typ.* Max. Input High Voltage XIN, RESET , R40~R45 VIH1 - 0.8V DD - VDD V R0,R1,R46,R47 R5,R6 VIH2 - 0.7V DD - VDD V Input Low Voltage XIN, RESET , R40~R45 VIL1 - 0 - 0.2V DD V R0,R1,R46,R47 R5,R6 VIL2 - 0 - 0.3V DD V Output High Voltage R0,R1,R4,R5,R6 VOH VDD = 5V IOH = -2mA V DD -1.0 V DD -0.4 - V Output Low Voltage R0,R1,R4,R5,R6 VOL VDD = 5V IOL = 10mA - 0.6 1.0 V Power Fail Detect Voltage VDD VPFD VDD =3~4V 3.0 - 4.0 V Input Leakage Current RESET , R0, R1, R4, R5, R6 IIH VI = V DD -5.0 - 5.0 uA IIL VI = 0V -5.0 - 5.0 uA Input Pull-up Current RESET IP1 VDD = 5V -180 -120 -30 uA R50, R51 IP2 VDD = 5V -90 -60 -15 uA Power Current Operating mode IDD fXIN =4MHz fXIN =8MHz - 4.5 15 mA STOP mode ISTOP VDD = 5V - 2 20 uA Hysteresis RESET , R40~R45 VT+ ~V T- VDD = 5V 0.5 0.8 - V * : Data in "Typ" column is at 5 V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. A/D Converter Characteristics ( 5V ) (V DD = 5.0V ± 10%, V AIN = 5.0V, V SS = 0V, T A = 25 °C) Parameter Symbol Specifications Unit Min. Typ.* Max. Analog Input Range VAIN VSS - VAVDD V Non-linearity Error NLE - 0.7 ± 1.5 LSB Differential Non-linearity Error NDIF - 0.1 ± 0.5 LSB Zero Offset Error NOFF - 1.5 ± 2.5 LSB Full Scale Error NFS - 1.0 ± 1.5 LSB Accuracy ACC - 2.0 ± 3.0 LSB AV DD Input Current IAVDD - 0.5 1.0 mA Conversion Time TCONV - - 40 uS Analog power supply Input Range VAVDD 4.5 5.0 5.5 V * : Data in "Typ" column is at 5 V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. LG Semicon GMS81604/08
DC Characteristics ( 3V ) (V DD = 3.0V ± 10%, V SS = 0V, T A = -20 ~ 85 °C, f XIN = 4 MHz) Parameter Pin Symbol Test Condition Specifications Unit Min. Typ.* Max. Input High Voltage XIN, RESET , R40~R45 VIH1 - 0.8V DD - VDD V R0,R1,R46,R47 R5,R6 VIH2 - 0.7V DD - VDD V Input Low Voltage XIN, RESET , R40~R45 VIL1 - 0 - 0.2V DD V R0,R1,R46,R47 R5,R6 VIL2 - 0 - 0.3V DD V Output High Voltage R0,R1,R4,R5,R6 VOH VDD = 3V IOH = -1mA V DD -0.5 VDD -0.3 - V Output Low Voltage R0,R1,R4,R5,R6 VOL VDD = 3V IOL = 5mA - 0.5 0.7 V Power Fail Detect Voltage** - - - - - - V Input Leakage Current RESET , R0, R1, R4, R5, R6 IIH VI = V DD -3.0 - 3.0 uA IIL VI = 0V -3.0 - 3.0 uA Input Pull-up Current RESET IP1 VDD = 3V -60 -40 -15 uA R50, R51 IP2 VDD = 3V -30 -20 -7.5 uA Power Current Operating mode IDD fXIN =4MHz - 2 5 mA STOP mode ISTOP VDD = 3V - 1 10 uA Hysteresis RESET , R40~R45 VT+ ~V T- VDD = 3V 0.3 0.6 - V * : Data in "Typ" column is at 3 V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. **: Power Fail Detection function is not available on 3V operation. A/D Converter Characteristics ( 3V ) (V DD = 3.0V ± 10%, V AIN = 3.0V, V SS = 0V, T A = 25 °C) Parameter Symbol Specifications Unit Min. Typ.* Max. Analog Input Range VAIN VSS - VAVDD V Non-linearity Error NLE - 0.2 ± 1.0 LSB Differential Non-linearity Error NDIF - 0.1 ± 0.5 LSB Zero Offset Error NOFF - 2.0 ± 2.5 LSB Full Scale Error NFS - 1.0 ± 1.5 LSB Accuracy ACC - 2.0 ± 3.0 LSB AV DD Input Current IAVDD - 0.3 0.5 mA Conversion Time TCONV - - 40 uS Analog power supply Input Range VAVDD 2.7 3.0 3.3 V * : Data in "Typ" column is at 3 V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. GMS81604/08 LG Semicon
Min. Typ. Max. Main clock frequency XIN fXIN 1 - 8 MHz Oscillation stabilization Time XIN, X OUT tST 20 - - ms External Clock Pulse Width XIN tCPW 80 - - ns External Clock Transition Time XIN tRCP , tFCP - - 20 ns Interrupt Pulse Width INT0, INT1, INT2, INT3 tIW 2 - - tSYS * RESET Input Low Width RESET tRST 8 - - tSYS * Event Counter Input Pulse Width EC0 , EC2 tECW 2 - - tSYS * Event Counter Transition Time EC0 , EC2 tREC , tFEC - - 20 ns *: t SYS is 2/f XIN . Timing Chart XIN 1 / f XIN tRCP tFCP tCPW tCPW 0.1V DD 0.9V DD tIW 0.8V DD 0.2V DD tIW INT0, INT1 INT2, INT3 RESET tRST 0.2V DD EC0 , EC2 tREC tFEC tECW tECW 0.8V DD 0.2V DD LG Semicon GMS81604/08
These parameters are for design guidance only and are not tested. 1 2 3 40 IOL - V OL IOL (mA) VDD =5.0V TA=25 °C VOL (V) VDD =5V 1 2 3 40 IOH - V OH IOH (mA) VDD =5.0V TA=25 °C VDD -VOH (V) 2 3 4 50 6 (V) IDD - V DD IDD (mA) TA=25 °C VDD fXIN = 4MHz fXIN = 8MHz 2 3 4 50 6 (V) ISTOP ISTOP (uA) TA=25 °C VDD Operating area fXIN (MHz) TA = -20~80 °C VDD (V)2 3 4 5 GMS81604/08 LG Semicon
0.5 1.0 1.5 2.00 IOL - V OL IOL (mA) VDD =3.0V TA=25 °C VOL (V) VDD =3.0V 0.5 1.0 1.5 2.00 IOH - V OH IOH (mA) VDD -VOH (V) VDD =3.0V TA=25 °C LG Semicon GMS81604/08
user RAM, control registers and Stack. are in address C0 H to FF H. will have an indeterminate effect. in each peripheral sections. Legend - = Unimplemented locations. 2) The register BITR and CKCTLR are located at same address. Address D3H is read as BITR, as written to CKCTLR. 4) Only bit 0 of ADCM can be read.
256 BYTES
Figure 9. Data Memory
Control Registers for the GMS81604/08 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C0 H R0 R0 port data register C1 H R0DD R0 port direction register C2 H R1 R1 port data register C3 H R1DD R1 port direction register C8 H R4 R4 port data register C9 H R4DD R4 port direction register CA H R5 R5 port data register CB H R5DD R5 port direction register CC H R6 R6 port data register CD H R6DD R6 port direction register D0 H PMR4 T3S T1S EC2S EC0S INT3S INT2S INT1S INT0S D1 H PMR5 - - BUZS - - - - - D3 H1) BITR Basic Interval Timer data register D3 H1) CKCTLR - - WDTON ENPCK BTCL BTS2 BTS1 BTS0 E0 H WDTR - WDTCL 6-bit Watch Dog Counter register E2 H TM0 CAP0 T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0 E3 H TM2 CAP2 T3ST T3SL1 T3SL0 T2ST T2CN T2SL1 T2SL0 E4 H T0/ TDR0/ CDR0 Timer 0 register/ Timer data register 0/ Capture data register 0 E5 H T1/ TDR1/ CDR1 Timer 1 register/ Timer data register 1/ Capture data register 1 E6 H T2/ TDR2/ CDR2 Timer 2 register/ Timer data register 2/ Capture data register 2 E7 H T3/ TDR3/ CDR3 Timer 3 register/ Timer data register 3/ Capture data register 3 E8 H ADCM - - ADEN ADS2 ADS1 ADS0 ADST ADSF E9 H ADR ADC result data register EC H BUR BUCK1 BUCK0 BU5 BU4 BU3 BU2 BU1 BU0 ED H2) PFDR - - - - - PFD PFR PFS F4 H IENL AE WDTE BITE - - - - - F5 H IRQL AIF WDTIF BITIF - - - - - F6 H IENH INT0E INT1E INT2E INT3E T0E T1E T2E T3E F7 H IRQH INT0IF INT1IF INT2IF INT3IF T0IF T1IF T2IF T3IF F8 H IEDS IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L Legend - = Unimplemented locations. NOTES: 1) The register BITR and CKCTLR are located at same address. Address D3 H is read as BITR, written to CKCTLR. 2) The register PFDR only be implemented on device, not on In-circuit Emulator. GMS81604/08 LG Semicon
are used as a general purpose input port. figure these pins as output or input. "0" to the corresponding bit to specify as an input pin. during initial setting as shown in Figure 10. whereas writing to it will write to the port latch. used as a corresponding alternate features. Figure 10. Example port I/O assignment
R5 and R5DD registers: R5 is a 3-bit bidirectional I/O port (address CA H). R50, R51 and R55 only are physically implemented on this device. R50, R51 have internal pullups which is activated on input but deactivated on output. As input, these pins that are externally pull low will source current (I P2 on the DC characteristics) because of the internal pullups. Caution: Pins R50, R51 are present on 42SDIP, 44PLCC package only, but not on 40DIP . Refer to Pin as - signment. Each pin is individually configurable as input and output through the R5DD register (address CB H). Port Pin Alternate Function R55 BUZ (Square-wave output for Buzzer driving) The control register PMR5 (address D1 H) controls the selection alternate function. After reset, this value is "0", port may be used as general I/O ports. To use buzzer function, write "1" to the PMR5. R47 R46 R45 R44 R43 R42 R41 R40 Port 4 Data Register ADDRESS: C8 H RESET VALUE: Undefined R47 R46 R45 R44 R43 R42 R41 R40R4DD ADDRESS: C9 H RESET VALUE: 00000000 Direction select 0: Input 1: Output Input/ Output data Port 4 Direction Register T3S T1S EC2S EC0S INT3S INT2S INT1S INT0SPMR4 ADDRESS: D0 H RESET VALUE: 00000000 0: R41 1: INT1 0: R47 1: T3O 0: R45 1: EC2 0: R46 1: T1O 0: R44 1: EC0 0: R43 1: INT3 0: R42 1: INT2 0: R40 1: INT0 MSB LSBIEDS ADDRESS: F8 H RESET VALUE: 00000000Edge Selection Register External Interrupt Edge select 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling) INT3 INT2 INT1 INT0 Port 4 Mode Register - - R55 - - - R51 R50 Port 5 Data Register ADDRESS: CA H RESET VALUE: Undefined - - R55 - - - R51 R50R5DD ADDRESS: CB H RESET VALUE: --0---00 Direction select 0: Input 1: Output Input/ Output data Port 5 Direction Register - - BUZS - - - - -PMR5 ADDRESS: D1 H RESET VALUE: --0-----Port 5 Mode Register 0: R55 1: BUZ (Buzzer Port) GMS81604/08 LG Semicon
R6 and R6DD registers: R6 is an 8-bit port (address CC H ). Pins R64~R67 are individually configurable as input and output through the R6DD register (address CD H ), but pins R60~R63 are input only. Port Pin Alternate Function R60 R61 R62 R63 R64 R65 R66 R67 AN0 (ADC input 0) AN1 (ADC input 1) AN2 (ADC input 2) AN3 (ADC input 3) AN4 (ADC input 4) AN5 (ADC input 5) AN6 (ADC input 6) AN7 (ADC input 7) R6DD (address CDH ) controls the direction of the R6 pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. On the initial RESET, R60 can not be used digital input port, because this port is selected as an ana- log input port by ADCM register. To use this port as a digital I/O port, change the value of lower 4 bits of ADCM (address 0E8H ). On the other hand, R6 port, all eight pins can not be used as digital I/O port simultaneousely. At least one pin is used as an analog input. R67 R66 R65 R64 R63 R62 R61 R60 Port 6 Data Register ADDRESS: CC H RESET VALUE: Undefined R67 R66 R65 R64 R63 R62 R61 R60R6DD ADDRESS: CD H RESET VALUE: 0000---- Direction select 0: Input 1: Output Input/ Output data Port 6 Direction Register Fixed as Input. Can not write. LG Semicon GMS81604/08
The GMS81604 has four Timer/Counter registers. an event has occurred (i.e. timer match). combine them. Also Timer 2 and Timer 3 are same. Timer data register correspondingly. TM0 and TM2 as shown in right Table. same with Timer 0, Timer 1, respectively.
0 X X 8-bit Timer 8-bit Timer
1 X X 8-bit Capture 8-bit Timer
When cleared, stop the counting. When cleared, stop the counting. TIMER 1 TIMER 0TM2 is in Figure 14. If this mode selected, the Timer 0 are used as a 16-bit timer mode. The Timer 1 is engaged to the Ti mer 0. The source clock is selected by bits T0SL1 and T0SL0. Figure 13. TM0: Timer 0, Timer 1 Mode Register
ers are same with Timer 0 and Timer 1.
- To use as an 8-bit timer/counter mode, bit CAP 0
control bits TxSL1, TxSL0 of register TMx). reading it as a Tx, written to TDRx.
0 X ≠ 0 ≠ 0 X X X X
Figure 16. 8-bit Timer/Counter Mode
0000 H until it matches TDR0, TDR1 and then resets
internal or external clock by bit T0SL1, T0SL0.
0 X 0 0 X X X X
Figure 19. 16-bit Timer/Counter Mode Figure 20. Timer Count Operation
Timer 1 still operates as an 8-bit timer/counter. also be used as a capture mode. x register is cleared and restarts by hardware. The CDRx and TDRx are in same address.
1 X ≠ 0 ≠ 0 X X X X
THIS FIGURE IS A EXAMPLE OF THE TIMER 0. MAY BE CHANGED CORRESPONDINGLY. Figure 21. 8-bit Capture Mode
that the Timer register is being run will 16 bits.
1 X 0 0 X X X X
REGISTERS AND FLAGS MAY BE CHANGED. Figure 22. 16-bit Capture Mode
nected to AV DD of ladder resistance of A/D module. version time takes maximum 40 uS (at f XIN =4 MHz). Figure 23. A/D Block Diagram
0: A/D conversion is in process. 1: Setting this bit starts an A/D conversion. After one cycle, bit is cleared to "0". consumes no operating current. Figure 24. ADCM: A/D Converter Control Register
circuit is shown in Figure 28. 12 interrupt sources are provided including the Reset. is set by finishing the analog to digital conversion. which set by a match in Watch dog timer register. Interrupt enable registers are shown in Figure 29. hardware, thus any other interrupt are inhibited. instruction, I-flag is set to "1" by hardware. Figure 28. Block Diagram of Interrupt Function
factor, device provides reduced power of STOP. instruction executed before going into the Stop mode. In the Stop mode, the on-chip oscillator is stopped. status of peripherals during Stop mode is shown below. stabilize (minimum 20 msec). two to next line of the STOP instruction. If I-flag = 1, the normal interrupt response takes place. will not vector to interrupt service routine. Figure 37. Timing of Stop Release by External Interrupt
By reset, exit from Stop mode is shown in Figure 38. PC: Program Counter contents after the event. N: Address of STOP instruction. Time can not be control by software. Figure 38. Timing of Stop Mode Release by Reset
Figure 43. Power Fail Processor Situations
All unused ports should be set properly that current flow through the port does not exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relation - ship with external circuit. In input mode, the pin im - pedance viewing from external MCU is very high that the current does not flow. But input voltage level should be V SS or V DD . Be careful that if unspecified voltage, i.e. if unfirmed voltage level is applied to input pin, there can be little current ( max. 1mA at around 2V) flow. If it is not appropriate to set to input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. GMS81604/08 LG Semicon
GMS81608T (OTP) PROGRAMMING The GMS81608T is one-time PROM (OTP) micro - controller with 8K bytes electrically programmable read only memory for the GMS81604/08 system evaluation, first production and fast mass production. The programming to the OTP device, user can have two way. One is using the universal programmer which is support LGS microcontrollers, other is using the general EPROM programmer. 1. Using the Universal programmer Third party universal programmer support to program the GMS81608T microcontrollers and lists are shown as below. Manufacturer: Advantech Web site: http://www.aec.com.tw Programmer: LabTool-48 Manufacturer: Hi-Lo systems Web site: http://www.hilosystems.com.tw Programmer: ALL-11, GANG-08 Socket adapters are supported by third party program - mer manufacturer. 2. Using the general EPROM(27C256) programmer The programming algorithm is simmilar with the stan - dart EPROM 27C256. It give some convience that user can use standard EPROM programmer. Make sure that 1ms programming pulse must be used, it gener - ally called "Intelligent Mode". Do not use 100us programming pulse mode, "Quick Pulse Mode". When user use general EPROM programmer, socket adaper is essencially required. It convert pin to fit the pin of general 27C256 EPROM. Three type socket adapters are provided according to package variation as below table. Socket Adapter Package Type OA816A-40SD 40 pin DIP OA816A-42SD 42 pin SDIP OA816A-42PL 44 pin PLCC With these socket adapters, the GMS81608T can easy be programming and verifying using 27C256 EPROM mode on general-purpose PROM programmer. In assembler and file type, two files are generated after compiling. One is "*.HEX", another is "*.OTP". The "*.HEX" file is used for emulation in circuit emulator (CHOICE-Dr TM or CHOICE-Jr TM ) and "*.OTP" file is used for programming to the OTP device. Programming Procedure 1. Select the EPROM device and manufacturer on EPROM programmer (Intel 27C256). 2. Select the programming algorithm as an Intelligent mode (apply 1ms writing pulse), not a Quick pulse mode. 3. Load the file (*.OTP) to the programmer. 4. Set the programming address range as below table. Address Set Value Buffer start address 6000 H Buffer end address 7FFF H Device start address 6000 H 5. Mount the socket adapter with the GMS81608T on the PROM programmer. 6. Start the PROM programmer to programming/ verifying. LG Semicon GMS81604/08
LG Semicon GMS81608T PROGRAMMING SPECIFICATION
GMS81608T PROGRAMMING SPECIFICATION LG Semicon
Pin No. MCU Mode OTP Mode
1 TEST I VPP -
2 AV DD - (1) -
3 R67/AN7 I/O (1) -
4 R66/AN6 I/O (1) -
5 R65/AN5 I/O (1) -
6 R64/AN4 I/O (1) -
7 R63/AN3 I (1) -
8 R62/AN2 I (1) -
9 R61/AN1 I (1) -
10 R60/AN0 I (1) -
11 R47/T3O I/O A4 I
12 R46/T1O I/O (1) -
13 R45/ EC2 I/O CE I
14 R44/ EC0 I/O OE I
15 R43/INT3 I/O A3 I
16 R42/INT2 I/O A2 I
17 R41/INT1 I/O A1 I
18 R40/INT0 I/O A0 I
19 R55/BUZ I/O (1) -
20 VDD - VDD -
NOTES: (1) Pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) Pins must be connected to V DD . (3) X OUT pin must be opened during programming. Pin No. MCU Mode OTP Mode
21 R17 I/O A12 I
22 R16 I/O A11 I
23 R15 I/O A10 I
24 R14 I/O A9 I
25 R13 I/O A8 I
26 R12 I/O A7 I
27 R11 I/O A6 I
28 R10 I/O A5 I
29 R07 I/O O7 O
30 R06 I/O O6 O
31 R05 I/O O5 O
32 R04 I/O O4 O
33 R03 I/O O3 O
34 R02 I/O O2 O
35 R01 I/O O1 O
36 R00 I/O O0 O
37 RESET I (1) -
38 XOUT O (3) -
39 XIN I (1) -
40 VSS - (1) -
I/O: Input/Output Pin I: Input Pin O: Output Pin LG Semicon GMS81608T PROGRAMMING SPECIFICATION
Pin No. MCU Mode OTP Mode
21 R51 I/O (2) -
NOTES: (1) Pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) Pins must be connected to V DD . (3) X OUT pin must be opened during programming. Pin No. MCU Mode OTP Mode
22 R50 I/O (2) -
23 R17 I/O A12 I
24 R16 I/O A11 I
25 R15 I/O A10 I
26 R14 I/O A9 I
27 R13 I/O A8 I
28 R12 I/O A7 I
29 R11 I/O A6 I
30 R10 I/O A5 I
31 R07 I/O O7 O
32 R06 I/O O6 O
33 R05 I/O O5 O
34 R04 I/O O4 O
35 R03 I/O O3 O
36 R02 I/O O2 O
37 R01 I/O O1 O
38 R00 I/O O0 O
39 RESET I (1) -
40 XOUT O (3) -
41 XIN I (1) -
42 VSS - (1) -
I/O: Input/Output Pin I: Input Pin O: Output Pin GMS81608T PROGRAMMING SPECIFICATION LG Semicon
Pin No. MCU Mode OTP Mode 1 N.C. - N.C. -
2 TEST I VPP -
3 AV DD - (1) -
4 R67/AN7 I/O (1) -
5 R66/AN6 I/O (1) -
6 R65/AN5 I/O (1) -
7 R64/AN4 I/O (1) -
8 R63/AN3 I (1) -
9 R62/AN2 I (1) -
10 R61/AN1 I (1) -
11 R60/AN0 I (1) -
12 R47/T3O I/O A4 I
13 R46/T1O I/O (1) -
14 R45/ EC2 I/O CE I
15 R44/ EC0 I/O OE I
16 R43/INT3 I/O A3 I
17 N.C. - N.C. -
18 R42/INT2 I/O A2 I
19 R41/INT1 I/O A1 I
20 R40/INT0 I/O A0 I
21 R55/BUZ I/O (1) -
22 VDD - VDD -
NOTES: (1) Pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) Pins must be connected to V DD . (3) X OUT pin must be opened during programming. Pin No. MCU Mode OTP Mode
23 R51 I/O (2) -
24 R50 I/O (2) -
25 R17 I/O A12 I
26 R16 I/O A11 I
27 R15 I/O A10 I
28 R14 I/O A9 I
29 R13 I/O A8 I
30 R12 I/O A7 I
31 R11 I/O A6 I
32 R10 I/O A5 I
33 R07 I/O O7 O
34 R06 I/O O6 O
35 R05 I/O O5 O
36 R04 I/O O4 O
37 R03 I/O O3 O
38 R02 I/O O2 O
39 R01 I/O O1 O
40 R00 I/O O0 O
41 RESET I (1) -
42 XOUT O (3) -
43 XIN I (1) -
44 VSS - (1) -
I/O: Input/Output Pin I: Input Pin O: Output Pin LG Semicon GMS81608T PROGRAMMING SPECIFICATION
PIN FUNCTION (OTP Mode) VPP (Program Voltage) VPP is the input for the program voltage for programming the EPROM. CE ( Chip Enable) CE is the input for programming and verifying internal EPROM. OE (Output Enable) OE is the input of data output control signal for verify. A0~A 12 (Address Bus) A0~A 12 are address input pins for internal EPROM. O0~O 7 (EPROM Data Bus) These are data bus for internal EPROM. PROGRAMMING The GMS81608T has address A 0~A 12 pins. Therefore, the programmer just program 8K bytes data of addresses 6000 H to 7FFF H into the GMS81608T OTP device. During the programming addresses A 13 , A 14 , A 15 of programmer must be pulled to a logic high. When the programmer write the data from 6000 H to 7FFF H , consequently, the data actually will be written into addresses E000 H to FFFF H of the OTP device. Programming Flow 1. The data format to be programmed is made up of Motorola S1 format. Ex) "Motorola S1" format; S00B00005741544348363038DF S1246000E1FF3BFF04A13F8F06E1C1711BFF3F1B003E1B00371B00361BFF3D1B003C1BFF3385 S12460211BFF321BFF351B92131B7FCC1BF3D61B17FD1BFCFC1B821B1BE01D1B8E191BFD18B1 S1057FF2941FD6 S1057FFEFF1F5F S9030000FC 2. Down load above data into programmer from PC. 3. Programming the data from address 6000 H to 7FFF H into the OTP MCU, the data must be turned over respectively, and then record the data into the OTP device. When read the data, it also must be turned over. Ex) 00(00000000) → FF(11111111), 76(01110110) → 89(10001001), FF (11111111)→ 00(00000000) etc. 4. Of course, the check sum is result of the sum of whole data from address 6000 H to 7FFF H in the file (not reverse data of the OTP MCU). * When GMS81608T shipped, the blank data of GMS81608T is initially 00 H (not FF H ). GMS81608T PROGRAMMING SPECIFICATION LG Semicon
xxxxxxxx.OTP FF FF FF Down Loadin gProgram 6000 H 6001 H 6002 H 6003 H 6004 H 6005 H 6006 H 6007 H 7FF2 H 7FF3 H 7FFE H 7FFF H FF FF FF 6000 H 6001 H 6002 H 6003 H 6004 H 6005 H 6006 H 6007 H 7FF2 H 7FF3 H 7FFE H 7FFF H FC E000 H E001 H E002 H E003 H E004 H E005 H E006 H E007 H FFF2 H FFF3 H FFFE H FFFF H Reading Verify Up Loading Data Addres sData Addres sData Programmer Buffer Checksum = E1+FF+3B+FF+04+A1+3F+8F+ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 94+1F+ ⋅ ⋅ ⋅ ⋅ +FF+1F Programming Example Program area
8 K BYTES
File Type: Motorola S-format GMS81608T 6000 H 7FFF H Address xxxxxxxx.OTP Universal Programmer Down Loading Program Verify Reading Buffer Start Address: 6000 H Buffer End Address: 7FFF H Device Start Address: E000 H Programming Flow LG Semicon GMS81608T PROGRAMMING SPECIFICATION
(TA = 25 °C ± 5°C) Mode CE OE A0~A 15 VPP V DD O 0~O 7 Read X X VDD 5.0V DOUT Output Disable VIH VIH X VDD 5.0V Hi-Z Programming VIL VIH X VPP VDD DIN Program Verify X X VPP VDD DOUT NOTES: 1. X = Either V IL or V IH 3. See DC Characteristics Table for V DD and V PP voltages during programming.DC CHARACTERISTICS (V SS =0 V, T A = 25 °C ± 5°C) Symbol Item Min Typ Max Unit Test condition VPP VPP supply voltage 12.0 - 13.0 V VDD (1) VDD supply voltage 5.75 - 6.25 V IPP (2) VPP supply current 50 mA CE =V IL IDD (2) VDD supply current 30 mA VIH Input high voltage 0.8 V DD V VIL Input low voltage 0.2 V DD V VOH Output high voltage VDD -1.0 V IOH = -2.5 mA VOL Output low voltage 0.4 V IOL = 2.1 mA IIL Input leakage current 5 uA NOTES: 1. V DD must be applied simultaneously or before V PP and removed simultaneously or after V PP . 2. The maximum current value is with outputs O 0 to O 7 unloaded. GMS81608T PROGRAMMING SPECIFICATION LG Semicon
NOTES: 1. The input timing reference level is 1.0 V for a V IL and 4.0V for a V IH at V DD =5.0V 2. To read the output data, transition requires on the OE from the high to the low after address setup time t AS . Address Valid tOE Valid Output tDH Addresses OE Output High-Z VIH VIL VIH VIL VIH VIL tAS (2) READING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be steady May change from H to L May change from L to H Do not care any change permitted Does not apply W ill be steady W ill be changing from H to L W ill be changing from L to H Changing state unknown Center line is high impedance "Off" state SWITCHING WAVEFORMS LG Semicon GMS81608T PROGRAMMING SPECIFICATION
NOTES: 1. The input timing reference level is 1.0 V for a V IL and 4.0V for a V IH at V DD =5.0V tDFP Addresses Data High-Z VIH VIL 12.5V VDD VPP VDD CE OE 6.0V 5.0V tAS tDS tVPS tVDS tOPW tPW tOES Program Program Verify tDH VIH VIL VIH VIL VIH VIL tAH Address Stable Data In Stable Data out Valid tOE PROGRAMMING ALGORITHM WAVEFORMS GMS81608T PROGRAMMING SPECIFICATION LG Semicon
AC READING CHARACTERISTICS (V SS =0 V, T A = 25 °C ± 5°C) Symbol Item Min Typ Max Unit Test condition tAS Address setup time 2 us tOE Data output delay time 200 ns tDH Data hold time 0 ns NOTES: 1. V DD must be applied simultaneously or before V PP and removed simultaneously or after V PP . AC PROGRAMMING CHARACTERISTICS (V SS =0 V, T A = 25 °C ± 5°C; See DC Characteristics Table for V DD and V PP voltages.) Symbol Item Min Typ Max Unit Condition* (Note 1) tAS Address set-up time 2 us tOES OE set-up time 2 us tDS Data setup time 2 us tAH Address hold time 0 us tDH Data hold time 1 us tDFP Output disable delay time 0 us tVPS VPP setup time 2 us tVDS VDD setup time 2 us tPW Program pulse width 0.95 1.0 1.05 ms tOPW CE pulse width when over programming 2.85 78.75 ms (Note 2) tOE Data output delay time 200 ns *AC CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%) . . . . 20 ns NOTES: 1. V DD must be applied simultaneously or before V PP and removed simultaneously or after V PP . 2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X (Intelligent Programming Algorithm).Refer to flow chart of page 13. LG Semicon GMS81608T PROGRAMMING SPECIFICATION
VDD = 6.0V VPP = 12.5V X = 0 PROGRAM ONE 1 ms PULSE INCREMENT X VERIFY BYTE VERIFY ONE BYTE LAST ADDRESS ? VDD = V PP = 5.0V COMPARE ALL BYTES TO ORIGINAL DATA DEVICE PASSED INCREMENT ADDRESS YES NO FAIL PASS FAIL PASS NO YES FAIL PASS DEVICE FAILED PROGRAM ONE PULSE OF 3X msec DURATION X = 25 ? ADDRESS= FIRST LOCATION Intelligent Programming Algorithm GMS81608T PROGRAMMING SPECIFICATION LG Semicon
i A. INSTRUCTION A.1 Terminology List Terminology Description A Accumulator X X - register Y Y - register PSW Program Status Word #imm 8-bit Immediate data dp Direct Page Offset Address !abs Absolute Address [ ] Indirect expression { } Register Indirect expression { }+ Register Indirect expression, after that, Register auto-increment .bit Bit Position A.bit Bit Position of Accumulator dp.bit Bit Position of Direct Page Memory M.bit Bit Position of Memory Data (000 H ~0FFF H ) rel Relative Addressing Data upage U-page (0FF00H ~0FFFF H ) Offset Address n Table CALL Number (0~15) + Addition x Upper Nibble Expression in Opcode y Upper Nibble Expression in Opcode − Subtraction × Multiplication / Division ( ) Contents Expression ∧ AND ∨ OR ⊕ Exclusive OR ~N O T ← Assignment / Transfer / Shift Left → Shift Right ↔ Exchange = Equal ≠ Not Equal Bit Position Bit Position
A.2 Instruction Map LOW HIGH 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 000 - SET1 dp.bit BBS A.bit,rel BBS dp.bit,re l ADC #imm ADC dp ADC dp+X ADC !abs ASL A ASL dp TCALL SETA1 .bit BIT dp POP A PUSH A BRK
001 CLRC SBC
#imm SBC dp SBC dp+X SBC !abs ROL A ROL dp TCALL CLRA1 .bit COM dp POP X PUSH X BRA rel
010 CLRG CMP
#imm CMP dp CMP dp+X CMP !abs LSR A LSR dp TCALL NOT1 M.bit TST dp POP Y PUSH Y PCALL Upage
011 DI OR
#imm OR dp OR dp+X OR !abs ROR A ROR dp TCALL OR1 OR1B CMPX dp POP PSW PUSH PSW RET
100 CLRV AND
#imm AND dp AND dp+X AND !abs INC A INC dp TCALL AND1 AND1B CMPY dp CBNE dp+X TXSP INC X
101 SETC EOR
#imm EOR dp EOR dp+X EOR !abs DEC A DEC dp TCALL EOR1 EOR1B DBNE dp XMA dp+X TSPX DEC X
110 SETG LDA
#imm LDA dp LDA dp+X LDA !abs TXA LDY dp TCALL LDC LDCB LDX dp LDX dp+Y XCN DAS 111 EI LDM dp,#im m STA dp STA dp+X STA !abs TAX STY dp TCALL STC M.bit STX dp STX dp+Y XAX STOP LOW HIGH 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
000 BPL
dp.bit BBC A.bit,rel BBC dp.bit,rel ADC {X} ADC !abs+Y ADC [dp+X] ADC [dp]+Y ASL !abs ASL dp+X TCALL JMP !abs BIT !abs ADDW dp LDX #imm JMP [!abs]
001 BVC
{X} SBC !abs+Y SBC [dp+X] SBC [dp]+Y ROL !abs ROL dp+X TCALL CALL !abs TEST !abs SUBW dp LDY #imm JMP [dp]
010 BCC
{X} CMP !abs+Y CMP [dp+X] CMP [dp]+Y LSR !abs LSR dp+X TCALL
5 MUL TCLR1
!abs CMPW dp CMPX #imm CALL [dp]
011 BNE
{X} OR !abs+Y OR [dp+X] OR [dp]+Y ROR !abs ROR dp+X TCALL DBNE Y CMPX !abs LDYA dp CMPY #imm RETI
100 BMI
{X} AND !abs+Y AND [dp+X] AND [dp]+Y INC !abs INC dp+X TCALL
9 DIV CMPY
!abs INCW dp INC Y TAY
101 BVS
{X} EOR !abs+Y EOR [dp+X] EOR [dp]+Y DEC !abs DEC dp+X TCALL XMA {X} XMA dp DECW dp DEC Y TYA
110 BCS
{X} LDA !abs+Y LDA [dp+X] LDA [dp]+Y LDY !abs LDY dp+X TCALL LDA {X}+ LDX !abs STYA dp XAY DAA
111 BEQ
{X} STA !abs+Y STA [dp+X] STA [dp]+Y STY !abs STY dp+X TCALL STA {X}+ STX !abs CBNE dp XYX NOP
A.3 Instruction Set Arithmetic / Logic Operation No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 1 ADC #imm 04 2 2 Add with carry.
2 ADC dp 05 2 3 A ← ( A ) + ( M ) + C
3 ADC dp + X 06 2 4
4 ADC !abs 07 3 4 NV--H-ZC 5 ADC !abs + Y 15 3 5
6 ADC [ dp + X ] 16 2 6
7 ADC [ dp ] + Y 17 2 6
8 ADC { X } 14 1 3
9 AND #imm 84 2 2 Logical AND
10 AND dp 85 2 3 A ← ( A ) ∧ ( M )
11 AND dp + X 86 2 4
12 AND !abs 87 3 4 N-----Z- 13 AND !abs + Y 95 3 5
14 AND [ dp + X ] 96 2 6
15 AND [ dp ] + Y 97 2 6
16 AND { X } 94 1 3
17 ASL A 08 1 2 Arithmetic shift left
18 ASL dp 09 2 4 N-----ZC
19 ASL dp + X 19 2 5
20 ASL !abs 18 3 5
21 CMP #imm 44 2 2
Compare accumulator contents with memory con- tents ( A ) - ( M )
22 CMP dp 45 2 3
23 CMP dp + X 46 2 4
24 CMP !abs 47 3 4 N-----ZC 25 CMP !abs + Y 55 3 5
26 CMP [ dp + X ] 56 2 6
27 CMP [ dp ] + Y 57 2 6
28 CMP { X } 54 1 3
29 CMPX #imm 5E 2 2 Compare X contents with memory contents
30 CMPX dp 6C 2 3 ( X ) - ( M ) N-----ZC
31 CMPX !abs 7C 3 4
32 CMPY #imm 7E 2 2 Compare Y contents with memory contents
33 CMPY dp 8C 2 3 ( Y ) - ( M ) N-----ZC
34 CMPY !abs 9C 3 4
35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z-
36 DAA DF 1 3 Decimal adjust for addition N-----ZC
37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC
38 DEC A A8 1 2 Decrement N-----ZC
← “0”← C
39 DEC dp A9 2 4 M ← ( M ) - 1 N-----Z-
40 DEC dp + X B9 2 5 N-----Z-
41 DEC !abs B8 3 5 N-----Z-
42 DEC X AF 1 2 N-----Z-
43 DEC Y BE 1 2 N-----Z-
44 DIV 9B 1 12 Divide : YA / X Q: A, R: Y NV--H-Z-
45 EOR #imm A4 2 2 Exclusive OR
46 EOR dp A5 2 3 A ← ( A ) ⊕ ( M )
47 EOR dp + X A6 2 4
48 EOR !abs A7 3 4 N-----Z- 49 EOR !abs + Y B5 3 5
50 EOR [ dp + X ] B6 2 6
51 EOR [ dp ] + Y B7 2 6
52 EOR { X } B4 1 3
53 INC A 88 1 2 Increment N-----ZC
55 INC dp + X 99 2 5 N-----Z-
56 INC !abs 98 3 5 N-----Z-
57 INC X 8F 1 2 N-----Z-
58 INC Y 9E 1 2 N-----Z-
59 LSR A 48 1 2 Logical shift right
60 LSR dp 49 2 4 N-----ZC
61 LSR dp + X 59 2 5
62 LSR !abs 58 3 5
63 MUL 5B 1 9 Multiply : YA ← Y × A N-----Z-
64 OR #imm 64 2 2 Logical OR
65 OR dp 65 2 3 A ← ( A ) ∨ ( M )
66 OR dp + X 66 2 4
67 OR !abs 67 3 4 N-----Z- 68 OR !abs + Y 75 3 5
69 OR [ dp + X ] 76 2 6
70 OR [ dp ] + Y 77 2 6
71 OR { X } 74 1 3
72 ROL A 28 1 2 Rotate left through Carry
73 ROL dp 29 2 4 N-----ZC
74 ROL dp + X 39 2 5
75 ROL !abs 38 3 5
76 ROR A 68 1 2 Rotate right through Carry
77 ROR dp 69 2 4 N-----ZC
78 ROR dp + X 79 2 5
79 ROR !abs 78 3 5
80 SBC #imm 24 2 2 Subtract with Carry
No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 76543210 “0” → → C 76543210C 76543210 C
v
81 SBC dp 25 2 3 A ← ( A ) - ( M ) - ~( C )
82 SBC dp + X 26 2 4
83 SBC !abs 27 3 4 NV--HZC 84 SBC !abs + Y 35 3 5
85 SBC [ dp + X ] 36 2 6
86 SBC [ dp ] + Y 37 2 6
87 SBC { X } 34 1 3
88 TST dp 4C 2 3 Test memory contents for negative or zero, ( dp ) -
H N-----Z-
89 XCN CE 1 5 Exchange nibbles within the accumulator
A7~A 4 ↔ A3~A 0 N-----Z- No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC
Register / Memory Operation No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC
1 LDA #imm C4 2 2 Load accumulator
2 LDA dp C5 2 3 A ← ( M )
4 LDA !abs C7 3 4 5 LDA !abs + Y D5 3 5 N-----Z-
6 LDA [ dp + X ] D6 2 6
7 LDA [ dp ] + Y D7 2 6
8L D A { X } D 4 1 3
9 LDA { X }+ DB 1 4 X- register auto-increment : A ← ( M ) , X ← X + 1
11 LDX #imm 1E 2 2 Load X-register
12 LDX dp CC 2 3 X ← ( M ) N-----Z-
13 LDX dp + Y CD 2 4
14 LDX !abs DC 3 4
15 LDY #imm 3E 2 2 Load Y-register
16 LDY dp C9 2 3 Y ← ( M ) N-----Z-
17 LDY dp + X D9 2 4
18 LDY !abs D8 3 4
19 STA dp E5 2 4 Store accumulator contents in memory
20 STA dp + X E6 2 5 ( M ) ← A
21 STA !abs E7 3 5
23 STA [ dp + X ] F6 2 7
24 STA [ dp ] + Y F7 2 7
25 STA { X } F4 1 4
26 STA { X }+ FB 1 4 X- register auto-increment : ( M ) ← A, X ← X + 1
27 STX dp EC 2 4 Store X-register contents in memory
29 STX !abs FC 3 5
30 STY dp E9 2 4 Store Y-register contents in memory
32 STY !abs F8 3 5
33 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z-
34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z-
35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← sp N-----Z-
36 TXA C8 1 2 Transfer X-register contents to accumulator: A ← X N-----Z-
37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer: sp ← X N-----Z-
38 TYA BF 1 2 Transfer Y-register contents to accumulator: A ← Y N-----Z-
39 XAX EE 1 4 Exchange X-register contents with accumulator :X ↔
40 XAY DE 1 4 Exchange Y-register contents with accumulator :Y ↔
41 XMA dp BC 2 5 Exchange memory contents with accumulator
42 XMA dp+X AD 2 6 ( M ) ↔ A N-----Z-
43 XMA {X} BB 1 5
No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC
1 ADDW dp 1D 2 5 16-Bits add without Carry
YA ← ( YA ) ( dp +1 ) ( dp ) NV--H-ZC 2C M P W d p 5 D 2 4 Compare YA contents with memory pair contents : (YA) − (dp+1)(dp) N-----ZC
3 DECW dp BD 2 6 Decrement memory pair
4 INCW dp 9D 2 6 Increment memory pair
5L D Y A d p 7 D 2 5 Load YA YA ← ( dp +1 ) ( dp ) N-----Z-
6 STYA dp DD 2 5 Store YA
7 SUBW dp 3D 2 5 16-Bits subtract without carry
YA ← ( YA ) - ( dp +1) ( dp) NV--H-ZC No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC
3 BIT dp 0C 2 4 Bit test A with memory : MM----Z-
4 BIT !abs 1C 3 5 Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M6 )
8 CLRG 40 1 2 Clear G-flag : G ← “0” --0-----
9 CLRV 80 1 2 Clear V-flag : V ← “0” -0--0---
11 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕
20 SETG C0 1 2 Set G-flag : G ← “1” --1-----
22 TCLR1 !abs 5C 3 6 Test and clear bits with A : 23 TSET1 !abs 3C 3 6 Test and set bits with A :
No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 2 BBC dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ← ( pc ) + rel 4 BBS dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ← ( pc ) + rel
5 BCC rel 50 2 2/4 Branch if carry bit clear
6B C S r e l D 0 2 2 / 4 Branch if carry bit set
7 BEQ rel D0 2 2/4 Branch if equal
8 BMI rel 90 2 2/4 Branch if minus
9B N E r e l 7 0 2 2 / 4 Branch if not equal
10 BPL rel 10 2 2/4 Branch if minus
11 BRA rel 2F 2 4 Branch always
12 BVC rel 30 2 2/4 Branch if overflow bit clear
13 BVS rel B0 2 2/4 Branch if overflow bit set
14 CALL !abs 3B 3 8 Subroutine call
15 CALL [dp] 5F 2 8
M( sp)← ( pcH ), sp← sp - 1, M(sp)← (pcL), sp ← sp - 1, if !abs, pc← abs ; if [dp], pcL← ( dp ), pcH ← ( dp+1 ) . 17 CBNE dp+X,rel 8D 3 6/8 if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel. 19 DBNE Y,rel 7B 2 4/6 if ( M ) ≠ 0 , then pc ← ( pc ) + rel. 20 JMP !abs 1B 3 3 Unconditional jump
22 JMP [dp] 3F 2 4
23 PCALL upage 4F 2 6
M(sp) ← ( pcH ), sp ← sp - 1, M(sp) ← ( pcL ), sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH ” .
24 TCALL n nA 1 8
Table call : (sp) ← ( pcH ), sp ← sp - 1, M(sp) ← ( pcL ),sp ← sp - 1, pcL ← (Table vector L), pcH ← (Table vector H)
x Control Operation & Etc. No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 1B R K 0 F 1 8 Software interrupt : B ← ”1”, M(sp) ← (pcH ), sp ← sp-1, M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH ) . ---1-0--
2 DI 60 1 3 Disable all interrupts : I ← “0” -----0--
3 EI E0 1 3 Enable all interrupt : I ← “1” -----1--
5 POP A 0D 1 4 sp ← sp + 1, A ← M( sp )
7 POP Y 4D 1 4 sp ← sp + 1, Y ← M( sp )
8 POP PSW 6D 1 4 sp ← sp + 1, PSW ← M( sp ) restored
9 PUSH A 0E 1 4 M( sp ) ← A , sp ← sp - 1
11 PUSH Y 4E 1 4 M( sp ) ← Y , sp ← sp - 1
12 PUSH PSW 6E 1 4 M( sp ) ← PSW , sp ← sp - 1
13 RET 6F 1 5
sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( sp )
14 RETI 7F 1 6
sp ← sp +1, PSW ← M( sp ), sp ← sp + 1, pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp ) restored
MASK ORDER & VERIFICATION SHEET GMS81604-HC 1. Customer Information Company Name 2. Device Information 3. Marking Specification 4. Delivery Schedule Customer Sample Date YYYY MM DD Risk Order YYYY MM DD Quantity LG Confirmation Application Order Date YYYY MM DD Tel: Fax: Name & Signature: Package 40DIP 42SDIP 5. ROM Code Verification Verification Date: YYYY MM DD Approval Date: YYYY MM DD Please confirm our verification data. I agree with your verification data and confirm you to make mask set. Check Sum: Tel: Fax: Name & Signature: Tel: Fax: Name & Signature: /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Set “FF” in this area 0000H 7000H 7FFFH ROM (4K) 6FFFH Mask Data Hitel Chollian Internet File Name: ( .OTP) (Please check mark into ) LG Semicon pcs pcs Check Sum: ( ) Customer should write inside thick line box. This box is written after “5.Verification”. LGS YYWW KOREA GMS81604 -HC Customer’s part number 44PLCC
MASK ORDER & VERIFICATION SHEET GMS81608-HC 1. Customer Information Company Name 2. Device Information 3. Marking Specification 4. Delivery Schedule Customer Sample Date YYYY MM DD Risk Order YYYY MM DD Quantity LG Confirmation Application Order Date YYYY MM DD Tel: Fax: Name & Signature: Package 40DIP 42SDIP 5. ROM Code Verification Verification Date: YYYY MM DD Approval Date: YYYY MM DD Please confirm our verification data. I agree with your verification data and confirm you to make mask set. Check Sum: Tel: Fax: Name & Signature: Tel: Fax: Name & Signature: /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 Set “FF” in this area 0000H 6000H 7FFFH ROM (8K) 5FFFH Mask Data Hitel Chollian Internet File Name: ( .OTP) (Please check mark into ) LG Semicon pcs pcs Check Sum: ( ) Customer should write inside thick line box. This box is written after “5.Verification”. LGS YYWW KOREA GMS81608 -HC Customer’s part number 44PLCC