GMS81508A HYNIX | Alldatasheet
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USE R ’S M AN U AL Re vision History Re v 2.2 (Dec. 1998) Add the package dim ension for 64LQFP on page 3-1, 4-1. Re v 2.1 (Nov. 1998) O perating Tem perature, -10~75°C is extended to -20~85°C. Add the unused port guidance on page 55. C orrect errata for opcode of “EO R [dp+X], EOR [dp]+Y , EO R {X}” in “Instruction Set”. A dd the OTP device program m ing guidance, recomm end using “Intelligent Mode”. Ad d the chapter for OTP program m ing manual as an appendix. Re v 2.0 (Sep. 1997)
- CONTENTS -
- OVERVIEW GMS81508/16 is a single chip microcomputer designed CMOS technology. The use of CMOS process enables extremely low power consumption. This device using the G8MC Core includes several peripheral functions such as Timer, A/D Converter, Programmable Buzzer Driver, Serial I/O, Pulse Width Modulation Function, etc. ROM,RAM,I/O are placed on the same memory map in addition to simple instruction set. 1.1. FEATURES GMS81508 GMS81516 ROM(Bytes) 8K 16K RAM(Bytes) 448 bytes(includes stack area) Execution Time 0.5us (@Xin=8MHz) Basic Interval Timer 8bit 5 1ch. Watch Dog Timer 6bit 5 1ch. Timer 8bit5 4ch.(or 16bit 5 2ch.) ADC 8bit 5 8ch. PWM 8bit 5 2ch. Serial I/O 8bit 5 1ch. External Interrupt 4ch. Buzzer Driver Programmable Buzzer Driving Port I/O Port 4 - Input only 52 - Input/Output Power Save Mode STOP Mode Operating Voltage 4.5 ~ 5.5V ( @ Xin=8MHz ) Operating Frequency 1 ~ 8MHz Package 64SDIP, 64QFP OTP GMS81516T Application Home Appliances, LED Applications
1.2. BLOCK DIA G R A M A /D C ONVERTER PWM B UZZER W .D.T S.I.C TIMER IN TE R R U PT C L O CK GEN. SYSTEM C ONTROL G 8MC C O R E R A M (448 BY T E) R O M (8/16K B Y T E) PRESCALER B .I.T PO RT PO RT PO RT PO RT PO RT PO RT PO RT A V ref A V ss R60~R67 (A N 0~AN 7) R57/PW M 1 R55/B U Z R56/PW M 0 R54/W D TO R53/Srdy R52/Sclk R51/Sout R50/Sin R47/T3 O R46/T1 O R45/EC2 R44/EC0 R43/IN T3 R42/IN T2 R41/IN T1 R40/IN T0 MP R ESET X in X out V dd V ss R60 R63 R64 R67 R50 R57 R40 R47 R30 R37 R20 R27 R10 R17 R00 R07
1.3. PIN ASSIGNMENT G M S R30/ RD R31/ Wt R32/ R/W R33/ C R34/ SYNC R35/ BRK R36/ BRQ R37/ HALT R00/ D0 R01/ D1 R02/ D2 R03/ D3 R04/ D4 R05/ D5 R06/ D6 R07/ D7 R10/ A0 R11/ A1 R12/ A2 R13/ A3 R14/ A4 R15/ A5 R16/ A6 R17/ A7 R20/ A8 R21/ A9 R22/ A10 R23/ A11 R24/ A12 R25/ A13 R26/ A14 R27/ A15 Vdd MP AVss AVref R67/AN7 R66/AN6 R65/AN5 R64/AN4 R63/AN3 R62/AN2 R61/AN1 R60/AN0 R57/PWM1 R56/PWM0 R55/BUZ R54/WDTO R53/Srdy R52/Sclk R51/Sout R50/Sin R47/T3O R46/T1O R45/EC2 R44/EC0 R43/INT3 R42/INT2 R41/INT1 R40/INT0 RESET Xin Xout Vss MP MODE
64 SDIP
31 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 4951 50 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R37/HALT R00/D0 R01/D1 R02/D2 R03/D3 R04/D4 R05/D5 R06/D6 R07/D7 R10/A0 R11/A1 R12/A2 R13/A3 R14/A4 R15/A5 R16/A6 R17/A7 R20/A8 R21/A9 R22/A10 R23/A11 R24/A12 R25/A13 R26/A14 R17/A15 Vss Xout Xin RESET R40/INT0 R41/INT1 R42/INT2 R36 BRQ R35 BAK R34 SYNC R33 C R32 R/W R31 Wt R30 Rd Vdd MP AVss AVref R67/AN7 R66/AN6
64 QFP
1.4 PACKAGE DIMENSION
UNIT: INCH 2.280 2.260 0.205 max. 0.022 0.016 0.050 0.030
0.070 BSC
0.140 0.120 m in. 0.015 0.680 0.660
0.750 BSC
0-15° 0.012 0.008 64SDIP 20.10 19.90 24.15 23.65 18.15 17.65 14.10 13.90 3.18 max. 0.50 0.35
1.00 BSC
SEE D ETA IL "A" 1.03 0.73 0-7° 0.36 0.10 0.23 0.13 1.95 REF DETAIL "A" UNIT: MM 64Q FP
1.60 max. SEE DETAIL "A" 0.75 0.45 0-7° 0.15 0.05 1.00 REF DETAIL "A" UNIT: MM10.00 BSC
12.00 BSC
10.00 BSC
0.38 0.22
0.50 BSC
1.45 1.35 64LQ FP 4-1
1.5. PIN DESCRIPTION Classification No. Symbol I/O Descriptions Power 1 Vdd I Power Supply Input Pin(4.5~5.5V)
32 Vss I Ground(0V)
I Controls Microprocess Mode of the Chip At "H" input : Single Chip Mode At "L" input : Microprocess Mode System Control or
29 RESET I In the state of "L" level, system enter to the reset
state. Clock
30 Xin
I This chip has an internal clock generating circuit. To control generating frequency, an external ceramic or a quartz crystal oscillator is connected between Xin and Xout pins.
31 Xout I If external clock is used, the clock source should be
connected to the Xin pin and the Xout pin should be left open.
24 EC0 I Event Counter Source Clock Input Pin
22 T1O O Timer Counter Overflow Output Pin
21 T3O O
28 INT0 I
Ext. Interrupt 27 INT1 I External Interrupt Request Signal Input Pin
26 INT2 I
25 INT3 I
4 AVref I Reference Voltage Input Pin for A/D Converter
3 AVss I Ground Level Input Pin for A/D Converter
12 AN0 I
11 AN1 I
9 AN3 I Analog Voltage Input Pin for A/D Converter
17 Srdy I/O Receive Enable Output Pin
Serial I/O 18 Sclk I/O Serial Clock Output Pin
19 Sout O Serial Data Output Pin
20 Sin I Serial Data Input Pin
P.W.M 14 PWM0 O PWM Pulse Output Pin
13 PWM1 O
Buzzer 15 BUZ O Buzzer Driving Frequency Output Pin W.D.T 16 WDTO O Watch dog Timer Overflow Output Pin
C lassification N o. Sym bol I/O Description R00 R07 I/O R0 Port ( Can be determ ined I/O by R0DD ) In MP m ode, This port functions as 8-bit data bus for the CPU. (D0~D7) R10 R17 I/O R1 Port ( Can be determ ined I/O by R1DD ) In MP m ode, This functions as 8-bit lower address output pins. (A0~A7) R20 R27 I/O R2 Port ( Can be determ ined I/O by R2DD ) In MP m ode, This functions as 8-bit higher address output pins.(A8~A15) I/O Port 57 R30 R37 I/O R3 Port ( Can be determ ined I/O by R3DD ) In MP m ode, This port functions as 8-bit control bus for the CPU. R40 R47 I/O R4 Port ( Can be determ ined I/O by R4DD ) R50 R57 I/O R5 Port ( Can be determ ined I/O by R5DD ) R60 R63 I R6 Port Input O nly R64 R65 I/O R 6 Port ( Can be determ ined I/O by R6DD )
- FUNCTIONS 2.1. REGISTERS 6 registers are built-in the CPU of G8MC. Accumulator(A), Index register X, Y, Stack Pointer (SP) and Program Status Word(PSW) consists of 8-bit registers. Program Counter(PC) consists of 16- bit registers. The contents of these registers are undefined after RESET. Program C ounter 1 5 8 PCH 7 0 PCL A - Register 7 0 A 1 5 8 Y ( YA 16bit Accumulator ) 7 0 A X - Register 7 0 X Y - Register 7 0 Y Program Status Word 7 0 PSW Stack Pointer 7 0 SP C arry Flag Z CH IG BN V Zero Flag Interrupt Enable Flag H alf Carry Flag B reak Flag G ( Direct Page ) Flag O verflow Flag N egative Flag
2.1.1. A - Reg ister The accum ulator is the 8-bit general purpose register. This is used register for data operation, data transfer, tem porary saves and conditional judgm ent. Accum ulator can be used as a 16-bit register with Y register and has a lower 8-bit data. In case of m ultiplication instruction(MUL), it works as a m ultiplier. After execution of MUL instruction, Accum ulator has lower 8-bit data of the results(16-bit). In case of division instruction(DIV), it has the lower 8-bit of dividend (16-bit) 2.1.2. X- Reg ister In index addressing m ode, this register is executed as a 8-bit index register within direct page(RAM area). also, In indirect addressing m ode, it is destination address register. This register can be used as a increm ent, decrem ent, com parison, and data transfer function. In case of division instruction(DIV), it works as a divisor. 2.1.3. Y- Reg ister In index addressing m ode, this register is executed as a index register. In case of 16-bit operation instruction, this register has upper 8-bit of YA (16-bit accum ulator). In case of m ultiplication instruction(MUL), this register is executed as a m ultiplicand register. After m ultiplication operation, it has the upper 8-bit of the result. In case of division instruction, it is executed as a dividend(upper 8-bit). After division operation, it has quotient. This register can be used as a loop counter of conditional branch com m and. (e.g. DBNE Y, rel) 2.1.4. Stack Pointer The stack pointer(SP) is an 8-bit register used during subroutine calling and interrupts. W hen branching out from an on-going routine to subroutine or interrupt routine, it is necessary to rem em ber the return address. norm ally, internal RAM is used for storing the return address and this area is called stack area. SP is pointer to show where the stack data are stored within the stack area. The stack area is located in 1-Page of internal RAM . SP m ust be initialized by S/W because the contents of SP is undefined after RESET. ex) LDX #0FEH ;0FEH -> X register TXSP ;X -> SP caution) You can't use !01FFH as stack. If you use this area, mal-function w ould be occurred.
The bellows shows data store and restore sequence to/from stack area. /G01 Interrupt /G02 RETI /G03 Subroutine CALL /G04 RET /G05 PUSH A ( X, Y, PSW ) /G06 POP A ( X, Y, PSW ) M (sp) /G01 ( PCH ) sp /G01 sp /G02 1 M (sp) /G01 ( PCL ) sp /G01 sp /G02 1 M (sp) /G01 A M (sp) /G01 ( PCH ) sp /G01 sp /G02 1 M (sp) /G01 ( PCL ) sp /G01 sp /G02 1 M (sp) /G01 ( PSW ) sp /G01 sp /G02 1 sp /G01 sp /G02 1 sp /G01 sp /G03 1 ( PCL ) /G01 M (sp) sp /G01 sp /G03 1 ( PCH) /G01 M (sp) sp /G01 sp /G03 1 A /G01 M (sp) ( PSW ) /G01 M (sp) sp /G01 sp /G03 1 ( PCL ) /G01 M (sp) sp /G01 sp /G03 1 ( PCH) /G01 M (sp) sp /G01 sp /G03 1 1 5 8 Stack Address ( 0100H /G01 01FFH ) 01H 7 0 SP Hardware fixed
2.1.5. Program Counter The program counter(PC) is a 16-bit counter which consists of 8-bit register PCH and PCL. The addressing space is 64K bytes. This counter indicates the address of the next instruction to be executed. In reset state, the program counter (PC) has reset routine address in address FFFFH and FFFEH . 2.1.6. Program Status W ord PSW is an 8-bit register which is com posed of flags to maintain the condition of the processor imm ediately after an operation. After RES ET, The contents of PSW is set to "00H ". PSW /G01 Carry Flag ( C ) After an operation, it is set to "1" when there is a carry from bit7 of ALU or not a borrow. SE TC ,CLR C instructions allow direct access for setting and resetting. it can be used as a 1-bit accum ulator. It is a branch condition flag of BCS, BCC instructions. /G02 Zero Flag ( Z ) After an operation including 16-bit operation, it is set to "1" when the result is “0”. It is a branch condition flag of BEQ , BNE. /G01 Interrupt Enable Flag ( I ) This flag is used to enable/disable all interrupts except interrupt caused by BRK instruction. W hen this flag is "1", it mean s interrupt enable condition. W hen an interrupt is accept, this flag is autom atically set to "0" thereby preventing other interrupts. also it is set to "1" by RETI instruction. This flag is set and cleared by EI, DI instructions. /G03 Ha lf Carry Flag ( H ) After an operation, it is set when there is a carry from bit3 of ALU or is not a borrow from bit4 of ALU. It can not be set by any instruction. it is cleared by CLRV instruction like V flag. N V G B H I Z C
/G04 Break Flag ( B ) This flag is set by BRK (S/W interrupt) instruction to distinguish BRK and TCALL instruction having the same vector address. /G05 Direct Page Flag ( G ) This flag assign direct page (0-page, 1-page) for direct addressing mode. When G-flag is "0", the direct addressing space is in 0-page(0000H~00FFH). When G-flag is "1", the direct addressing space is in 1-page(0100H~01FFH). It is set and cleared by SETG, CLRG instruction /G06 Overflow Flag ( V ) This flag functions when one word is added or subtracted in binary with the sign. When results exceeds +127 or -128, this flag is set. When BIT instruction is executed, The bit6 of memory is input into V-flag. This flag is cleared by CLRV instruction, but set instruction is not exist. It is a branch condition flag of BVS, BVC. /G07 Negative Flag ( N ) N-flag is set when the result of a data transfer or operation is negative (bit7 is “1”). it means the bit-7 of memory is sign bit. thereby data is valid in the range of -128 ~ +127. When BIT instruction is executed, The bit7 of memory is input into N-flag. Set or clear instruction is not exist. It is a branch condition flag of BPL, BMI instruction.
2.2. M EM ORY SP A CE All RAM ,RO M ,I/O , Peripheral Register are placed in the sam e m em ory area. Therefore, sam e instructions enable both data transfer and operation without the need to distinguish m em ory and I/O. The program counter of G MS81508 /16 consists of 16-bit and mem ory addressing space is 64K byte. 2.2.1. RAM area RAM( includes stack area) is 448 Bytes ( 0000H /G01 01FFH ). The internal RAM is used for data storage, subroutine calling or stack area when interrupts occur. W hen RAM is used as the stack area, the depth of the subroutine "nesting" and the interrupt levels should be kept in m ind in order to avoid destruction of the RAM contents. 2.2.2. Peripheral Register area Address 00C0H /G01 00FFH are assigned for peripheral register. 2.2.3. Program ROM area /G02 PCALL subroutines m ust be located in PC ALL area ( FF00H /G01 FFBFH ). /G03 TC ALL vector area ( FFC0 H /G01 FFDFH ) has the vector address corresponding to TCALL instruction. /G04 Interrupt Vector area ( FFE0H /G01 FFFFH ) has the vector address of interrupts, inclusive RESET.
(192 byte) Peripheral Registers RAM(STACK) (256 byte) Program ROM PCALL Area TCALL Vector Area Interrupt Vector Area !0000H !00C0H !0100H !0200H !C000H !E000H !FF00H !FFC0H !FFE0H Not Used Area 0-Page 1-Page Direct Page(dp) U-Page G M S G M S Absolute Address /G01 VECTOR TABLE TCALL INTERRUPT Address Vector Address Vector FFC0H - FFC1H TCALL 15 FFE0H - FFE1H not used FFC2H - FFC3H TCALL 14 FFE2H - FFE3H not used FFC4H - FFC5H TCALL 13 FFE4H - FFE5H Serial I/O FFC6H - FFC7H TCALL 12 FFE6H - FFE7H Basic Interval Timer FFC8H - FFC9H TCALL 11 FFE8H - FFE9H Watch Dog Timer FFCAH - FFCBH TCALL 10 FFEAH - FFEBH A/D Converter FFCCH - FFCDH TCALL 9 FFECH - FFEDH Timer 3 FFCEH - FFCFH TCALL 8 FFEEH - FFEFH Timer 2 FFD0H - FFD1H TCALL 7 FFF0H - FFF1H Timer 1 FFD2H - FFD3H TCALL 6 FFF2H - FFF3H Timer 0 FFD4H - FFD5H TCALL 5 FFF4H - FFF5H Ext. Int. 3 FFD6H - FFD7H TCALL 4 FFF6H - FFF7H Ext. Int. 2 FFD8H - FFD9H TCALL 3 FFF8H - FFF9H Ext. Int. 1 FFDAH - FFDBH TCALL 2 FFFAH - FFFBH Ext. Int. 0 FFDCH - FFDDH TCALL 1 FFFCH - FFFDH not used FFDEH - FFDFH TCALL 0 FFFEH - FFFFH RESET
2.2.4. Peripheral Register List Address Re gister Name SYM BO L R /W RESET VALUE 7 6 5 43 2 10 00C 0H R 0 PORT DA TA REG ISTER R0 R /W U ndefined 00C 1H R 0 PORT I/O D IREC TION REG ISTER R 0DD W 0 0 0 00 0 00 00C 2H R 1 PORT DA TA REG ISTER R0 R /W U ndefined 00C 3H R 1 PORT I/O D IREC TION REG ISTER R 0DD W 0 0 0 00 0 00 00C 4H R 2 PORT DA TA REG ISTER R0 R /W U ndefined 00C 5H R 2 PORT I/O D IREC TION REG ISTER R 0DD W 0 0 0 00 0 00 00C 6H R 3 PORT DA TA REG ISTER R0 R /W U ndefined 00C 7H R 3 PORT I/O D IREC TION REG ISTER R 0DD W 0 0 0 00 0 00 00C 8H R 4 PORT DA TA REG ISTER R4 R /W U ndefined 00C 9H R 4 PORT I/O D IREC TION REG ISTER R 4DD W 0 0 0 00 0 00 00C A H R 5 PORT DA TA REG ISTER R5 R /W U ndefined 00C B H R 5 PORT I/O D IREC TION REG ISTER R 5DD W 0 0 0 00000 00C C H R 6 PORT DA TA REG ISTER R6 R /W U ndefined 00C D H R 6 PORT I/O D IREC TION REG ISTER R 6DD W 0 0 0 0 - - - - 00D 0H PORT R 4 M O D E REG ISTER PM R 4 W 0 0 0 00 0 00 00D 1H PORT R 5 M O D E REG ISTER PM R 5 W - - 0 0 - - - - 00D 2H TEST M O DE RE G ISTER TM R W - - - - - 0 0 0 00D 3H BASIC INTERVAL RE G ISTER B ITR R U ndefined C LOCK CON TRO L R EG ISTER CKC TLR W - - 0 10 1 11 00E 0H W ATCH DOG TIM ER W D TR W - 0 1 11 1 11 00E 2H TIM ER M ODE RE G ISTER 0 TM 0 R /W 0 0 0 00 0 00 00E 3H TIM ER M ODE RE G ISTER 2 TM 2 R /W 0 0 0 00 0 00 00E 4H TIM ER 0 DATA REG ISTER TD R 0 R /W U ndefined 00E 5H TIM ER 1 DATA REG ISTER TD R 1 R /W U ndefined 00E 6H TIM ER 2 DATA REG ISTER TD R 2 R /W U ndefined 00E 7H TIM ER 3 DATA REG ISTER TD R 3 R /W U ndefined 00E 8H A/D CONVER TER M ODE REG ISTER A D CM R /W - - 0 00 0 01 00E 9H A/D CONVER TER D ATA REG ISTER A D R R U ndefined 00E A H SERIA L I/O M O D E REG ISTER SIO M R /W - 0 0 00 0 01
Address Re gister Name SYM BO L R /W RESET VALUE 7 6 5 43 2 10 00E B H SERIA L I/O RE G ISTER SIO R R/W Undefined 00EC H BUZZER DRIVER RE G ISTER B U R W U ndefined 00F0H PW M 0 DATA REG ISTER PW M R0 W U ndefined 00F1H PW M 1 DATA REG ISTER PW M R1 W U ndefined 00F2H PW M CON TRO L REG ISTER PW M CR W 00 00F3H IN TERRUPT M ODE R EG ISTER IM O D R /W - - 0 00 0 00 00F4H IN TERRUPT ENAB LE REG ISTER LO W IE N L R /W 000 0---- 00F5H IN TERRUPT REQUEST FLAG REG ISTER LO W IR Q L R /W 000 0---- 00F6H IN TERRUPT ENAB LE REG ISTER H IGH IE N H R /W 0 0 0 00 0 00 00F7H IN TERRUPT REQUEST FLAG REG ISTER H IGH IR Q H R /W 0 0 0 00 0 00 00F8H EXT. IN TERRUPT EDGE S E LEC TION RE G ISTER IE D S W 0 0 0 00 0 00 /G07 -: Not Used /G07 W rite O nly Register can not be accessed by bit m anipulation instruction.
2.3. C LOCK GENER A TION C IRC U IT The clock generation circuit of G MS81508 /16 consists of oscillation circuit, prescaler, Basic Interval Tim er. The source clock of peripherals is provided by 11-bit prescaler. O SC C ircuit C lock Pulse G enerator Prescaler C om parator W D TR0 1 2 3 4 5 6 7 Internal System C lock IFBIT IFWDT B TCL EN PC K W D TCL To R ESET C ircuit Internal Data Bus CKC T LR 2.3.1. Oscillation Circuit The clock signal incom ing from crystal oscillator or ceramic resonator via Xin and Xout or from external clock via Xin is supplied to Clock Pulse G enerator and Prescaler. The internal system clock for CPU is m ade by Clock Pulse G enerator, and several peripheral clock is divided by prescaler. The clock generation circuit of crystal oscillator or ceramic resonator is shown in below. /G01 C rystal O scillator or Ceram ic Re sonator /G02 External clock /G05 In STOP Mode, The oscillation is stopped, Xin pin goes to "L" level status, and Xout pin goes to "H " level state. Xin C in GND Cout Xout Xin External C lock O penXout
2.3.2. Prescaler The prescaler consists of 11-bit binary counter, and input clock is supplied by oscillation circuit. The frequency divided by prescaler is used as a source clock for peripherals. /G02 Frequency-Divided Outputs of Prescaler fex (/G01 ) PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 Period 250 /G02 500 /G02 1 /G03 2 /G03 4 /G03 8 /G03 16 /G03 32 /G03 64 /G03 128 /G03 256 /G03 The peripheral clock supplied from prescaler can be stopped by ENPCK. (However, PS11 cannot be stopped by ENPCK) WWWWWW 76543210 Internal Data Bus Peripherals ENPCK fex B.I.T. PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS0 Enable Peripheral Clock 0 : stop 1 : supply /G04 /G04 ENPCKWDTON BTCL BTS2 BTS1 BTS0 CKCTLR <00D3 H >
2.4. BASIC IN TER VA L TIM ER /G06 . G enerates reference tim e interval interrupt request as a timer. ( Note; The writing at sam e address overwrites the CKCTLR .) /G06 . The overflow of B.I.T be used the source clock of W atch Dog Tim er. 2.4.1. Control of Basic Interval Tim er The Basic Interval Tim er is free running tim er. W hen the counting value is changed "0FFH" to "00H" , The interrupt request flag is generated. The counter can be cleared by setting BTC L (Bit 3 of CKCTLR ) and the BTC L is auto-cleared after 1 m achine cycle. The initial state (after Reset) of BTCL is “0”. The input clock of Basic Interval Tim er is selected by BTS2~BTS0 (Bit2~0 of CKCTLR) am ong the prescaler outputs (PS4~PS11 ). The Basic Interval Tim er Register (BITR) can be read. The CKC TLR and the BITR have a sam e address (00D3H). So, If you write to this address, the CKC TLR would be controlled. If you read this address, the counting value of BITR would be read. /G01 C LO CK CO NTRO L REG ISTER PS4 /G04 /G04 W D TO N EN PC K BTCL BTS2 BTS1 BTS0CKC TLR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 BITRPS5 PS6 PS7 PS8 PS9 PS 10 PS 11 MUX IFBIT Internal Data Bus Internal Data Bus S am e address w hen read, it can be read as counter value. W hen w rite, it can be w rite as control register. B.I.T. input clock selection B.I.T. C LEAR ( W hen w riting ) 0 : B.I.T. Free-run 1 : B.I.T. C lear ( auto cleared after 1 m achine cycle ) /G04 /G04 5 4 EN PC KW D TO N B TC L BTS2 BTS1 BTS0 W W W W W W <00D3H > CKC TLR
/G01 BASIC INTERVAL TIMER DATA REGISTER 2.5. WATCH DOG TIMER The Watch Dog Timer is a means of recovery from a system problem. In this Device, the Watch Dog Timer consists of 6-bit binary counter, 6-bit comparator and watch dog timer register(WDTR). The source clock of WDT is overflow of Basic Interval Timer. The interrupt request of WDT is generated when the counting value of WDT equal to the contents of WDTR( bit0~5). This can be used as s/w interrupt or MICOM RESET signal(Watch Dog Function). 2.5.1. Control of Watch Dog Timer It can be used as 6-bit timer or WDT according to bit5(WDTON) of Clock Control Register (CKCTLR). The counter can be cleared by setting WDTCL ( Bit 6 of WDTR) and the WDTCL is auto-cleared after 1 machine cycle. The initial state (after Reset) of WDTCL is “0”. /G01 CLOCK CONTROL REGISTER /G01 WATCH DOG TIMER REGISTER WDT ON 0 : 6-bit Timer 1 : Watch Dog Timer /G04 /G04 5 4 ENPCKWDTON BTCL BTS2 BTS1 BTS0 W W W W W W <00D3 H > CKCTLR Watch Dog Timer Clear 0 : free run 1 : W.D.T counter clear /G04 WDTCL WDTR5 4 3 2 1 0 W W W W W W W W <00E0H > WDTR Determines the interval of W.D.T Interrupt WDTR3WDTR4 WDTR0WDTR1WDTR2 B.I.T data 5 4 RR R R R R R R <00D3 H > BITR
The interval of W DT interrupt is decided by the interrupt interval of Basic Interval Tim er and the contents of W DTR. The interval of W DT = The contents of W DTR /G01 The interval of B .I.T. C aution) Do not use the contents of W DTR = "0" 0 0 0 PS4 ( 2 /G08 ) 512 /G08 32,256 /G08 0 0 1 PS5 ( 4 /G08 ) 1,024 /G08 64,512 /G08 0 1 0 PS6 ( 8 /G08 ) 2,048 /G08 129,024 /G08 0 1 1 PS7 ( 16 /G08 ) 4,096 /G08 258,048 /G08 1 0 0 PS8 ( 32 /G08 ) 8,192 /G08 516,096 /G08 1 0 1 PS9 ( 64 /G08 ) 16,384 /G08 1,032,192 /G08 1 1 0 PS10 ( 128 /G08 ) 32,768 /G08 2,064,384 /G08 1 1 1 PS11 ( 256 /G08 ) 65,536 /G08 4,128,768 /G08 2.5.2. The output of W D T signal The overflow of W DT can be output through R54/W DT O port by setting bit4 of PMR5(W DTS) to "1". /G01 PO RT R5 M O DE R EG ISTER <00D1H > PMR5 BUZS W D TS WW R 54/W D T O Selection 0 : R 54 ( Input / O utput ) 1 : W D TO ( O utput )
2.6. TIMER The GMS81508/16 has four multi-functional 8-bit binary timers(Timer0~Timer3). Timer0 (or Timer2) is can be used as a 16-bit timer/event counter with Timer1(or Timer3). The Timer0-1 and Timer2-3 have same functions and structures. So, We will explains about Timer0 and Timer1 only. /G01 Operation Mode of Timer Timer0,Timer2 Timer1,Timer3 -. 8-bit Interval Timer -. 8-bit Event Counter -. 8-bit input capture -. 8-bit Interval Timer -. 8-bit rectangular pulse output -. 16-bit Interval Timer -. 16-bit Event Counter -. 8-bit rectangular pulse output ck PS6 PS4 PS2 T0CN T1ST INT0 CAP0 T0ST PS6 PS4 PS2 EC0 TDR0 Internal Data Bus 16bit Mode16bit Mode MUX TM0 1 03 25 47 6 TDR1 IFT0 INTR0 T1O IFT1 Comparator 0 Comparator 1 Data Reg. 1Data Reg. 0 T 0 T 1 8 8 Clea ck Clea MUX MUX F / FEDGE MUX MUX
/G01 TIME R M O DE R EG ISTER 0,2(TM0,TM2) /G01 TIME R D ATA REG ISTER (TDR0 ~ TDR3) T1 Input C lock Selection 00 : C onnection to T0 (16bit Mode ) 01 : PS 2 ( 500 /G02 ) 10 : PS 4 ( 2 /G03 ) 11 : PS 6 ( 8 /G03 ) T3 Input C lock Selection 00 : C onnection to T2 (16bit Mode ) 01 : PS 2 ( 500 /G02 ) 10 : PS 4 ( 2 /G03 ) 11 : PS 6 ( 8 /G03 ) T0 Input C lock Selection 00 : EC 0 01 : PS 2 ( 500 /G02 ) 10 : PS 4 ( 2 /G03 ) 11 : PS 6 ( 8 /G03 ) T2 Input C lock Selection 00 : EC 2 01 : PS 2 ( 500 /G02 ) 10 : PS 4 ( 2 /G03 ) 11 : PS 6 ( 8 /G03 ) <00E2H > <00E3H > TM 0 TM 2 CAP0 CAP2 T1ST T3ST T1SL1 T3SL1 T1SL0 T3SL0 T0ST T2ST T0C N T2C N T0SL1 T2SL1 T0SL0 T2SL0 R /W R /W R /W R /W R /W R /W R /W R /W R /W R /W R /W R /W R /W R /W R /W R /W T0 Start/Stop control 0 : C ount Stop 1 : C ounting start after clearing T0 T2 Start/Stop control 0 : C ount Stop 1 : C ounting start after clearing T2 T0 Start/Stop control 0 : COUNT S top 1 : COUNT S tart T2 Start/Stop control 0 : COUNT S top 1 : COUNT S tart Input C apture S election 0 : Tim er/C ounter 1 : Input C apture Input C apture S election 0 : Tim er/C ounter 1 : Input C apture T1 Start/Stop control 0 : C out Stop 1 : C ounting start after clearing T1 T3 Start/Stop control 0 : C out Stop 1 : C ounting start after clearing T3 TDR0~3 7 6 5 4 3 2 1 0 R /W R /W R /W R /W R /W R /W R /W R /W ( W RITE) M odulo D ata W rite ( READ ) C ount V alue R ead <00E4H~ 00E7H >
2.6.1. Control of Timer T0 ( T1 ) consists of 8-bit Binary Up-Counter. When the counting value of Timer0 , Timer1 and Timer0-1(16bit) become equal to the contents of Timer Data Register(TDR0,TDR1,TDR0-1) value, the counter is cleared to "00H" and restarts count-up operation. At this time, Interrupt request (IFT0 or IFT1) is generated. Any of the PS2, PS4, PS6 or external clock can be selected as the clock source of T0 by bit1(T0SLI) and bit0(T0SL0) of TM0. Any of the PS2, PS4, PS6 or overflow of T0 can be selected as the clock source of T1 by bit5(T1SL1) and bit4(T1SL0) of TM0. When the overflow of T0 is selected as input clock of T1, Timer0-1 operates as 16 -bit timer. In this case, Timer0-1 only is controlled by T0ST,T0CN and the interrupt vector is Timer0 vector. The operation of T0, T1 is controlled by bit3(T0ST), bit2(T0CN) and bit6(T1ST) of TM0. T0CN controls count stop/start without clearing counter. T0ST and T1ST control count stop/start after timer clear. In order to enable count-up of timer , T0CN, T0ST and T1ST should become “1”. In order to start count-up after clearing of counter, T0ST or T1ST should be set to "1" after set to "0" temporarily. Interval Period InterruptInterruptInterrupt MATCHMATCHMATCH ClearClearClear 00H IFT0 T0 VALUE TDR0 VALUE CountCount StopCountStop “0” “1” Start InterruptInterrupt MATCHMATCH ClearClearClear 00H IFT0 T0 VALUE TDR0 VALUE T0ST COUNTER T0CN
By read Tim er Data Register(TDR0 ~3),The counting value of tim er can be read at any tim e. 2.6.2. Interval Tim er The interrupt cycle is determined by the source clock of tim er and the contents of TDR. Interrupt cycle = source clock /G01 the contents of TD R In order to write data to TDR, you have to stop tim er. otherwise, TD R value is invalid. /G02 Maxim um Interrupt Cycle according to source clock @ fex=8MHz 8-bit TIMER Mode 16-bit TIM ER Mode source clock m ax. count source clock m ax. count PS2 ( 0.5 /G08 ) 128 /G08 PS2 ( 0.5 /G08 ) 32,768 /G08 T0,T2 PS4 ( 2 /G08 ) 512 /G08 PS4 ( 2 /G08 ) 131,072 /G08 PS6 ( 8 /G08 ) 2,048 /G08 PS6 ( 8 /G08 ) 524,288 /G08 PS2 ( 0.5 /G08 ) 128 /G08 T1,T3 PS4 ( 2 /G08 ) 512 /G08 PS6 ( 8 /G08 ) 2,048 /G08 2.6.3. Event Counter The event counter operates in the sam e way as the interval tim er except it counts the external event input from R44 /EC0 and R45/EC1 port. it only counts at the falling edge of event input clock. In order to input of external event clock, the relevant Port Mode Register(bit4,bit5 of PMR4) is set to "1". TD R value should be initialized to “FFH ” because tim er is cleared when it equals to TDR value, but if you want to use interrupt, TD R value should be written to "1H~FFH ". 2.6.4. Pulse Output A pulse width 50% cycle duty is output to the R46/T1 O or R47/T3 O port and reverse the output when tim er interrupt is generated. This creates a pulse period which is two tim es that of the tim er interrupt cycle. The output pulse period is determ ined by the source clock of timer and the contents of TDR. output period = source clock(/G07 ) /G02 the contents of TD R /G02 2 In order to output of pulse, the bit6,bit7 of PMR 4 is set to "1". 2.6.5. Input Cap ture This function m easures the period or width of pulse input from external INT. (R40/IN T0, R42/INT2) port. The period of pulse is m easured by selecting rising edge or falling edge of the interrupt edge select register(IEDS) and the width of pulse is m easured by selecting both edge of IEDS. The external interrupt is generated at the valid edge according to IEDS. At this tim e, The counting value of tim er is loaded into TDR and counter is cleared and restarts count-up.
“H”Width “L”Width Timer Operation the counting value of timer is latched timer is cleared to 00H timer restart count-up /G01 PORT R4 MODE REGISTER <00D0 H > PMR4 T3S T1S EC2S EC0S INT3S INT2S INT1S INT0S W W WWW W W W R44/ EC0 Selection 0 : R44 ( Input / Output ) 1 : EC0 ( Input ) R45/ EC2 Selection 0 : R45 ( Input / Output ) 1 : EC2 ( Input ) R47 / T3 Selection 0 : R47 ( Input / Output ) 1 : T3 ( Output ) R46 / T1 Selection 0 : R46 ( Input / Output ) 1 : T1 ( Output ) R40 / INT0 Selection 0 : R40 ( Input / Output ) 1 : INT0 ( Input ) R42 / INT2 Selection 0 : R42 ( Input / Output ) 1 : INT2 ( Input )
2.7. EXTERN A L IN TERRUPT An interrupt request is generated when a level-change from "H" to "L" or "L" to "H " of IN T0,IN T1,IN T2,IN T3 pin is detected. The edge of external interrupt is selected by interrupt edge selection register(IEDS ) and ports(R40,R41 ,R42 ,R43) corresponding to IN T0,IN T1,INT4,INT3 are determined as a input port for external interrupt by bit0~3 of port4 mode register(PMR4). /G01 EXT. INTERRU PT EDG E SELECTIO N REG ISTER <00D0H > PMR4 T3S T1S EC 2S EC 0S IN T3S IN T2S IN T1S IN T0S W W WWW W W W R 40 / IN T0 S election 0 : R 40 ( Input / O utput ) 1 : IN T0 ( Input ) R 43 / IN T3 S election 0 : R 43 ( Input / O utput ) 1 : IN T3 ( Input ) R 41 / IN T1 S election 0 : R 41 ( Input / O utput ) 1 : IN T1 ( Input ) R 42 / IN T1 S election 0 : R 42 ( Input / O utput ) 1 : IN T2 ( Input ) <00F8H > IED S IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L WWWW W W WW INT0 Edge S election 00 : - 01 : Falling 10 : R ising 11 : Falling & R ising INT1 Edge S election 00 : - 01 : Falling 10 : R ising 11 : Falling & R ising INT3 Edge S election 00 : - 01 : Falling 10 : R ising 11 : Falling & R ising INT2 Edge S election 00 : - 01 : Falling 10 : R ising 11 : Falling & R ising
2.8. A/D CONVERTER A/D Converter has an 8-bit resolution, and input is possible up to 8 channel. A/D Converter consists of Analog Input Multiplexer, A/D convert Mode Register, Resistance Ladder, Sample and Holder, Successive Approximation Circuit and A/D Conversion Data Register. Ladder Resistor Decoder MUX S/H Control Register Successive Approximation Circuit A/D Conversion Data Register(8bit) ADEN ADS2 ADS1 ADS0 ADST ADSF-- AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 COMPARATOR AVref AVss Internal Data Bus IFA 2.8.1. Control of A/D Converter The analog input is selected by bit2~4 of A/D Converter Mode Register(ADCM). This bits chooses among AN0~AN7. The other analog pins which are not used not A/D conversion be used as normal port. The A/D Conversion is started by setting A/D Conversion Start bit (ADST) to "1"(only for ADEN=1). After A/D Conversion is started, ADST is cleared by hardware. During A/D Conversion, when ADST is set to "1", A/D Conversion starts again from the beginning. The analog input voltage and the reference voltage are compared and the result is stored in the A/D Converter Data Register(ADR) and ADSF(bit0 of ADCM) is set to "1". The A/D interrupt request is generated at the completion of A/D conversion. The result of the conversion is obtained by reading out the A/D register(ADR).
/G01 A/D CO NVE RTER MO DE REGISTER(ADCM) /G01 A/D CO NVE RTER DATA REG ISTER(ADR) <00E8H > A D C M /G04 /G04 5 4 ADS2ADEN ADS1 ADS0 ADST ADSF - - R /W R /W R /W R /W R /W R /W A/D C onversion Status bit 0 : during A /D C onversion 1 : com pleted A/D C onversionA/D C onverter input select 000 : channel 0(AN 0) 001 : channel 1(AN 1) 010 : channel 2(AN 2) 011 : channel 3(AN 3) 100 : channel 4(AN 4) 101 : channel 5(AN 5) 110 : channel 6(AN 6) 111 : channel 7(AN 7) A/D C onverter Enable bit 0 :D isable A/D C onverter 1 : Enable A/D C onverter A/D C onversion Start bit 0 : invalid 1 : Start A/D C onversion (after 1 cycle, be cleared to "0") <00E8H > A D C M /G04 /G04 5 4 ADS2ADEN ADS1 ADS0 ADST ADSF - - R /W R /W R /W R /W R /W R A/D C onversion Status bit 0 : during A /D C onversion 1 : com pleted A/D C onversionA/D C onverter input select 000 : channel 0(AN 0) 001 : channel 1(AN 1) 010 : channel 2(AN 2) 011 : channel 3(AN 3) 100 : channel 4(AN 4) 101 : channel 5(AN 5) 110 : channel 6(AN 6) 111 : channel 7(AN 7) A/D C onverter Enable bit 0 :D isable A/D C onverter 1 : Enable A/D C onverter A/D C onversion Start bit 0 : invalid 1 : Start A/D C onversion (after 1 cycle, be cleared to "0") <00E9H > A D R 5 4 R R R R R R R R A/D C onversion D ata
2.9. SERIAL I/O The serial I/O is 8-bit clock synchronous type and consists of serial I/O register, serial I/O mode register, clock selection circuit octal counter and control circuit. SIOR 1 03 25 47 6 Sclk Octal CounterControl Circuit Internal Data BUS Internal Data BUS SM0 SM1 Srdy Srdy0 Srdy In MUXPS5 PS4 PS3 IFSIO Exclk R Q S Sin Sout 667 0 SIOMSM0 SOSFSIOSTSCK0SCK1/G05 Srdy SM1
/G01 Serial I/O M ode Register This register controls serial I/O function. According to SCK1 and SCK 0, the internal clock or external clock can be selected. /G01 Serial I/O Data Register The Serial I/O Data Register (SIOR ) is a 8-bit shift register. First LSB is send or is received. <00EB H > SIOR R /W R /W R /W R /W R /W R /W R /W R /W At transmittion S ending D ata at S ending Mode R eceiving D ata at R eceiving Mode <00EA H > SIO M /G01 Srdy SM 1 SM 0 SCK1 SCK0 SIO ST SIO SF /G01 R /W R /W R /W R /W R /W R /W R S erial Transm ission C lock S election 00 : PS 3 ( 1 /G03 ) 01 : PS 4 ( 2 /G03 ) 10 : PS 5 ( 4 /G03 ) 11 : E xternal C lock S erial O peration M ode 00 : N orm al P ort(R 52,R 51,R 50) 01 : S ending M ode(Sclk,S out,R 50) 10 : R eceiving M ode(Sclk,R 51,Sin) 11 : S ending & R eceiving M d (S lk S Si) S erial Transm ission Start 0 : Invalid 1 : Start(After one SCK, becom es”0”) S erial Transm ission Status Flag 0 : during transmission 1 : finished R 53/Srdy Selection 0 : R 53 1 : Srdy
2.9.1. Data Transmission/Receiving Timing The serial transmission is started by setting SIOST(bit1 SIOM) to ”1”. After one cycle of SCK, SIOST is cleared automatically to “0”. The serial output data from 8-bit shift register is output at falling edge of Sclk. and input data is latched at rising edge of Sclk. When transmission clock is counted 8 times, serial I/O counter is cleared as “0”. Transmission clock is halted in “H ” state and serial I/O interrupt (IFSIO) occurred. Timing Diagram of Serial I/O 2.9.2. The Serial I/O operation by Srdy pin /G01 transmission clock = external clock The Srdy pin becomes "L" by SIOST = "1". This signal tells to the external system that this device is ready for serial transmission. The external system detects the "L" signal and starts transmission. The Srdy pin becomes "H" at the first rising edge of transmission clock. /G01 transmission clock = internal clock The I/O of Srdy pin is input mode. When the external system is ready to for serial transmission, the "L" level is inputted at this pin. At this time this device starts serial transmission. SIOST Srdy(Output) SIOST Srdy(Input) D7D6D5D1 D4 D3D2D0 D7D6D5D1 D4 D3D2D0 Input Clock Sclk Latch Output IFSIO Sin Sout SIOST
2.9.3. The m ethod of Serial I/O /G02 Select transm ission/receiving m ode <Notice> W hen external clock is used, the frequency should be less than 1MHz and recomm ended duty is 50%. /G03 In case of sending m ode, write data to be send to SIO R. /G04 Set SIOST to “1” to start serial transm ission. <Notice > If both transm ission m ode is selected and transm ission is perform ed sim ultaneously it would be m ade error. /G09 The SIO interrupt is generated at the com pletion of SIO and SIO SF is set to “1”. In SIO interrupt service routine, correct transm ission should be tested. /G0A In case of receiving m ode, the received data is acquired by reading the SIO R. 2.9.4. The M ethod to Test Correct Transm ission w ith S/W Serial I/O Interrupt Service Routine SIO SF SE=0 Write SIO M N orm al Operation O verrun Error SR A bnormal Serial Method to Test Transm ission. Note) SE: Interrupt Enable Regist Low IENL ( Bit3 ) SR : Interrupt Request Flag Regist Low IRQ L ( Bit3 )
2.10. PWM PW M (Pulse W idth Modu lation) has a 8-bit resolution and the PS8 ,PS9,PS10,PS11 of the prescaler can be selected as input clock PW M. PW M R 0 C om parator C ounter PW M R 1 C om parator C ounter P1C K 1 P1C K 0 P0C K 1 P0C K 0 EN 1 EN 0 PO L1 PO L0 S Q R S Q R MUX MUX Polarity Polarity PS8 PS9 PS10 PS11 PS8 PS9 PS10 PS11 Internal D ata B us Internal D ata B us O verflow O verflow PW M 0 PW M 1 PW M C R 2.10.1. Controls of PW M The input clock is selected by PW M Control Register (PW M CR), and the width of pulse is determined by the PW M Register (PW MR ). The pulse period according to input clock are as follows. Input clock PW M Period PS8 (32/G06 ) 8,192/G06 PS9 (64/G06 ) 16,384/G06 PS10 (128/G06 ) 32,768/G06 PS11 (256/G06 ) 65,536/G06 Bit2 (EN0) and bit3 (EN1) of PW M control Register (PW M CR ) determ ine the operation channel of PW M . W hen EN0=0 and EN1=0, PW M does not executed. The EN0 and EN1 are Enable bit of PW M channel 0 and channel 1 respectively. W hen EN0=1, PW M channel0 executes. W hen EN1=1, PW M channel1 executes. PO LO and PO L1 are a polarity control bit of channel0 and channel1. W hen they are 0, LO W active. W hen 1, HIG H active. PW M CR becom es "00h" in reset state.
/G01 PWM C O NTROL R EGISTER /G01 PWM D ATA REG ISTER (a) Active Low period (b) Active High period pulse widthpulse width C ounter Load Value + 1 D uty C ycle = /G01 100[% ] 256 <00F2H > PWMCR PICK1 PICK0 P0CK P0CK EN1 EN0 PO L1 PO L0 W W W W W W W W PW M Enable Flag 00 : D isable 01 : PW M0 10 : PW M1 11 : PW M 0,PW M 1 PW M 1 C lock Selection 00 : PS 8 01 : PS 9 10 : PS 10 11 : PS 11 PW M 0 C lock Selection 00 : PS 8 01 : PS 9 10 : PS 10 11 : PS 11 PW M0 O utput P olarity 0 : Active Low 1 : Active H igh PW M1 O utput P olarity 0 : Active Low 1 : Active H igh <00F0H > <00F1H > PWMR0 PWMR1 W W W W W W W W PW M D ATA
2.11. BUZZER DRIVER Buzzer driver consist of 6 bit binary counter, Buzzer Register(BUR), and selector of clock. The wide range frequency(500Hz~250KHz) can be generated using programmable counter. PORT R55 is assigned for output port of Buzzer Driver by setting bit5 of PMR5($00D1H) to "1". BUCK1 BUCK0 BU5 BU4 BU3 BU2 BU1 BU0 MUX 0 1 2 3 4 5 T Q PS4 PS5 PS6 PS7 Buzzer Output6bit Counter WtBUR Internal Data Bus /G01 PORT R5 MODE REGISTER /G01 BUZZER DATA REGISTER <00D1 H > PMR5 BUZ WDTO W W R55 / BUZ Selection 0 : R55 ( Input / Output ) 1 : BUZ ( Output ) <00EC H > BUR BUCK1 BUCK0 BU5 BU4 BU3 BU2 BU1 BU0 W W WWWWWW Buzzer Count DataBuzzer Source Clock Selection 00 : PS4 01 : PS5 10 : PS6 11 : P S 7
2.11.1. Buzzer Driver O peration The bit0-5 of Buzzer Register (BUR) determ ines output frequency for buzzer driving. The frequency is calculated as shown bellows. N = BU R data freq. = 1/(source clock 5 N 5 2) The bit6 and bit7 of Buzzer register (BUR) selects the source clock of the buzzer counter am ong PS4 (2us), PS5 (4us), PS6 (8us) and PS7 (16us). The buzzer counter is cleared by W t signal of BUR and starts the counting. also, It is cleared by counter overflow, and continues count-up to output the rectangular wave of duty 50%. * Caution: don't use BUR register as 00H. (counter reset state) /G02 The output frequency of buzzer according to Buzzer Register bit5 - bit0 (fex = 8 MHz) RE G . RE G . O UTPUT FRE Q UENC Y[KH z] RE G . RE G . O UTPUT FRE Q UENC Y[KH z] LO AD DEC LO AD HEX PS4 (2us) PS5 (4us) PS6 (8us) PS7 (16us) LO AD DEC LO AD HEX PS4 (2us) PS5 (4us) PS6 (8us) PS7 (16us) 250 125 83.333 62.5 41.666 35.714 31.25 27.778 22.728 20.834 19.23 17.858 16.666 15.626 14.706 13.888 13.158 12.5 11.904 11.364 10.87 10.416 9.616 9.26 8.928 8.62 8.334 8.064 7.812 125 62.5 41.666 31.25 20.834 17.858 15.626 13.888 12.5 11.364 10.416 9.616 8.928 8.334 7.812 7.352 6.944 6.579 6.25 5.952 5.682 5.434 5.208 4.808 4.630 4.464 4.310 4.166 4.032 3.906 62.5 31.25 20.834 15.626 12.5 10.416 8.928 7.812 6.944 6.25 5.682 5.682 4.808 4.464 4.166 3.906 3.676 3.472 3.288 3.124 2.976 2.840 2.718 2.604 2.5 2.404 2.314 2.232 2.156 2.084 2.016 1.954 31.25 15.626 10.416 7.812 6.25 5.208 4.464 3.906 3.472 3.126 2.84 2.604 2.404 2.232 2.084 1.9541 1.838 1.736 1.644 1.562 1.488 1.420 1.358 1.302 1.250 1.202 1.158 1.116 1.078 1.042 1.008 0.976 7.576 7.352 7.142 6.944 6.756 6.578 6.41 6.3 6.098 5.952 5.814 5.682 5.556 5.434 5.32 5.208 5.102 4.902 4.808 4.716 4.63 4.546 4.464 4.386 4.31 4.238 4.166 4.098 4.032 3.968 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 2.551 2.5 2.451 2.404 2.358 2.315 2.273 2.232 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.894 1.838 1.786 1.736 1.689 1.645 1.602 1.563 1.524 1.488 1.453 1.421 1.389 1.359 1.33 1.302 1.276 1.25 1.225 1.202 1.179 1.157 1.136 1.116 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496
2.12. INTERRUPTS The interrupts are usually used when the processing routine has the higher priority than on-going program and a routine muse be executed at specific interval. 2.12.1. Interrupt Circuit Configuration and Kinds GMS81508/16 Interrupt circuits consists of Interrupt Enable Register (IENH,IENL), Interrupt Request Register (IRQH,IRQL), priority circuit and selecting circuit. The configuration of Interrupt circuit is shown in below. IRQL IRQH RESET IFT3 D ata BUS IMOD I-FLAG BRK to CPU Standby Mode Release PRIORITY CONTROL T2R T3R IENH 10 32 54 76 10 32 54 /G07/G07 T0R T1R INT2R INT3R INT0R INT1R BITR WDTR SR AR IENL /G07 /G07- /G075 47 6 Data BUS IFT2 IFT1 IFT0 INT3 INT2 INT1 INT0 IFA IFWDT IFBIT IFS INTERRUPT VECTOR ADDRESS GEN.
/G01 Interrupt Source The interrupts sources are external interrupt source(IN T0, INT1,INT2,INT3), peripheral function After reset input(RESET), the program is executed from the address in reset vector table like general interrupts. Type Ma sk Priority Interrupt Request Source Vector H Vector L Non Ma skable
1 R ST R eset Pin FFFFH FFFE H
2 IN T0R External Interrupt 0 FFFBH FFFA H
3 IN T1R External Interrupt 1 FFF9H FFF8H
4 IN T2R External Interrupt 2 FFF7H FFF6H
H /W 5 IN T3R External Interrupt 3 FFF5H FFF4H Interrupt 6 T0R Timer 0 FFF3H FFF2H
7 T1R Tim er 1 FFF1H FFF0H
8 T2R Tim er 2 FFEFH FFEEH
9 T3R Tim er 3 FFED H FFFC H
10 AR A/D C onverter FFEBH FFEAH
11 W DTR W atch Do g Tim er FFE9H FFE8 H
12 BITR Basic Interval Tim er FFE7 H FFE6 H
13 SR Serial I/O FFE5H FFE4 H
/G09 BRK Break Instruction FFDFH FFD EH 2.12.2. Interrupt Control The interrupts is controlled by the interrupt m aster enable flag I-Flag(3'rd bit of PSW ), interrupt enable register(IENH,IENL), interrupt request register(IR Q H,IR Q L) except RES ET and S/W interrupt. /G01 Interrupt Enable Register ( IENH, IEN L) This register is com posed of interrupt enable flags of each interrupt source, this flags determ ines whether an interrupt will be accepted or not. when enable flag is "0", an interrupt corresponding interrupt source is prohibited.
/G01 Interrupt Request Flag Register ( IRQH, IRQL) Whenever interrupt request is generated, the interrupt request flag is set. The request flag maintains '1" until interrupt is accepted. The accepted interrupt request flag is automatically cleared by interrupt process cycle. Interrupt Request Flag Register ( IRQH, IRQL) is Read/ Write Register. So, it is possible to be checked and changed by program. 2.12.3. Interrupt Priority When two or more interrupts requests are generated at the same sampling point, the interrupt having the higher priority is accepted. The interrupt priority is determined by H/W. however, multiple priority processing through software is possible by using interrupt control flags(IENH, IENL, I-flag) and interrupt mode register(IMOD). Interrupt Masking Flag 0 : Interrupt Disable 1 : Interrupt Enable <00F6H > IENH INT0E INT1E INT2E INT3E T0E T1E T2E T3E R/W R/W R/W R/W R/W R/W R/W R/W <00F4H > IENL AE WDTE BITE SE R/W R/W R/W R/W - - - - Interrupt Request Flag 0 : Disable 1 : Enable <00F7H > IRQH INT0R INT1R INT2R INT3R T0R T1R T2R T3R R/W R/W R/W R/W R/W R/W R/W R/W <00F5H > IRQL AR WDTR BITR SR R/W R/W R/W R/W - - - -
2.12.4. Interrupt Sequence W hen interrupt is accepted, the on-going process is stopped and the interrupt service routine is executed. After the interrupt service routine is com pleted it is necessary to restore everything to the state before the interrupt occurred. As soon as an interrupt is accepted, the contents of the program counter and the program status word are saved in the stack area. At the sam e tim e, the contents of the vector address corresponding to the accepted interrupt, which is in the interrupt vector table, enters into the program counter and interrupt service routine is executed. In the interrupt service routine, the corresponding interrupt request flag is cleared and interrupt m aster enable flag(I-flag) becom es "0", thereby another interrupts are not accepted before I-flag is set to "1" by program . In order to execute the interrupt service routine, it is necessary to write the jum p address(the first address of the interrupt service routine) in vector table corresponding to each interrupt. /G02 Interrupt Accept Timing /G01 The valid timing after executing Interrupt control Flag /G0B I-Flag is valid, after EI, D I executed /G0C IEN H , IENL register is valid after next instruction
1 C ycles 0/G08 12 C ycles 8 C ycles
Interrupt O verhead : 9/G02 21 C ycles Int.request S am pling Interrupt Process S tep Interrupt routine A comm and before Interrupt
/G02 Interrupt Process Step Timing 2.12.5. Software Interrupt The interrupt is the lowest priority order software interrupt by BRK instruction. B-flag is set. Interrupt vector of BRK instruction is shared with the vector of TCALL 0. Each processing step is determined by B-Flag as a below. /G02 Execution of BRK/ TCALL0 BRK or TCALL0 1 TCALL 0 RoutineBRK Interrupt Routine RET B-Flag ? RETI V.L System Clock Instruction Fetch sp-2 new pcV.HV.Lsp-1pc spAddress Bus PSW OpcodeADHADLPCL V.L, V.H is Vector Address, ADL, ADH is start Address of Interrupt Service Routine as Vector Contents Interrupt Process Step Interrupt Service Routine not Used PCHData Bus Internal Read Internal Write
2.12.6. M ultiple Interrupt W hen an interrupt is accepted, and program flow goes to the interrupt service routine. The interrupt m aster enable flag(I-flag) is autom atically cleared and other interrupts are inhibited. W hen interrupt service is com pleted by RETI instruction, I-flag is set autom atically. If other interrupts are generated during interrupt service, The interrupt having higher priority is accepted when the previous interrupt service routine is com pleted. In order to m ultiple interrupts, I-flag mu st be cleared by EI instruction within the interrupt routine. Then, The higher priority interrupt is accepted am ong the interrupts that interrupt request flag is "1". /G01 Interrupt Mode Register ( IM O D ) if IM 1,IM 0 is selected as a "01", the interrupt selected by IP0~IP3 can be accepted and other interrupts are not accepted. Using this register, we can change the interrupt priority order by s/w. Interrupt Mode D efinition 00 : M ode 0 (Priority by H /W ) 01 : M ode 1(D efinition by IP 3/G05 IP0) 1- : Inhibit Interrupt Interrupt D efinition S election 0001 : IN T0 0010 : IN T1 0011 : IN T2 0100 : IN T3 0101 : TIM ER 0 0110 : TIM ER 1 0111 : TIM ER 2 1000 : TIM ER 3 1001 : AD C 1010 : W D T 1011 : BIT 1100 : SIO <00F3H > IM OD /G04 /G04 IM 1 IM 0 IP3 IP2 IP1 IP0 /G01 /G01 R /W R /W R /W R /W R /W R /W
When multiple interrupt is accepted, it is possible to change Interrupt Accept Mode. In case of multiple interrupt at hardware priority accept mode(Mode0) In case of multiple interrupts nest H/W priority accept mode (Mode0) and S/W selection accept mode(Mode1) EI EIEI Main Program ( Mode 0 ) 1’st INT. Routine ( Mode 0 ) 2’nd INT. Routine ( Mode 0 ) 3’rd INT. Routine InterruptInterruptInterrupt EI EI EI Main Program ( Mode 0 ) 1’st INT. Routine ( Mode 0 ) 2’nd INT. Routine ( Mode 1 ) 3’rd INT. Routine Interrupt InterruptInterrupt Reload IMOD Stacking IMOD Change Mode
2.13. STA NDB Y FUNC TION To save the consum ing power of device, GMS81508/16 has STO P Mode. In this m ode, the execution of program is stopped. Stop Mode entered by STOP instruction. /G02 At STOP Mode, Device O peration State. Peripheral Function STO P M ode O scillator /G0A CPU C lock /G0A RAM, Re gister Re tain I/O Port R etain Prescaler /G0A Basic Interval Tim er /G0A Serial I/O O peration( External Clock Selection) W DT, Tim er, A/DC ,PW M , Buzzer Driver /G0A Address Bus, Data Bus Re tain Rd, W t, R /W Re tain HALT, BR Q , BAK Active C "L" level SYNC "H" level halt STO P IFBIT CPU C lock Re lease Signal from Interrupt C ircuit RESET C lock Pulse GEN. MUX Prescaler RQ SQ O verflow Detection Basic Interval Tim er RQ SQ OS C . C ircuit
2.13.1. STOP Mode STOP Mode can be entered by STOP instruction during program execution. In STOP mode, oscillator is stopped to make all clocks stop, which leads to the mode requiring much less power consumption. All register and RAM data are preserved. Caution) NOP instruction have to be written more than 2 to next lines of STOP instruction. 2.13.2. STOP Mode Release The release of STOP mode is done by reset input or interrupt. When there is a release signal of STOP mode, the instruction execution is started after stabilization oscillation time set by program. After releasing STOP mode, instruction execution is different by I-Flag(bit 2 of PSW). If I-Flag = “1” entered Interrupt Service Routine, If I-Flag = “0” execute program from next instruction of STOP instruction. /G02 STOP Mode Release Release Factor Release Method RESET By RESET pin=Low level, and Device is initialized. INT0,INT1 INT2,INT3 In the state of enable flag=1 corresponding to each interrupt at the edge. Serial I/O When Serial I/O is executed by external clock, STOP mode is released. /G02 Release Timing of STOP Mode System Clock Release Signal by interrupt STOP Stabilization Oscillation TimeSTOP Mode determined by program. RESET Stabilization oscillation time + 8 Cycles /G06
W hen release the STOP Mode, to secure oscillation stabilization tim e, we use Basic Interval Tim er. So, before execution ST O P instruction, we m ust select suitable B.I.T. clock for oscillation stabilization tim e. Otherwise, It is possible to release by only RES ET input. Because STO P m ode is released by interrupt, even if both of interrupt enable bit(IE) and interrupt request flag is "1", STO P m ode can not be executed. /G02 STOP M ode Releasing Flow N O P N O P Interrupt Service Routine I-Flag ? STOP Mode R elease Interrupt Request IE ? STOP Mode STOP C om m and
2.14. RESET FUNCTION To reset the device, maintain the RESET="L" at least 8 machine cycle after power supplying and oscillation stabilization. RESET terminal is organized as schmitt input. If initial value is undefined, it is needed initialize by a S/W. /G02 RESET Operation Timing Opcode System Clock Instruction Fetch ? StartFFFFFFFE?? ?Address Bus FE? ADHADL? FFFE H , is vector address and ADL, ADH is start address of main program as vector contents RESET Process Step Main Program ? ?Data Bus Internal Read RESET
- I/O POR TS There are 7-ports(R0~R6) in this device. This ports are double-functional ports and the function can be selected by program . The direction of ports is determ ined by Port Direction Register.(1=output, 0=input) The data that is written on the program m ed output pin is stored in the port data register and is transferred to the output pin. W hen data is input to the programmed p in. data is read not from output pin but from port data register. therefore, previously output data can be read correctly regardless or the logical level of the pin due to output loading. Because the programm ed input pin is floating, the value of the pin can be read correctly. W hen data is written to the program m ed input pin, it is written only to the port data register and the pin rem ains floating. 3.1. R0 PORT R0 Port is com posed of 8-bit program m able I/O pin. Re gister Name Sym bol R /W Address Initial Value R0 I/O Direction Register R0DD W 00C1H 0000 0000 R0 PO RT Data Register R0 R/W 00C0H N ot initialized /G01 R0 PO RT I/O DIRE CTIO N REGISTER /G01 R0 PO RT DATA REG ISTER D eterm ines I/O of R 0 port 0 : Input 1 : O utput <00C1H > R0DD R0DD7 R0DD6 R0DD5 R0DD4 R0DD3 R0DD2 R0DD1 R0DD0 W W W W W W W W P ort R 0 output data <00C0H > R 07 R 06 R 05 R 04 R 03 R 02 R 01 R 00 R /W R /W R /W R /W R /W R /W R /W R /W
/G01 Pin Function According to Operation Modes PIN Single Chip Mode Microprocessor Mode R00/D0 I/O I/O R01/D1 I/O I/O R02/D2 I/O Programmable I/O Port I/O Data I/O Port from/to External Memory R03/D3 I/O I/O for CPU. R04/D4 I/O I/O R05/D5 I/O I/O R06/D6 I/O I/O R07/D7 I/O I/O 3.2. R1 PORT R1 Port is composed of 8-bit programmable I/O pin. Register Name Symbol R/W Address Initial Value R0 I/O Direction Register R1DD W 00C3 H 0000 0000 R0 PORT Data Register R1 R/W 00C2 H Not initialized /G01 R1 PORT I/O DIRECTION REGISTER /G01 R1 PORT DATA REGISTER /G01 Pin Function According to Operation Modes Determines I/O of R1 port 0 : Input 1 : Output <00C3 H > R1DD R1DD7 R1DD6 R1DD5 R1DD4 R1DD3 R1DD2 R1DD1 R1DD0 W W W W W W W W Port R1 output data <00C2 H > R17 R16 R15 R14 R13 R12 R10 R/W R/W R/W R/W R/W R/W R/W R/W
PIN Single Ch ip Mode M icroprocessor Mode R 10/A0 I/O O R 11/A1 I/O O R 12/A2 I/O Programm able I/O P ort O low 8bit address of E xternal M em ory R 13/A3 I/O O for CP U. R 14/A4 I/O O R 15/A5 I/O O R 16/A6 I/O O R 17/A7 I/O O 3.3. R2 PORT R2 Port is com posed of 8-bit program m able I/O pin. Re gister Name Sym bol R /W Address Initial Value R2 I/O Direction Register R2DD W 00C5H 0000 0000 R2 PO RT Data Register R2 R/W 00C4H N ot initialized /G01 R2 PO RT I/O DIRE CTIO N REGISTER /G01 R2 PO RT DATA REG ISTER D eterm ines I/O of R 2 port 0 : Input 1 : O utput <00C5H > R2DD R2DD7 R2DD6 R2DD5 R2DD4 R2DD3 R2DD2 R2DD1 R2DD0 W W W W W W W W P ort R 2 output data <00C4H > R 27 R 26 R 25 R 24 R 23 R 22 R 21 R 20 R /W R /W R /W R /W R /W R /W R /W R /W
/G01 Pin Function According to Operation Modes PIN Single Chip Mode Microprocessor Mode R20/A8 I/O O R21/A9 I/O O R22/A10 I/O Programmable I/O Port O upper 8bit address of External Memory R23/A11 I/O O for CPU. R24/A12 I/O O R25/A13 I/O O R26/A14 I/O O R27/A15 I/O O 3.4. R3 PORT R3 Port is composed of 8-bit programmable I/O pin. Register Name Symbol R/W Address Initial Value R3 I/O Direction Register R3DD W 00C7 H 0000 0000 R3 PORT Data Register R3 R/W 00C6 H Not initialized /G01 R3 PORT I/O DIRECTION REGISTER /G01 R3 PORT DATA REGISTER Determines I/O of R3 port 0 : Input 1 : Output <00C7 H > R3DD R3DD7 R3DD6 R3DD5 R3DD4 R3DD3 R3DD2 R3DD1 R3DD0 W W W W W W W W Port R3 output data <00C6 H > R37 R36 R35 R34 R33 R32 R31 R30 R/W R/W R/W R/W R/W R/W R/W R/W
/G01 Pin Function According to Operation M odes PIN Single Ch ip Mode M icroprocessor Mode R 30 I/O O R d : external m em ory read strobe R 31 I/O O W t : external m em ory w rite strobe R 32 I/O Program m able I/O P ort O R /W :R ead/W rite cycle output pin of C PU R 33 I/O O C : tim ing signal output pin R34 I/O O SYNC : op code fetch output pin of CPU R 35 I/O O BR K : bus acknow ledge output pin of CPU R 36 I/O I BR Q : bus request input pin of C U P R 37 I/O I H ALT : C PU halt input pin 3.5. R4 PORT R4 Port is com posed of 8bit program m able I/O port and this port are double functional pin. Re gister Name Sym bol R /W Address Initial Value R4 I/O Direction Register R4DD W 00C9H 0000 0000 R4 Port Data Register R4 R/W 00C8H N ot initialized Port R4 Mode Register PMR4 W 00D0H 0000 0000 Interrupt Edge Select Register IEDS R/W 00F8H 0000 0000 /G01 R4 PO RT I/O DIRE CTIO N REGISTER /G01 R4 PO RT DATA REG ISTER P ort R 4 output data <00C8H > R 47 R 46 R 45 R 44 R 43 R 42 R 41 R 40 R /W R /W R /W R /W R /W R /W R /W R /W D eterm ines I/O of R 4 port 0 : Input 1 : O utput <00C9H > R4DD R4DD7 R4DD6 R4DD5 R4DD4 R4DD3 R4DD2 R4DD1 R4DD0 W W W W W W W W
/G01 PORT R4 MODE REGISTER /G01 INTERRUPT EDGE SELECTION REGISTER 3.6. R5 PORT R5 Port is composed of 8-bit programmable I/O port. R54,R55 is double functional pin. Register Name Symbol R/W Address Initial Value R5 I/O Direction Register R5DD W 00CB H 0000 0000 R5 Port Data Register R5 R/W 00CA H Not initialized R5 Port Mode Register PMR5 W 00D1 H --00 ---- <00D0 H > PMR4 T3S T1S EC2S EC0S INT3S INT2S INT1S INT0S WW W W W W R45/ EC2 Selection 0 : R45 ( Input / Output ) 1 : EC2 ( Input ) R44/ EC0 Selection 0 : R44 ( Input / Output ) 1 : EC0 ( Input ) R47 / T3 Selection 0 : R47 ( Input / Output ) 1 : T3 ( Output ) R46 / T1 Selection 0 : R46 ( Input / Output ) 1 : T1 ( Output ) R40 / INT0 Selection 0 : R40 ( Input / Output ) 1 : INT0 ( Input ) R41 / INT1 Selection 0 : R41 ( Input / Output ) 1 : INT1 ( Input ) R42 / INT2 Selection 0 : R42 ( Input / Output ) 1 : INT2 ( Input ) R43 / INT3 Selection 0 : R43 ( Input / Output ) 1 : INT3 ( Input ) W W <00F8H > IEDS IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L WW W WW W INT0 Edge Selection 01 : Falling 10 : Rising 11 : Falling & Rising INT1 Edge Selection 01 : Falling 10 : Rising 11 : Falling & Rising INT2 Edge Selection 01 : Falling 10 : Rising 11 : Falling & Rising INT3 Edge Selection 01 : Falling 10 : Rising 11 : Falling & Rising WW
/G01 R5 PO RT I/O DIRE CTIO N REGISTER /G01 R5 PO RT DATA REG ISTER /G01 PO RT R5 M O DE R EG ISTER 3.7. R6 PORT R6 Port consists of 4-bit Programmable I/O ports and 4-bit input only ports and this port can be used as a analog input port for A/D conversion by program . Re gister Name Sym bol R /W Address Initial Value R6 I/O Direction Register R6DD W 00CD H 0000 ---- R6 Port Data Register R6 R/W 00CC H N ot initialized A/D Converter Mode Register ADCM W 00E8H --00 0001 P ort R 5 O utput D ata <00CA H > R 57 R 56 R 55 R 54 R 53 R 52 R 51 R 50 R /WR /W R /W R /W R /WR /W R /W R /W D eterm ines I/O of R 5 port 0 : Input 1 : O utput <00CB H > R5DD R5DD7 R5DD6 R5DD5 R5DD4 R5DD3 R5DD2 R5DD1 R5DD0 W W WW W W W <00D1H > PMR5 7 BUZ W D TO N WW R 55 / BU Z Selection 0 : R 55 ( Input / O utput ) 1 : BUZ ( O utput ) R 54 / W D TO N Selection 0 : R 54 ( Input / O utput ) 1 : W D TO N ( O utput ) W
/G01 R6 PORT I/O DIRECTION REGISTER /G01 R6 PORT DATA REGISTER On the initial RESET, R60 can’t be used digital input port, because this port is selected as an analog input port by ADCM register. To use this port as a digital I/O port, change the value of lower 4 bits of ADCM(address 0E8H). On the other hand,R6 port, all eight pins can not be used as digital I/O port simultaneously. At least one pin is used as an analog input. /G01 UNUSED PORTS All unused ports should be set properly that current flow through port doesn't exist. First consider the setting the port as an input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn’t flow. But input voltage level should be VSS or VDD . Be careful that if unspecified voltage, i.e. if unfirmed level voltage is applied to input pin, there can be little current ( max. 1mA at 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. Port R6 output data <00CC H > R47 R46 R45 R44 R43 R42 R41 R40 R/W R/W R/W RRR/W Determines I/O of R6 port 0 : Input 1 : Output <00CD H > R6DD R6DD7 R6DD6 R6DD5 R6DD4 R6DD3 R6DD2 R6DD1 R6DD0 W W W W RR
3.8. TERM IN A L TYPES PIN TERM IN A L TYPE Xin Xout RESET MP R00 ~ R07 Rd Data Bus Vss Data Bus MUX MUX D irection REG . VddData Bus Data Bus Data REG . MP Rd Data Bus Xin Xout Vdd Vss STO P Vss
R10 ~ R27 R20 ~ R27 R30 R31 R32 R33 R34 R35 R36 R37 Data Bus Data Bus Data Bus Vss MUX MUX Vdd MP From R30 ... Rd From R31 ... Wt From R32 ... R/W From R33 ... C From R34 ... SYNC From R35 ... BAK Data REG. Direction REG. Rd Data Bus Data Bus Data Bus Vss MUX Vdd MP Data REG. Direction REG. Rd to BRQ to HALT Data Bus Data Bus Address Bus Data Bus Vss MUX MUX Vdd MP Data REG. Direction REG. Rd
Data Bus Data REG . D irection REG . Rd To R40 /G01 IN T0 To R41 /G01 IN T1 To R42 /G01 IN T2 To R43 /G01 IN T3 To R44 /G01 EC 0 To R45 /G01 EC 2 To R50 /G01 Sin Data Bus Vss Data Bus MUX Vdd Selection Data Bus Data REG . D irection REG . Rd Data Bus Data Bus Data Bus Vss MUX MUX Vdd Selection From R46 ... T1O From R47 ... T3O From R51 ... Sout From R54 ... W D TO From R55 ... BUZ From R56 ... PW M0 From R57 ... PW M1 Data REG . D irection REG . Rd sck o sck i Data Bus exck Data Bus Data Bus Vss MUX MUX MUX Vdd Selection Data REG . D irection REG .
Data REG. Direction REG. To A/D Converter Data Bus Vss Data Bus MUX Direction REG. Vdd Data Bus Data REG. Rd Data Bus To A/D Converter Rd
- ELEC TR IC AL C H A R A C TER ISTIC S 4.1. A B O U LU TE MA XIMU M R A TIN G S P aram eter S ym bol U nit R atings Supply V oltage Vdd V -0.3 ~ 7.0 Input V oltage Vi V -0.3 ~ Vdd+0.3 Storage Tem perature Tstg °C -40 ~ 125 4.2. RECOM M EN D ED OPE R A TING CON D ITIONS Param eter S ym bol U nit Specifications M in. Typ. M ax. Supply V oltage Vdd V 4.5 5.5 O perating Frequency fXin M H z 1 8 O perating Tem perature Topr °C -20 85 4.3. A /D CON VER TER CH A R A C TERISTICS ( Vdd = 5V /G07 10% , Vss = 0/G08 , ,f (Xin) = 8 /G01 ) P aram eter Pin S ym bol U nit SPECI FICATIO N ETC M in. Typ. M ax. Analog Input R ange AN 0~AN 7 VAIN V Vss Vref Accuracy LSB /G07 3 C onversion Tim e Tconv /G03 20 Analog P ow er Suppiy Input R ange AV ref Vref V Vdd
4.4. DC CHARACTERISTICS Parameter Symbol Pin Test Condition Unit Specifications Min. Typ. Max. RESET,,R4,R5,R6 0.8Vdd Vdd "H" Input voltage Vih R0,R1,R2,R3 V 0.7Vdd Vdd Xin 0.9Vdd Vdd RESET,R4,R5,R6 0 0.12Vdd "L" Input voltage Vil R0,R1,R2,R3 V 0 0.3Vdd Xin 0 0.1Vdd "H" Input Leakage Current Iih all input pins Vi = Vdd /G09 -5 5 "L" Input Leakage Current Iil all input pins Vi = Vss /G09 -5 5 "H" output Voltage Voh R0,R1,R2,R3,R4,R5 Ioh = -2mA V Vdd-1 "L" output Voltage R0,R1,R2,R3,R4,R5 Iol = 5mA V 1.0 Power Operating Idd all input = Vss /G0A 20 40 Current STOP Istop /G09 20 100 Hysteresis V T+ ~ VT- RESET, V 0.3 0.8 EC2,EC0,Sin,Sclk,INT0~3 0.3 0.8 RAM Data Retention Vram Vdd at clock stop V 2.0
4.5. A C C H A R AC TER ISTICS 4.5.1. Input Con ditions P aram eter Pin S ym bol Unit SPECI FICATIO N ETC MIN . TYP. M A X. O perating Frequency Xin fcp M H z 1 - 8 S ystem C lock tsys ns 500 - 250 O scillation Stabilization Tim e Xin, Xout tST ms 20 E xternal C lock P ulse W idth Xin tcpw ns 100 E xternal C lock Transition Tim e Xin trcp,tfcp ns 20 Interrupt Pulse W idth IN T0~IN T3 tIW tsys 2 RESET Input "L" W idth RESET tR ST tsys 8 E vent C ounter Input Pulse W idth EC 0,EC 2 tECW tsys 2 E vent C ounter Transition Tim e EC 0,EC 2 trEC , tfEC ns 20 /G01 Tim ing C hart RESET Xin tfcptrcp 0.5 V Vdd-0.5V tcpw1/fcp tcpw INT3 INT2 INT1 INT0 0.2 Vdd0.8 Vdd tIWtIW tRST
0.2 Vdd
0.8 Vdd 0.8 Vdd tEC WtEC W trEC tfEC
4.5.2. Serial Transfer Parametet Pin Symbol Unit SPECIFICATION etc MIN. TYP. MAX. Serial Input Clock Pulse Sclk tscyc ns 2tsys+200 - 8 Serial Input Clock Pulse Width Sclk tsckw ns tsys+70 - 8 Serial Input Clock Pulse Transition Time Sclk tfsck,trsck ns - 30 Sin Input Pulse Transition Time Sin tfsin,trsin ns - 30 Sin Input Setup time(Exnternal Sclk) Sin tsus ns 100 - Sin Input Setup time(Internal Sclk) Sin tsus ns 200 - Sin Input Hold Time Sin ths ns tsys+70 - Serial Output Clock Cycle Time Sclk tscyc ns 4tsys - 16tsys Serial Output Clock Transition Time Sclk tsckw ns 2tsys-30 - Serial Output Clock Transition Time Sclk tfsck,trsck ns - 30 Serial Output Delay Time Sout tr EC, tfEC ns 100 /G01 Serial I/O Timing Chart Sin Sclk 0.2 Vdd Sout
0.8 Vdd
4.5.3. M icroprocessor M ode I/O Tim ing P aram eter Pin S ym bol Unit SPECI FICATIO N etc MIN . TYP. M A X. C ontrol C lock O utput W idth C tC L ns 90 - Address O utput D elay Tim e A0 ~ A 15 tdC A ns - 80 D ata Output D elay Time D 0 ~ D7 tdCD ns - 180 D ata O utput H old Tim e D 0 ~ D 7 thw ns - 20 D ata Input S etup Tim e D 0 ~ D 7 tsuR ns 80 - D ata Input H old Tim e D 0 ~ D 7 thR ns 15 - R d O utput D elay Tim e R d tdR d tsys - 90 W t O utput D elay Tim e W t tdW t tsys - 130 R /W O utput D elay Tim e R /W tdR W tsys - 50 sync O utput D elay Tim e SY N C tdsync tsys - 50 /G01 Tim ing C hart tsys tcw tcw 0.8V dd 0.8V dd 0.2V dd0.2V dd tdCA tdCD tstR tdRd tdWt tdRW 0.8V dd 0.2V dd tdsync 0.8V dd 0.2V dd thR thW 0.2V dd 0.2V dd 0.8V dd 0.2V dd C A 0~A 15 w rite m ode D 0~D 7 read m ode D 0~D 7 Rd Wt R/W SYNC
4.5.4. Bus Holding Timing Parameter Pin Symbol Unit SPECIFICATION etc MIN. TYP. MAX. BRQ Setup Time BRQ tSUB tsys 100 - BAK Delay Time BAK tdBA tsys - 50 BAK Release Delay Time BAK tdRBA tsys - 220 Bus(Address,Data) Control Release Delay Time D0 ~ D7 A0 ~ A15 Rd,Wt,R/W tdRA tsys - 210 /G01 Timing Chart Instruction Ececution Holding Cycle Instruction Ececution 0.2Vdd 0.2Vdd 0.2Vdd 0.2Vdd 0.8Vdd 0.8Vdd 0.2Vdd tdBA tsuBtsuB tdRBA tdRA Hi-Z C SYNC BRQ BAQ D0~D7 A0~A15 Rd Wt R/W
- INSTRU C TIO N SET 1. ARITHM ETIC/ LOGIC OPERATION NO. M N EM O N IC OP CO D E B Y TE NO C Y C LE NO O PER A TION FLA G NVGBHIZC 1 AD C #im m 04 2 2 Add w ith carry.
2 AD C dp 05 2 3 A /G09 ( A ) /G0A ( M ) /G0A C
3 AD C dp + X 06 2 4
4 AD C !abs 07 3 4 NV--H-ZC 5 ADC !abs + Y 15 3 5
6 AD C [ dp + X ] 16 2 6
7 AD C [ dp ] + Y 17 2 6
8 AD C { X } 14 1 3
9 AN D #im m 84 2 2 Logical AN D
10 AN D dp 85 2 3 A /G09 ( A ) /G0B ( M )
11 AN D dp + X 86 2 4
12 AN D !abs 87 3 4 N-----Z- 13 AN D !abs + Y 95 3 5
14 AN D [ dp + X ] 96 2 6
15 AN D [ dp ] + Y 97 2 6
16 AN D { X } 94 1 3
17 ASL A 08 1 2 Arithm etic shift left
18 ASL dp 09 2 4 C 7 6 5 4 3 2 1 0 N-----ZC
19 ASL dp + X 19 2 5
20 ASL !abs 18 3 5
21 C MP #im m 44 2 2 C om pare accum ulator contents w ith m em ory contents
22 C MP dp 45 2 3 ( A ) /G0C ( M )
23 C MP dp + X 46 2 4
24 C MP !abs 47 3 4 N-----ZC 25 C MP !abs + Y 55 3 5
26 C MP [ dp + X ] 56 2 6
27 C M P [ dp ] + Y 57 2 6
28 C MP { X } 54 1 3
29 C M P X #im m 5E 2 2 C om pare X contents w ith m em ory contents
30 C M P X dp 6C 2 3 ( X ) /G0C ( M ) N-----ZC
31 C M P X !abs 7C 3 4
32 C M P Y #im m 7E 2 2 C om pare Y contents w ith m em ory contents
33 C M P Y dp 8C 2 3 ( Y ) /G0C ( M ) N-----ZC
34 C M P Y !abs 9C 3 4
35 C O M dp 2C 2 4 1’S C omplem ent : ( dp ) /G09 /G0D ( dp ) N-----Z-
36 D AA D F 1 3 D ecim al adjust for addition N-----ZC
37 D AS C F 1 3 D ecim al adjust for substraction N-----ZC
/G02 /G02 ”0”/G02 /G02 /G02/G02 /G02/G02 /G02/G02
NO. M N EM O N IC OP CO D E B Y TE NO C Y C LE NO O PER A TION FLA G NVGBHIZC
38 DE C A A8 1 2 D eccrem ent N-----Z-
39 DE C dp A9 2 4 M /G09 ( M ) /G0C 1 N-----Z-
40 DE C dp + X B9 2 5 N-----Z-
41 D EC !abs B8 3 5 N-----Z-
42 DE C X AF 1 2 N-----Z-
43 DE C Y BE 1 2 N-----Z-
44 D IV 9B 1 12 D ivide : YA / X Q: A, R: Y NV--H-Z-
45 EO R #im m A4 2 2 E xclusive O R
46 EO R dp A5 2 3 A /G09 ( A ) ¯ ( M )
47 EO R dp + X A6 2 4
48 EO R !abs A7 3 4 N-----Z- 49 EO R !abs + Y B5 3 5
50 EO R [ dp + X ] B6 2 6
51 EO R [ dp ] + Y B7 2 6
52 EO R { X } B4 1 3
53 IN C A 88 1 2 Increm ent N-----ZC
54 IN C dp 89 2 4 M /G09 ( M ) /G0A 1 N-----Z-
55 IN C dp + X 99 2 5 N-----Z-
56 IN C !abs 98 3 5 N-----Z-
57 IN C X 8F 1 2 N-----Z-
58 IN C Y 9E 1 2 N-----Z-
59 LSR A 48 1 2 Logical shift right
60 LSR dp 49 2 4 7 6 5 4 3 2 1 0 C N-----ZC
61 LSR d p + X 59 2 5
62 LSR !abs 58 3 5
63 M U L 5B 1 9 M ultiply : YA/G09 Y /G0E A N-----Z-
64 O R #im m 64 2 2 Logical O R
65 O R dp 65 2 3 A /G09 ( A ) /G0F ( M )
66 O R dp + X 66 2 4
67 O R !abs 67 3 4 N-----Z- 68 O R !abs + Y 75 3 5
69 O R [ dp + X ] 76 2 6
70 O R [ dp ] + Y 77 2 6
71 O R { X } 74 1 3
72 R O L A 28 1 2 R otate left through carry
73 R O L dp 29 2 4 C 7 6 5 4 3 2 1 0 N-----ZC
74 R O L dp + X 39 2 5
75 R O L !abs 38 3 5
76 R O R A 68 1 2 R otate right through carry
77 R O R dp 69 2 4 7 6 5 4 3 2 1 0 C N-----ZC
78 RO R dp + X 79 2 5
79 R O R !abs 78 3 5 /G02 /G02/G02 /G02 /G02 /G02/G02 /G02/G02 /G02/G02 /G03/G03/G03/G03 /G03 /G03/G03 /G03/G03 /G03/G03
NO. M N EM O N IC OP CO D E B Y TE NO C Y C LE NO O PER A TION FLA G NVGBHIZC
80 SB C #imm 24 2 2 Substract w ith carry
81 SBC dp 25 2 3 A /G09 ( A ) /G0C ( M ) /G0C /G0D ( C )
82 SBC dp + X 26 2 4
83 SBC !abs 27 3 4 NV--HZC 84 SBC !abs + Y 35 3 5
85 SBC [ dp + X ] 36 2 6
86 SBC [ dp ] + Y 37 2 6
87 SBC { X } 34 1 3
88 TST dp 4C 2 3 Test mem ory contents for negative or zero
( dp ) /G0C 00H N-----Z-
89 XC N C E 1 5 E xchange nibbles w ithin the accumu lator
A7~A4 /G10 A3~A0 N-----Z- 2. REGISTER / M EM O R Y OPE R ATION NO. M N EM O N IC OP CO D E B Y TE NO C Y C LE NO O PER A TION FLA G NVGBHIZC
1 LD A #im m C 4 2 2 Load accumu lator
2 LDA dp C5 2 3 A /G09 ( M )
3 LD A dp + X C 6 2 4
4 LDA !abs C7 3 4 5 LD A !abs + Y D 5 3 5 N-----Z-
6 LD A [ dp + X ] D 6 2 6
7 LD A [ dp ] + Y D 7 2 6
8 LD A { X } D 4 1 3
9 LD A { X }+ D B 1 4 X- register auto-increm ent : A /G09 ( M ) , X/G09 X/G0A 1
11 LD X #im m 1E 2 2 Load X-register
12 LD X dp C C 2 3 X /G09 ( M ) N-----Z-
13 LD X dp + Y C D 2 4
14 LD X !abs D C 3 4
15 LD Y #im m 3E 2 2 Load Y-register
16 LD Y dp C 9 2 3 Y /G09 ( M ) N-----Z-
17 LD Y dp + X D 9 2 4
18 LD Y !abs D 8 3 4
19 STA dp E5 2 3 Store accum ulator contents in m em oy
20 STA dp + X E6 2 4 ( M ) /G09 A
21 STA !abs E7 3 4
23 STA [ dp + X ] F6 2 6
24 STA [ dp ] + Y F7 2 6
25 STA { X } F4 1 3
26 STA { X }+ FB 1 4 X- register auto-increm ent : ( M ) /G09 A , X/G09 X/G0A 1
NO. MNEMONIC CODE NO NO OPERATION NVGBHIZC
27 STX dp EC 2 4 Store X-register contents in memoy
29 STX !abs FC 3 5
30 STY dp E9 2 4 Store Y-register contents in memoy
32 STY !abs F8 3 5
33 TAX E8 1 2 Transfer accumulator contents to X-register : X /G09
A N-----Z-
34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y /G09 A N-----Z-
35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X /G09
36 TXA C8 1 2 Transfer X-register contents to accumulator: A /G09 X N-----Z-
37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer: sp /G09 X N-----Z-
38 TYA BF 1 2 Transfer Y-register contents to accumulator: A /G09 Y N-----Z-
39 XAX EE 1 4 Exchange X-register contents with accumulator :X/G10
A
40 XAY DE 1 4 Exchange Y-register contents with accumulator :Y/G10
A
41 XMA dp BC 2 5 Exchange memory contents with accumulator
42 XMA dp+X AD 2 6 ( M ) /G10 A N-----Z-
43 XMA {X} BB 1 5
44 XYX FE 1 4 Exchange X-register contents with Y-register : X/G10
Y 3. 16-BIT OPERATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC
1 ADDW dp 1D 2 5 16-Bits add without carry
YA /G09 ( YA ) /G0A ( dp +1 ) ( dp ) NV--H-ZC
2 CMPW dp 5D 2 4 Compare YA contents with memory pair contents :
(YA)/G0C (dp+1)(dp) N-----ZC
3 DECW dp BD 2 6 Decrement memory pair
( dp+1)( dp) /G09 ( dp+1) ( dp)/G0C 1 N-----Z-
4 INCW dp 9D 2 6 Increment memory pair
( dp+1) ( dp) /G09 ( dp+1) ( dp )/G0A 1 N-----Z-
5 LDYA dp 7D 2 5 Load YA
YA /G09 ( dp +1 ) ( dp ) N-----Z-
6 STYA dp DD 2 5 Store YA
( dp +1 ) ( dp ) /G09 YA
7 SUBW dp 3D 2 5 16-Bits substact without carry
YA /G09 ( YA )/G0C ( dp +1) ( dp) NV--H-ZC
- BIT MANIPULATION NO. M N EM O N IC OP CO D E B Y TE NO C Y C LE NO O PER A TION FLA G NVGBHIZC
3 BIT dp 0C 2 4 Bit test A w ith m em ory : MM----Z-
4 BIT !abs 1C 3 5 Z /G09 ( A ) /G0B ( M ) , N /G09 ( M7 ) , V/G09 ( M6 )
8 C LR G 40 1 2 C lear G -flag : G /G09 “0” --0-----
9 C LR V 80 1 2 C lear V-flag : V /G09 “0” -0--0---
11 EO R 1B M .bit AB 3 5 Bit exclusive-O R C -flag and N O T : C /G09 ( C ) ¯ /G0D (M .bit)
20 SE TG C0 1 2 S et G -flag : G /G09 “1” --1-----
22 TC LR 1 !abs 5C 3 6 Test and clear bits w ith A : N-----Z- 23 TSE T1 !abs 3C 3 6 Test and set bits w ith A : N-----Z- 5. BRANCH / JUM P O PERA TION NO. M N EM O N IC OP CO D E B Y TE NO C Y C LE NO O PER A TION FLA G NVGBHIZC 2 BBC dp.bit,rel y3 3 5/7 if ( bit ) /G11 0 , then pc/G09 ( pc ) /G0A rel 4 BBS dp .bit,rel x3 3 5/7 if ( bit ) /G11 1 , then pc/G09 ( pc ) /G0A rel
5 BC C rel 50 2 2/4 Branch if carry bit clear
if ( C )/G11 0 , then pc/G09 ( pc )/G0A rel
6 BC S rel D 0 2 2/4 Branch if carry bit set
if ( C )/G11 1 , then pc/G09 ( pc )/G0A rel
7 BE Q rel D 0 2 2/4 Branch if equal
if ( Z ) /G11 1 , then pc/G09 ( pc ) /G0A rel
NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC
8 BMI rel 90 2 2/4 Branch if minus
if ( N ) /G11 1 , then pc/G09 ( pc ) /G0A rel 9B N E r e l 7 0 2 2 / 4 Branch if not equal if ( Z ) /G11 0 , then
10 BPL rel 10 2 2/4 Branch if minus
if ( N ) /G11 0 , then pc/G09 ( pc ) /G0A rel
11 BRA rel 2F 2 4 Branch always
pc/G09 ( pc ) /G0A rel
12 BVC rel 30 2 2/4 Branch if overflow bit clear
if (V)/G11 0 , then pc/G09 ( pc)/G0A rel
13 BVS rel B0 2 2/4 Branch if overflow bit set
if (V)/G11 1 , then pc/G09 ( pc )/G0A rel 14 CALL !abs 3B 3 8 Subroutine call
15 CALL [dp] 5F 2 8 M( sp) /G09 ( pcH ), sp/G09 sp - 1, M( sp) /G09 ( pcL ), sp /G09 sp
- 1, if !abs, pc/G09 abs ; if [dp], pcL/G09 ( dp ), pcH/G09 ( dp+1 ) . 17 CBNE dp+X,rel 8D 3 6/8 if ( A ) /G12 ( M ) , then pc/G09 ( pc ) /G0A rel. 19 DBNE Y,rel 7B 2 4/6 if ( M ) /G12 0 , then pc/G09 ( pc ) /G0A rel. 20 JMP !abs 1B 3 3 Unconditional jump
22 JMP [dp] 3F 2 4
23 PCALL upage 4F 2 6 U-page call
M( sp)/G09 ( pcH ), sp/G09 sp - 1, M( sp) /G09 ( pcL ), sp /G09 sp - 1, pcL/G09 ( upage ), pcH/G09 ”0FFH” .
24 TCALL n nA 1 8 Table call : (sp)/G09 ( pcH ), sp/G09 sp - 1,
M( sp) /G09 ( pcL ),sp /G09 sp - 1, pcL/G09 (Table vector L), pcH/G09 (Table vector H)
- CONTROL OPERA TION & etc. NO. M N EM O N IC OP CO D E B Y TE NO C Y C LE NO O PER A TION FLA G NVGBHIZC
1 BR K 0F 1 8 Softw are interrupt : B /G09 ”1”, M ( sp)/G09 ( pcH ), sp /G09
sp - 1, M ( s )/G09 ( pcL ), sp/G09 sp - 1, M ( sp)/G09 ( P SW ), sp /G09 sp -1, pcL/G09 ( 0FFDE H ) , pcH/G09 ( 0FFD FH) . ---1-0--
2 D I 60 1 3 D isable interrups : I /G09 “0” -----0--
3 EI E0 1 3 Enable interrups : I /G09 “1” -----1--
5 PO P A 0D 1 4 sp /G09 sp/G0A 1, A /G09 M( sp )
7 PO P Y 4D 1 4 sp /G09 sp/G0A 1, Y /G09 M( sp )
8 PO P PSW 6D 1 4 sp /G09 sp/G0A 1, P SW /G09 M( sp ) ( restored )
9 PUS H A 0E 1 4 M( sp ) /G09 A , sp /G09 sp/G0C 1
11 PUSH Y 4E 1 4 M( sp ) /G09 Y , sp /G09 sp/G0C 1
12 PUSH PSW 6E 1 4 M( sp ) /G09 PSW , sp /G09 sp/G0C 1
13 R ET 6F 1 5 R eturn from subroutine
sp/G09 sp +1, pcL/G09 M ( sp ), sp /G09 sp +1, pcH /G09 M( sp )
14 R ETI 7F 1 6 R eturn from interrupt
sp /G09 sp +1, P SW /G09 M( sp ), sp/G09 sp +1, pcL/G09 M ( sp ), sp /G09 sp +1, pcH /G09 M( sp ) ( restored )
- GMS81516AT (OTP) PROGRAMMING The GMS81516AT is one-time PROM (OTP) micro - controller with 16K bytes electrically programmable read only memory for the GMS81508/16 system evaluation, first production and fast mass production. To programming the OTP device, user can have two way. One is using the universal programmer which is support HME microcontrollers, other is using the gen - eral EPROM programmer. 1. Using the Universal programmer Third party universal programmer support to program the GMS81516AT microcontrollers and lists are shown as below. Manufacturer: Advantech Web site: http://www.aec.com.tw Programmer: LabTool-48 Manufacturer: Hi-Lo systems Web site: http://www.hilosystems.com.tw Programmer: ALL-11, GANG-08 Socket adapters are supported by third party program - mer manufacturer. 2. Using the general EPROM(27C256) programmer The programming algorithm is simmilar with the stan - dart EPROM 27C256. It gives some convience that user can use standard EPROM programmer. Make sure that 1ms programming pulse must be used, it gener - ally called "Intelligent Mode". Do not use 100us programming pulse mode, "Quick Pulse Mode". When user use general EPROM programmer, socket adaper is essencially required. It convert pin to fit the pin of general 27C256 EPROM. Three type socket adapters are provided according to package variation as below table. Socket Adapter Package Type OA815A-64SD 64 pin SDIP OA815A-64QF-10 64 pin LQFP (10 x 10) OA815A-64QF 64 pin QFP (14 x 20) With these socket adapters, the GMS81516AT can easy be programming and verifying using Intel 27C256 EPROM mode on general-purpose PROM programmer. In assembler and file type, two files are generated after compiling. One is "*.HEX", another is "*.OTP". The "*.HEX" file is used for emulation in circuit emulator (CHOICE-Dr TM or CHOICE-Jr TM ) and "*.OTP" file is used for programming to the OTP device. Programming Procedure 1. Select the EPROM device and manufacturer on EPROM programmer (Intel 27C256). 2. Select the programming algorithm as an Intelligent mode (apply 1ms writing pulse), not a Quick pulse mode. 3. Load the file (*.OTP) to the programmer. 4. Set the programming address range as below table. Address Set Value Buffer start address 4000 H Buffer end address 7FFF H Device start address 4000 H 5. Mount the socket adapter with the GMS81516AT on the PROM programmer. 6. Start the PROM programmer to programming/ verifying. GMS81508/16 HYUNDAI MicroElectronics
The GMS81516AT is a high-performance CMOS 8-bit microcontroller with 16K bytes of EPROM. The d evice is one of GMS800 family. The HME GMS81516AT is a powerful microcontroller which prov ides a highly flexible and cost effective solution to many embedded control applications. The GMS81516A T provides the following standard features: 16K bytes of EPROM, 448 bytes of RAM, 56 I/O lines, 16-bit or 8-bit timer/counter, a precision analog to digital converter, PWM, on-chip oscillator and clock circuitry. PIN CONFIGURATION 64SDIP GMS81516AT HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING
GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics
NOTES: (1) These pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) These pins must be connected to V DD . (3) X OUT pin must be opened during programming. Pin No. MCU Mode OTP Mode
1 VDD - VDD -
2 MP I VPP -
3 AVSS I (1) I
4 AVREF I (1) I
5 R67/AN7 I/O (1) I
6 R66/AN6 I/O (1) I
7 R65/AN5 I/O (1) I
8 R64/AN4 I/O (1) I
9 R63/AN3 I (1) I
10 R62/AN2 I (1) I
11 R61/AN1 I (1) I
12 R60/AN0 I (1) I
13 R57/PWM1 I/O (1) I
14 R56/PWM0 I/O (1) I
15 R55/BUZ I/O (1) I
16 R54/WDTO I/O (1) I
17 R53/ SRDY I/O (1) I
18 R52/SCLK I/O (1) I
19 R51/SOUT I/O (1) I
20 R50/SIN I/O (1) I
21 R47/T3O I/O (2) I
22 R46/T1O I/O (2) I
23 R45/ EC2 I/O CE I
24 R44/ EC0 I/O OE I
25 R43/INT3 I/O (1) I
26 R42/INT2 I/O (1) I
27 R41/INT1 I/O (1) I
28 R40/INT0 I/O (1) I
29 RESET I (1) I
30 XIN I (1) I
31 XOUT O (3) O
32 VSS - VSS -
Pin No. MCU Mode OTP Mode
33 R27 I/O A15 I
34 R26 I/O A14 I
35 R25 I/O A13 I
36 R24 I/O A12 I
37 R23 I/O A11 I
38 R22 I/O A10 I
39 R21 I/O A9 I
40 R20 I/O A8 I
41 R17 I/O A7 I
42 R16 I/O A6 I
43 R15 I/O A5 I
44 R14 I/O A4 I
45 R13 I/O A3 I
46 R12 I/O A2 I
47 R11 I/O A1 I
48 R10 I/O A0 I
49 R07 I/O O7 I/O
50 R06 I/O O6 I/O
51 R05 I/O O5 I/O
52 R04 I/O O4 I/O
53 R03 I/O O3 I/O
54 R02 I/O O2 I/O
55 R01 I/O O1 I/O
56 R00 I/O O0 I/O
57 R37 I/O (1) I
58 R36 I/O (1) I
59 R35 I/O (1) I
60 R34 I/O (1) I
61 R33 I/O (1) I
62 R32 I/O (1) I
63 R31 I/O (1) I
64 R30 I/O (1) I
I/O: Input/Output Pin I: Input Pin O: Output Pin HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING
NOTES: (1) These pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) These pins must be connected to V DD . (3) X OUT pin must be opened during programming. Pin No. MCU Mode OTP Mode
1 R65/AN5 I/O (1) I
2 R64/AN4 I/O (1) I
3 R63/AN3 I (1) I
4 R62/AN2 I (1) I
5 R61/AN1 I (1) I
6 R60/AN0 I (1) I
7 R57/PWM1 I/O (1) I
8 R56/PWM0 I/O (1) I
9 R55/BUZ I/O (1) I
10 R54/WDTO I/O (1) I
11 R53/ SRDY I/O (1) I
12 R52/SCLK I/O (1) I
13 R51/SOUT I/O (1) I
14 R50/SIN I/O (1) I
15 R47/T3O I/O (2) I
16 R46/T1O I/O (2) I
17 R45/ EC2 I/O CE I
18 R44/ EC0 I/O OE I
19 R43/INT3 I/O (1) I
20 R42/INT2 I/O (1) I
21 R41/INT1 I/O (1) I
22 R40/INT0 I/O (1) I
23 RESET I (1) I
24 XIN I (1) I
25 XOUT O (3) O
26 VSS - VSS -
27 R27 I/O A15 I
28 R26 I/O A14 I
29 R25 I/O A13 I
30 R24 I/O A12 I
31 R23 I/O A11 I
32 R22 I/O A10 I
Pin No. MCU Mode OTP Mode
33 R21 I/O A9 I
34 R20 I/O A8 I
35 R17 I/O A7 I
36 R16 I/O A6 I
37 R15 I/O A5 I
38 R14 I/O A4 I
39 R13 I/O A3 I
40 R12 I/O A2 I
41 R11 I/O A1 I
42 R10 I/O A0 I
43 R07 I/O O7 I/O
44 R06 I/O O6 I/O
45 R05 I/O O5 I/O
46 R04 I/O O4 I/O
47 R03 I/O O3 I/O
48 R02 I/O O2 I/O
49 R01 I/O O1 I/O
50 R00 I/O O0 I/O
51 R37 I/O (1) I
52 R36 I/O (1) I
53 R35 I/O (1) I
54 R34 I/O (1) I
55 R33 I/O (1) I
56 R32 I/O (1) I
57 R31 I/O (1) I
58 R30 I/O (1) I
59 VDD - VDD -
60 MP I VPP -
61 AV SS I (1) I
62 AV REF I (1) I
63 R67/AN7 I/O (1) I
64 R66/AN6 I/O (1) I
I/O: Input/Output Pin I: Input Pin O: Output Pin GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics
NOTES: (1) These pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) These pins must be connected to V DD . (3) X OUT pin must be opened during programming. Pin No. MCU Mode OTP Mode
1 R63/AN3 I (1) I
2 R62/AN2 I (1) I
3 R61/AN1 I (1) I
4 R60/AN0 I (1) I
5 R57/PWM1 I/O (1) I
6 R56/PWM0 I/O (1) I
7 R55/BUZ I/O (1) I
8 R54/WDTO I/O (1) I
9 R53/ SRDY I/O (1) I
10 R52/SCLK I/O (1) I
11 R51/SOUT I/O (1) I
12 R50/SIN I/O (1) I
13 R47/T3O I/O (2) I
14 R46/T1O I/O (2) I
15 R45/ EC2 I/O CE I
16 R44/ EC0 I/O OE I
17 R43/INT3 I/O (1) I
18 R42/INT2 I/O (1) I
19 R41/INT1 I/O (1) I
20 R40/INT0 I/O (1) I
21 RESET I (1) I
22 XIN I (1) I
23 XOUT O (3) O
24 VSS - VSS -
25 R27 I/O A15 I
26 R26 I/O A14 I
27 R25 I/O A13 I
29 R24 I/O A12 I
29 R23 I/O A11 I
30 R22 I/O A10 I
31 R21 I/O A9 I
32 R20 I/O A8 I
Pin No. MCU Mode OTP Mode
33 R17 I/O A7 I
34 R16 I/O A6 I
35 R15 I/O A5 I
36 R14 I/O A4 I
37 R13 I/O A3 I
38 R12 I/O A2 I
39 R11 I/O A1 I
40 R10 I/O A0 I
41 R07 I/O O7 I/O
42 R06 I/O O6 I/O
43 R05 I/O O5 I/O
44 R04 I/O O4 I/O
45 R03 I/O O3 I/O
46 R02 I/O O2 I/O
47 R01 I/O O1 I/O
48 R00 I/O O0 I/O
49 R37 I/O (1) I
50 R36 I/O (1) I
51 R35 I/O (1) I
52 R34 I/O (1) I
53 R33 I/O (1) I
54 R32 I/O (1) I
55 R31 I/O (1) I
56 R30 I/O (1) I
57 VDD - VDD -
58 MP I VPP -
59 AV SS I (1) I
60 AV REF I (1) I
61 R67/AN7 I/O (1) I
62 R66/AN6 I/O (1) I
63 R65/AN5 I/O (1) I
64 R64/AN4 I/O (1) I
I/O: Input/Output Pin I: Input Pin O: Output Pin HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING
PIN FUNCTION (OTP Mode) VPP (Program Voltage) VPP is the input for the program voltage for programming the EPROM. CE ( Chip Enable) CE is the input for programming and verifying internal EPROM. OE (Output Enable) OE is the input of data output control signal for verify. A0~A 15 (Address Bus) A0~A 15 are address input pins for internal EPROM. O0~O 7 (EPROM Data Bus) These are data bus for internal EPROM. PROGRAMMING The GMS81516AT has address A 0~A 15 pins. Therefore, the programmer just program the data (from 4000 H to 7FFF H ) into the GMS81516AT OTP device, during addresses A 14 ,A15 must be pulled to a logic high. When the programmer write the data from 4000 H to 7FFF H , consequently, the data actually will be written into addresses C000 H to FFFF H of the OTP device. 1. The data format to be programmed is made up of Motorola S1 format. Ex) "Motorola S1" format; S0080000574154434880 S1244000E1FF3BFF04A13F8F06E101711B821B1BE01D1B3B191BF6181BF01C1BFF081BFF0AE0 S12440211BF5091BFF0B1BFF3F1B003E1B003D1B003C1BFF3B1B003A1BFF391BFF381BFF353D S1057FF2983FB2 S1057FFEFF3F3F S9030000FC 2. Down load above data into programmer from PC. 3. Programming the data from address 4000 H to 7FFF H into the OTP MCU, the data must be turned over respectively, and then record the data. When read the data, it also must be turned over. Ex) 00(00000000) → FF(11111111), 76(01110110) → 89(10001001), FF (11111111)→ 00(00000000) etc. 4. Of course, the check sum is result of the sum of whole data from address 4000 H to 7FFF H in the file (not reverse data of OTP MCU). * When GMS81516AT shipped, the blank data of GMS81516AT is initially 00 H (not FF H ). GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics
xxxxxxxx.OTP FF FF FF Down Loadin gProgram 4000 H 4001 H 4002 H 4003 H 4004 H 4005 H 4006 H 4007 H 7FF2 H 7FF3 H 7FFE H 7FFF H FF FF FF 4000 H 4001 H 4002 H 4003 H 4004 H 4005 H 4006 H 4007 H 7FF2 H 7FF3 H 7FFE H 7FFF H FC C000 H C001 H C002 H C003 H C004 H C005 H C006 H C007 H FFF2 H FFF3 H FFFE H FFFF H Reading Verify Up Loading Data Addres sData Addres sData Programmer Buffer Checksum = E1+FF+3B+FF+04+A1+3F+8F+ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 98+3F+ ⋅ ⋅ ⋅ ⋅ +FF+3F Programming Example Program area
16 K BYTES
File Type: Motorola S-format GMS81516AT 4000 H 7FFF H Addressxxxxxxxx.OTP Universal Programmer Down Loading Program Verify Reading Programming Flow HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING
(TA = 25 °C ± 5°C) Mode CE OE A0~A 15 VPP V DD O 0~O 7 Read X X VDD 5.0V DOUT Output Disable VIH VIH X VDD 5.0V Hi-Z Programming VIL VIH X VPP VDD DIN Program Verify X X VPP VDD DOUT NOTES: 1. X = Either V IL or V IH 2. See DC Characteristics Table for V DD and V PP voltages during programming. DC CHARACTERISTICS (V SS =0 V, T A = 25 °C ± 5°C) Symbol Item Min Typ Max Unit Test condition VPP Intelligent Programming 12.0 - 13.0 V VDD (1) Intelligent Programming 5.75 - 6.25 V IPP (2) VPP supply current 50 mA CE =V IL IDD (2) VDD supply current 30 mA VIH Input high voltage 0.8 V DD V VIL Input low voltage 0.2 V DD V VOH Output high voltage VDD -1.0 V IOH = -2.5 mA VOL Output low voltage 0.4 V IOL = 2.1 mA IIL Input leakage current 5 uA NOTES: 1. V DD must be applied simultaneously or before V PP and removed simultaneously or after V PP . 2. The maximum current value is with outputs O 0 to O 7 unloaded. GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics
NOTES: 1. The input timing reference level is 1.0 V for a V IL and 4.0V for a V IH at V DD =5.0V 2. To read the output data, transition requires on the OE from the high to the low after address setup time t AS . Address Valid tOE Valid Output tDH Addresses OE Output High-Z VIH VIL VIH VIL VIH VIL tAS (2) READING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be steady May change from H to L May change from L to H Do not care any change permitted Does not apply W ill be steady W ill be changing from H to L W ill be changing from L to H Changing state unknown Center line is high impedance "Off" state SWITCHING WAVEFORMS HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING
NOTES: 1. The input timing reference level is 1.0 V for a V IL and 4.0V for a V IH at V DD =5.0V tDFP Addresses Data High-Z VIH VIL 12.5V VDD VPP VDD CE OE 6.0V 5.0V tAS tDS tVPS tVDS tOPW tPW tOES Program Program Verify tDH VIH VIL VIH VIL VIH VIL tAH Address Stable Data In Stable Data out Valid tOE PROGRAMMING ALGORITHM WAVEFORMS GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics
AC READING CHARACTERISTICS (V SS =0 V, T A = 25 °C ± 5°C) Symbol Item Min Typ Max Unit Test condition tAS Address setup time 2 us tOE Data output delay time 200 ns tDH Data hold time 0 ns NOTES: 1. V DD must be applied simultaneously or before V PP and removed simultaneously or after V PP . AC PROGRAMMING CHARACTERISTICS (V SS =0 V, T A = 25 °C ± 5°C; See DC Characteristics Table for V DD and V PP voltages.) Symbol Item Min Typ Max Unit Condition* (Note 1) tAS Address set-up time 2 us tOES OE set-up time 2 us tDS Data setup time 2 us tAH Address hold time 0 us tDH Data hold time 1 us tDFP Output disable delay time 0 us tVPS VPP setup time 2 us tVDS VDD setup time 2 us tPW Program pulse width 0.95 1.0 1.05 ms Intelligent tOPW CE pulse width when over programming 2.85 78.75 ms (Note 2) tOE Data output delay time 200 ns *AC CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%) . . . . 20 ns NOTES: 1. V DD must be applied simultaneously or before V PP and removed simultaneously or after V PP . 2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X Refer to page 13. HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING
VDD = 6.0V VPP = 12.5V X = 0 PROGRAM ONE 1 ms PULSE INCREMENT X VERIFY BYTE VERIFY ONE BYTE LAST ADDRESS ? VDD = V PP = 5.0V COMPARE ALL BYTES TO ORIGINAL DATA DEVICE PASSED INCREMENT ADDRESS YES NO FAIL PASS FAIL PASS NO YES FAIL PASS DEVICE FAILED PROGRAM ONE PULSE OF 3X msec DURATION X = 25 ? ADDRESS= FIRST LOCATION Intelligent Programming Algorithm GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics