GM0936TQ HYNIX | Alldatasheet

Document overview

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Technical content

Features

  • Designed for standard 2.048MHz master clock for U.S. Analog, U.S. Digital, CT2, DECT, GSM, and PCS Standards for Hand - held Battery - Powered Telephones
  • On - chip voltage references
  • Package Type : 48 LQFP, 20 DIP, 20 SOP
  • Single 3 - V operation
  • Low power consumption – Operating mode .... 20mW Typ – Power - down mode ... 1mW Typ
  • Combined A/D, D/A, and Filters
  • Electret microphone bias reference voltage available
  • Compatible with all digital signal processors ( DSPs )
  • Programmable volume control
  • 300 Hz - 3.6 kHz Passband with Specified Master clock NC NC NC AVcc NC NC NC NC DVcc MICMUTE NC VMID NC AGND NC NC NC NC NC NC DGND NC NC NC NC EARGS EARB EARA____ PDN MICBIAS MICGS MICIN EXTMIC MICSEL NC NC NC DIN FSR EARMUTE NC CLK FSX DOUT NC NC NC

48 LQFP

(TOP VIEW) ____ PDN EARA EARB EARGS MICMUTE NC DIN EARMUTE MICBIAS MICGS MICIN VMID GND NC NC DOUT FSX CLK

20 DIP/SOP

(TOP VIEW) GM0936TQ Voice - Band Audio CODEC for CDMA

Description

The GM0936TQ contains A/D and D/A conversion functions integrate d on a single chip, and utilizes the sigma - delta modulation technique to achieve high resolution data conve rsion and low power consumption. The GM0936TQ is an ideal analog front end device fo r high performance voice - band communication systems. Cellular telephone systems are targeted i n particular; however, these integrated circuits can function in other systems including digi tal audio, telecommunications, and data acquisition. The transmit section is designed to interface directly with an electret microphone element. One of two microphone input signals, MICIN and EXTMIC, is selected by MICS EL. If MICSEL is floated or Low, then MICIN is selected, and if MICSEL is high, then EXTMIC is selected. The microphone input signal (MICIN and EXTMIC) is buffered, first - order low - pass filtered, and amplified with provision for setting the amplifier gain to accommodate a range of signal inpu t levels. The amplified signal is 1bit - modulated by second - order sigma - delta modulator. The modulated signal is then applied to the inp ut of high - performance FIR - type digital decimation filters with frequency response equaliza tion. The resulting data is then clocked out of DOUT as a serial data stre am. The receive section takes a frame of sereal data on DIN and converts it to analog through high - performance FIR - type digital interpolation filter together with frequency respon se equalization, second - order digital sigma - delta modulator, and analog reconstruction filters. On - chip voltage reference ensures a highly integrated solution and all internal voltage references are generated. An internal reference voltage, VMID, is used to devel op the midlevel virtual ground for all the amplifier circuits and the microphone bias circuit.Another r eference voltage, MICBIAS, can supply bias current for the microphone. Serial DSP interfaces for transmit and receive paths support di rectly industry standard DSP processors. The GM0936TQ devices are characterized for operation from - 20 to 70 ¡É.

Analog 2nd order S - D Modulator Block Diagram Integrator1 Integrator2 Quantizer1/21/2 Yx Digital 2nd order S - D Modulator Block Diagram Quantizer Yx Delay1Delay2 ANALOG Σ Δ- MODULATOR VOLTAGE REFERENCE POST FILTER 1 - BIT DAC SINC 3 - FILTER FIR - FILTER DIGITAL Σ Δ- MODULATOR SINC 2 - FILTER FIR - FILTER VMID MICIN AV CC AGND DV CC DGND INTERFACE DIN DOUT CLK MICMUTE EARA EARB MICGS MICBIAS FSR FSX MICSEL EXTMIC EARGS EARMUTE _ __ PDN

NAME LQFP SOP&DIP I/O DESCRIPTION AGND 34 16 Analog Ground AVcc 4 5 Analog Power (3V) EARA 44 2 O Earphone output EARB 45 3 O Side-tone output EARGS 46 4 I Side-tone input EARMUTE_ 17 10 I Earphone output mute control signal MICBIAS 42 20 O Microphone bias MICGS 41 19 O Output of the internal microphone amplifier MICIN 40 18 I Microphone input MICMUTE_ 11 6 I Microphone input mute VMID 36 17 O Bias voltage reference. A pair of external, low- leakage, high-frequency capacitors (1 µF and 470 pF) should be connected between VMID and ground for filtering ETMIC 39 N/A I Hand-free MIC-IN MICSEL 38 N/A I MIC-IN selection input. When float or low, MICSEL selects MICIN. When high, MICSEL selects EXTMIC.

NAME LQFP SOP&DIP I/O DESCRIPTION CLK 19 11 I Clock input (2.048 MHz) DGND 27 16 Digital ground DIN 15 8 I Receive data input DOUT 21 13 O Transmit data output DVcc 9 5 Digital power (3 V) FSR 16 9 I Frame-synchronization clock input for receive channel FSX 20 12 I Frame-synchronization clock input for receive channel PDN_ 43 1 I Power-down input, Active Low NC 1,2,3, 5,6,7, 8,10, 12,13, 14,18, 22,23, 24,25, 26,28, 29,30, 31,32, 33,35 7, 14, 15 No internal connection

Electrical Characteristics

SYMBOLPARAMETER MIN MAX UNIT DV CC , AV CCSupply Voltage Range V V indDigital Input Voltage Range - 0.3 V V inaAnalog Input Voltage Range - 0.3 V Absolute Maximum Ratings over operating free - air temperature range TYP SYMBOLPARAMETER MIN MAX UNIT DV CC , AV CCSupply Voltage 3.3 V V IHHigh - level Input Voltage V T A Operating free - air Temperature - 20 70 ¡É Recommended Operating Conditions TYP 3.02.7 0.8 - 0.3 3.6 3.6 3.6 Low - level Input Voltage V IL 2.2 V PARAMETER MIN MAX UNIT Power Dissipation , Operating mW Power Dissipation , Power down TYP Power Supply Characteristics, f CLK = 2.048 MHz, outputs not loaded, Vcc =3V, T A =25 ¡É 1 mW PARAMETER MIN MAX UNIT Input Capacitance 10 pF Input Leakage Current - 10 10 §Ë Low - level output Voltage (I OL = 3.2mA) 0.4 V High - level output Voltage (I OH = - 3.2mA) 2.4 V TYP Digital Characteristics (T A =25 ¡É , DV CC = AV CC = 3V)

TEST CONDITIONSPARAMETER MIN MAX UNIT V I = 0 to 3 VV IO Input offset voltage at MICIN mV nA MHz Microphone interface TYP Speaker interface + 5 + 200 1.5 I IB Input bias current at MICIN B 1 Unity - gain bandwidth, open loop at MICIN V/V µA 10000 Av Large - signal voltage amplification at MICGS VMID mA1MICBIAS(source only) Iomax Maximum output current TEST CONDITIONSPARAMETER MIN MAX UNIT V O(PP) AC output voltage Vpp mA Ω TYP + 1 I Omax Maximum output current r o Output resistance at EARA, EARB dB- 60Gain change R L = 600 Ω EARMUTE low, max level when muted

S/(N+THD) dB Analog Characteristics (T A =25 ¡É , DV CC = AV CC = 3V, fs = 8 KHz) TYP A/D Converter Output Sample Rate 8 KHz Maximum output current for MICBIAS 1 mA Maximum output voltage for Microphone Amplifier Vpp0.95 PARAMETER MIN MAX UNIT 0.76 0.73 dB TYP Transmit filter transfer over recommended ranges of supply volta ge and free - air temperature, CLK=2.048 MHz, FSX=8 kHz 0.67 - 1.9 - 4.5 Gain relative to input signal at 1.02 kHz Input amplifier set for unity gain, the output for 400mVpp signal at MICGS is 0dB f MICIN = 50 Hz f MICIN = 200 Hz f MICIN = 300 Hz f MICIN = 1 kHz f MICIN = 2 kHz f MICIN = 3 kHz TEST CONDITIONS - 5.4 - 8.9 f MICIN = 3.3 kHz f MICIN = 3.8 kHz 0.85

S/(N+THD) dB TYP D/A Converter 128 Maximum output current (R L =600 §Ù) mA Output Voltage Range Vpp0.81 + 1 0.91 PARAMETER MIN MAX UNIT 178 dB TYP Transmit idle channel noise and distortion, linear mode selected , over recommended ranges of supply voltage and free - air temperature (see Notes 1 and 2) 52.3 51.9 50.7 49.0 Gain relative to input signal at 1.02 kHz MICIN connected to MICGS through a 22 k Ω resistor MICIN to DOUT at 0 dBm0 TEST CONDITIONS µV rmsTransmit noise MICIN to DOUT at - 3 dBm0 MICIN to DOUT at - 6 dBm0 MICIN to DOUT at - 9 dBm0 MICIN to DOUT at - 12 dBm0 Notes: 1. The input amplifier is set for inverting unity gain. 2. Transmit noise, linear mode: 200 µV rms is equivalent to - 75 dB (referenced to device 0 dB level). PARAMETER MIN MAX UNIT 59.7 dB TYP Receive distortion, linear mode selected, over recommended ranges of supply voltage and free - air temperature 59.6 56.1 55.3 Receive signal - to - distortion ratio with sine - wave input DIN to EARA at - 3 dBm0 TEST CONDITIONS DIN to EARA at - 6 dBm0 DIN to EARA at - 9 dBm0 DIN to EARA at - 12 dBm0 DIN to EARA at 0 dBm0

Supply voltage rejection, transmit channel dB Supply voltage rejection, receive channel TYP Power supply rejection over recommended ranges of supply voltage and operating free - air temperature - 50 TEST CONDITIONS Idle channel, supply signal = 100mVrms f = 1 kHz (measured at DOUT) Idle channel, supply signal = 100mVrms f = 1 kHz (measured at EARA) dB- 50

Transmit timing requirements Receive timing requirements MIN MAX UNIT tsu (FSX) Setup time, FSX high before CLK ¡é th (FSX) Hold time, FSX high after CLK ¡é 20 468 20 468 ns ns MIN MAX UNIT tsu (FSR) Setup time, FSR high before CLK ¡é th (FSR) Hold time, FSR high after CLK ¡é 20 468 20 468 ns ns tsu (DIN) Setup time, DIN high or low before CLK ¡é th (DIN) Hold time, DIN high or low after CLK ¡é ns ns Clock timing requirements MIN NOM MAX UNIT Duty cycle, CLK 45% 50% 55% PARAMETER MIN MAX UNIT CLK Frequency Sampling Rate 8 KHz DIN Delay from CLK nsDOUT Delay from CLK ns TYP Timing (T A =25 ¡É , DV CC = AV CC = 3V)

2.048 MHz

Figure1. Receive Side Timing Diagram Timing Diagram 0 1 2 3 4 15 16 17 See Note BSee Note A th(FSR)tsu(FSR) 20% 80% Receive Time Slot 80% 3DIN 15 16 15 16 1 ≈≈≈≈4 th(DIN) tsu(DIN) 20% CLK FSX Figure2. Transmit Side Timing Diagram 0 1 2 3 4 15 16 17 See Note BSee Note A th(FSX)tsu(FSX) 20% 80% Transmit Time Slot 80% DOUT tpd3 20% NOTES: A. This window is allowed for FSR high. B. This window is allowed for FSR low. C. Transitions are measured at 50%. NOTES: A. This window is allowed for FSX high. B. This window is allowed for FSX low. C. Transitions are measured at 50%. tpd1 See Note C See Note C tpd2 1 2 3 4 ≈≈≈≈ 15 16

To minimize power consumption, a power - down mode is provided. mode, the average power consumption is reduced to 1mW. falling edges of CLK following FSR. Table 1. Power-On and Power-Down Procedures

NOTE A: Terminal numbers shown are for the 48 LQFP package. with a feedback network and applied to the amplifier inverting i nput (MICIN) to set the amplifier gain. VMID appears at a terminal to provide a place to filter the VMID voltage. Figure 3. Typical Microphone Interface The MICMUTE input causes the digital circuitry to transmit all zero code on DOUT. frequency response equalization.

The encoder performs an A/D conversion on a 2nd - order Sigma - Delta ( Σ- Δ) modulator using a switched - capacitor technology and high - performance FIR - type digital decimation filters with frequency response equalization. The resulting data is then cloc ked out of DOUT as a serial data. data word structure The data word is 16 bits long. The first 13 bits comprises the a udio data sample, and the last three bits form the volume control word in the receive direction (DIN) and are zero pad bits in the transmit direction (DOUT). The sign bit is transmitted first. receive operation decoding The serial data word is received at DIN on the first 13 clock cy cles. The receive section converts a frame of sereal data to analog through high - performance FIR - type digital interpolation filter together with frequency response equalization, second - order digital sigma - delta modulator, and analog reconstruction filters. receive buffer The receive buffer contains the volume control. earphone amplifier The output can be used to drive a single - ended load with the output signal voltage centered around VMID . EARA in Figure 4 is the output pin for the decoded analog sign al. EARB in the figure is used for sidetone signal output which is used internally. A resistor - capacitor pair attached to EARB is embedded to reduce the number of on - board components. See the next section for more information on sidetone generation. PRINCIPLES OF OPERATION

NOTE A: Terminal numbers shown are for the 48 LQFP package. Figure 4. Earphone Audio - Output Amplifier Configuration latched into the GM0936TQ and must be present in each received d ata word.

0 D12

Table 2. Receive-Data Bit Definitions

NOTE A: Terminal numbers shown are for the 48 TQFP package. higher clock frequencies and sample rates The GM0936TQ is designed to work with sample rates up to 16kHz w here the frequency of the frame sync determines the sampling frequency. However, there is a fund amental requirement to maintain the ratio of the master clock frequency, f CLK , to the frame sync frequency, f FSR / f FSX . This ratio for the GM0936TQ is 2.048 MHz/8 kHz, or 256 master clocks per frame sync . For example, to operate the GM0936TQ at a sampling rate of f FSR and f FSX equal to 16 kHz, f CLK must be 256 times 16 kHz, or 4.096 MHz. If the GM0936TQ is operated above an 8 - kHz sample rate, however, it is expected that the performance becomes somewhat degraded. Exact parameter specifica tions for rates up to 16 - kHz sample rate are not specified at this time. output gain set and sidetone considerations The single - ended outputs EARA and EARB are capable of driving output power level up to 1mW into load impedance of 1k Ω separately.The sidetone signal and the received signal can be summed by configuring external components like in Figure 5. The amount of sidetone mixing is controlled by the resistor connected between EARB and EARGS. If the resistance bec ome greater, the amount of sidetone mixing increases. Figure 5. Configuration for Gain - Setting and Sidetone

APPLICATION INFORMATION

To speaker driving amp.