FX623P

FX623 CMLMICRO | Alldatasheet

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Technical content

Features

Measures Call Progress Tone Frequencies [‘Busy’, ‘Dial’, ‘Fax-Tone’ etc.] Telephone, PABX, Fax and Dial-Up Modem Applications Low-Power Requirement (600µA at 3.3 Volts TYP ) for Line-Powered Applications Custom Tone Decoder [13 Call-Progress Frequencies Recognized] Operates to a 3.579545MHz Telephone System Clock Operates Under Simple Logic or µProcessor System Control The FX623 is a low-power decoding microcircuit that measures the frequency of telephone system call progress tones. With progress signals input from the telephone line, this single-chip product is programmed to recognize up to thirteen of the World's most commonly used call-progress frequencies, analyze signal quality and present the measured result as a 4-bit parallel data word at the tri-state Data Output. Using the parallel information from the FX623, the host system suitably configured, can recognize such call progress information as: ‘Dial’, ‘Busy’, ‘Number Unobtainable’, ‘Ringing’ and Fax/Modem system signals. Brief Description This information can then be employed in telephone applications (simple or complex) to control telephone operations. The data output will require a suitable software format to analyze the frequency information from the FX623. Requiring only a single 3.0 [MIN] volt power supply, the FX623 may be line-powered and will operate under simple logic or system µProcessor control using the 'Data-Change, 'Hold' and 'Chip-Select' functions. The FX623, whose small size and low power consumption makes it ideal for remote applications, requires a 3.579545MHz telephone system clock or Xtal input, is available in a 16-pin plastic DIL package. Fig.1 Functional Block Diagram XTAL/CLOCK OSCILLATOR SIGNAL IN XTAL/CLOCK Clocks Clocks DATA CHANGE DATA OUTPUTS IRQ VDD VSS CONTROL CIRCUITRY TIMER CHIP SELECT HOLD PURS DIGITAL FILTER OUTPUT LATCHES LIMITER XTAL MEASUREMENT AND DECODE FX623

Data Outputs: A 4-bit parallel data word, forming a HEX character representing the decoded tone frequency. This word is output after a successful decode. Table 1 details the Hex character output codes for the relevant decoded tone frequencies. Upon power-up this output is set to ‘E H ’, but no Data Change pulse generated. These are tri-state outputs. Q3: Q2: Q1: Q0: V DD : Positive supply rail. A minimum supply voltage of 3.0 volts is required. Levels and voltages within this decoder are dependent upon this supply. limiter section is set internally; this pin should not be loaded with any other circuitry. No internal connection. Leave open circuit. Xtal: The output of the on-chip clock oscillator inverter. No internal connection. Leave open circuit. Xtal/Clock: The input to the clock oscillator inverter. A 3.579545MHz Xtal or externally derived clock should be connected here (see Figure 2). V SS : Negative supply rail (GND). Hold: An input to control the Output Latch condition; employed in combination with the Data Change output to facilitate, if required, Interrupt and/or handshake operations with a µProcessor. With Hold placed “Low”, with a tone input, the Data Change output will be held “High” at the next data change, and the current output code is locked in the Output Latches regardless of any changes to the input signal. The output code remains as held until this input is returned “High” (see Figure 3). Whilst this input is “High” the output data, Q0 - Q3, cycles normally with the input audio. This pin has an internal 1.0MΩ pullup resistor. PURS: Power-Up ReSet. To reset internal circuitry at power-up; a logic “1” level is required at this pin for a duration of at least 2.5mS after the Xtal/Clock input and full V DD levels are applied. The component configuration shown in Figure 2 is recommended; for slow-rising power supplies the time constant of components should be increased accordingly. IRQ: Interrupt Request. An output for µProcessor operation; normally “High” this output is latched “Low” when an internal data change occurs if the Chip Select input is “High”. This output is reset (“High”) the when Chip Select line is taken “Low”. To permit “wire-OR” connection with other peripherals, this output has a low-impedance when “Low” and a high-impedance when “High”. CS: Chip Select- A controlling function. When held “High” the Data Outputs Q0, Q1, Q2 and Q3 and the Data Change output are disabled. When taken “Low” the Data Outputs Q0, Q1, Q2 and Q3 and the Data Change output are enabled; the Interrupt Request (IRQ) is reset (“High”) when CS is taken “Low”. See Figures 3 and 4. Data Change: A positive-going pulse is generated at this output when the data changes (Tone or N OTONE ). New tone-data is presented to the Q0, Q1, Q2 and Q3 Data Outputs if the Hold input is set “High”. This is a tri-state output.

Application Information

SIGNAL INCOMPOSITE SIGNAL IN A HEX Code Output representing the decoded tone frequency See Table 1 DATA OUTPUTS VSS C 5 XTAL HOLD IRQ CS Fig.2 Recommended External Components Band Edges (Hz) Nominal Hex Output Code Lower Upper Centre Character Q3 Q2 Q1 Q0 Edge Edge Freq. 0 0000 3 6 4 3 8 6 375 1 0001 4 8 8 5 2 0 500 2 0010 5 2 0 5 8 0 550 3 0011 5 8 0 6 1 8 600 4 0100 3 8 6 4 1 2 400 5 0101 4 1 2 4 3 6 425 6 0110 4 3 6 4 6 3 450 7 0111 4 6 3 4 8 7 475 8 1000 9 0 0 1008 950 9 1001 1273 1325 1300 A 1010 1350 1455 1400 B 1011 1750 1855 1800 C 1100 2062 2140 2100 D 1101 frequency not guaranteed E 1110 frequency not guaranteed F 1111 N OTONE Table 1 Tone Decode Frequencies Timing Information With CS Low - Figure 3. After initial power-up and the Hold input inactive (High), as frequencies are input, with the Data Change output as an active (High) indicator, the data is presented at the Data Outputs. If/when the Hold input is placed active (Low), the data at the Data Outputs is frozen and the Data Change output held High at its next active excursion - until the Hold input is returned High. With the Hold input held High - Figure 4. As frequencies are input a correct decode will produce an active (Low) interrupt level. This interrupt (IRQ) is serviced and reset by an active (Low) CS input. Note the ‘valid data’ period at the Data Outputs. Component Value R 1 1.0MΩ R 2 1.0MΩ C 1 47.0nF C 2 4.7nF C 3 33.0pF C 4 33.0pF C 5 1.0µF X1 3.579545MHz Tolerances R = ±10% C = ±20%

Tone 1 Tone 2 Tone 3 Tone ’N’ ’N’ HOLD tPURS PURS tNT tDC HOLDt NORMt PULt VDD SIGNAL IN OUTPUTS Q0 - Q3 DATA OUT Q0 - Q3 (INTERNAL) DATA CHANGE IRQ CS NOTONE TRI-STATE TRI-STATE VALID DATA (READ DATA) VALID DATA (READ DATA) Tone 1 RIRQt IRt ACSt HIZt EF 1 tPURS PURS Fig.4 Timing with the HOLD Input Held “High”; CS and IRQ are used Fig.3 Timing with the Chip Select Input Held “Low”; CS and IRQ are not used

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3 to 7.0V Input voltage at any pin (ref VSS = 0V) -0.3 to (V DD + 0.3V) Sink/source current (supply pins) +/- 30mA (other pins) +/- 20mA Total device dissipation @ TAMB 25°C 800mW Max. Derating 10mW/°C Storage temperature range:FX623P -40°C to +85°C (plastic) Supply Voltage (VDD ) 3.0 5.5 V at 25°C All device characteristics are measured under the following conditions unless otherwise specified: VDD = 3.3V, TOP = -40 to +85 °C. Audio Level 0dB ref: = 775mVrms. Xtal/Clock Frequency = 3.579545MHz Characteristics See Note Min. Typ. Max. Unit Static Values Supply Current - 0.6 1.0 mA Input Logic “1” 0.7 - - %V DD Input Logic “0” - - 0.3 %V DD Output Logic “1” 0.8 - - %V DD Output Logic “0” - - 0.2 %V DD Impedance CS and PURS Input 10.0 - - M Ω Hold Input 1 0.5 - - M Ω Signal Input 0.1 - - M Ω IRQ Output (logic “1”) - 30.0 100 k Ω IRQ Output (logic “0”) - 175 500 Ω Q0 - Q3 & Data-Change Outputs (logic “1”) - 0.7 2.0 k Ω Q0 - Q3 & Data-Change Outputs (logic “0”) - 175 500 Ω Q0 - Q3 & Data-Change Outputs (high Z) 1.0 - - M Ω Dynamic Values Signal Input Range 2, 5 35.0 1,166 mVrms Decode Bandedge Tolerance 3 -1.0 - 1.0 % Xtal Inverter Voltage Gain 20.0 - - V/V Input Impedance 10.0 - - M Ω Output Impedance - - 160 k Ω Decoder Timing - Figures 3 and 4 Power Up Reset Time t PURS 2.5 - - ms Data 'E' Time t DE 31.0 - - ms N OTONE to Tone Response Time tRESP 4 - 27.0 50.0 ms Tone to NOTONE Response Time t NT 4 - - 60.0 ms Data to Data-Change Pulse Time tDC 0.625 - 1.15 ms Data-Change Pulse Width t PUL - 1.25 - ms Hold to Data-Change Rise Time tHOLD 63.0 - - µs HOLD to Data-Change Fall Time tNORM - - 150 µs IRQ Tone Response Time t RIRQ - 29.0 52.0 ms IRQ Reset Time t IR - - 250 ns Data Access Time t ACS - - 250 ns CS High to Output Tri-State Time tHIZ - - 100 ns Notes 1. This pin has an on-chip 1.0MΩ pullup resistor. 2. An a.c. coupled sine or squarewave. 3. See Table 1, Tone Decode Frequencies. 4. Delay between the change of input (Tone/NOTONE ) and the change at the Q0 - Q3 outputs. 5. The signal input maximum value is determined by the formula VDD /2.83.

The FX623 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage. CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.

Ordering Information

FX623P 16-pin plastic DIL (P3) Package Outlines The FX623 is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. NOT TO SCALE Max. Body Length 20.57mm Max. Body Width 6.60mm FX623P 16-pin plastic DIL (P3)