FX214

FX214 CMLMICRO | Alldatasheet

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Technical content

Publication D/214/2 November 1987

7 Provisional Issue

© *Variable Split-Band Frequency © Powersave Facility Inversion Voice Scrambler © Mobile or Cellular Radio Applications © 32 Programmable Split Frequencies » Fixed or Rolling Code Applications © CTCSS HP Filter © Serial/Parallel Load Options: © High Recovered Audio Quality FX214 (Serial), FX224 (Parallel), © Low-Power 5 Volt CMOS FX234 (Serial and Parallel) © Half-Duplex Switching © DIL and SMD Package Options tl AROUND (PSi/ THROUGH. aD /TATCH XTAL/CLOCK ENABLE/MAU =| pa OTE Lean SCRAMBLE + Lean SORRTBTE | mu TRuseniPam ef Ft tre s = || ee ee A, et —“e | a =e aaa — ae oy > FX214 So A per ont ges FX 224 chy Oe ba = Bye FX234 mute 3 STN Te BIAS BAS. iy BIAS . 02 ae r= 2 ™ BIAS = ee as ‘BIAS, Bus Fig. 1 Functional Block Diagram Brief Description The FX214, 224 and 234 are a family of Low-Power combinations are externally programmable using a CMOS LSI devices designed as Variable Split-Band 5-bit code, this code can be either fixed or varying (VSB) Voice Scramblers. (Rolling), for greater security. The device uses separate Rx and Tx paths which are “Sync/Speech Mute’, ‘Powersave’, ‘Clear’ and ‘Audio switched for Half-Duplex operation. To prevent Bypass’ facilities are controlled via external interference from sub-audio products, an on-chip commands. Continuous Tone Controlled Squelch System (CTCSS) Timing and filter clocks are derived internally from an Highpass Filter is automatically switched to the input on-chip 1MHz oscillator requiring only an external in Rx, and to the output in Tx. 1MHz Xtal or clock pulse input. Scrambling is achieved by splitting the input voice This device demonstrates high baseband and carrier frequencies into upper and lower frequency bands frequency rejection with good ‘recovered audio’ using switched capacitor filters, modulating each band quality. Serial or Parallel command loading functions with selected carrier frequencies to ‘frequency invert’ are available in both DIL and SMD packages with a the bands, then summing the output. Dual’ load device in a 28-lead plastic leaded chip A total of 32 different split-point and carrier frequency carrier, |

fm = "| FX | FX | FX | FX | FX 2144 | 214LG | 224J | 224LG]234LH 7 1 1 1 1 Xtal/Clock: Input to the clock oscillator inverter. A 1MHz Xtal input or externally derived 1MHz clock is injected here. See Figure 2. | 8 2 2 2 2 | Xtal: Output of the clock oscillator inverter. 9 3 3 Serial Data Input: This pin is used, on devices wired in the serial loading | mode, to input an 8-bit word representing the digital control functions. This word is loaded using the serial data clock and is input in the following sequence:— ENABLE; CLEAR; Rx/Tx; Ap; Ay; A; Ag; Ag, with the Load/Latch being operated on completion, See Timing Diagram Figure 7. : ; a Pe Programming Inputs: In parallel mode, these are the 5 digital inputs 5 5 6 re whose code defines the split point frequency and the High and Low 6 6 7 i band carrier frequencies. Each of the 5 input pins have a 1MQ internal 1 pullup resistor. Table 2 contains programming information. 7 7 8 Ao 8 8 9 Rx/Tx: This digital input selects the Receive or Transmit paths and configures Upperband and Lowerband filter bandwidths whilst setting the CTCSS High Pass Filter position in the signal path. See Table 1 and Figures 5 and 6. 1MQ internal pullup resistor (Rx). 13 8 10 —_Parailel/Serial: This pin defines the loading mode of the digital function “a | inputs. In the FX224J and FX224LG parallel load devices this pin has no | external connections. For FX214J and FX214LG serial load devices this pin must be externally connected to Vg. For the FX234LH, the dual loading | device, this pin must be externally connected to Vgg for the serial mode. This pin, on all devices has a 1MQ internal pullup resistor (Parallel). See | Figure 2(a), (b), (c). 9 9 | 11 | Clear/Scramble: This digital input puts the device into ‘Clear’ or ‘Frequency | Inversion’ mode by controlling the application of carrier frequency to the Upper and Lower band Balanced Modulators. In ‘Scramble’ the Balanced | Modulator carrier frequency values are selected by the split point address | Ap—Ag (Table 2). In ‘Clear’ carriers are turned off and the Balanced | Modulators are bypassed internally, the Lower band signal is not added to to the output signal. 1MQ internal pullup resistor (Clear). 10 | 10 | 12 _ Enable/Mute: This digital function is used to disable Receive or Transmit signal paths for rolling code synchronization whilst maintaining bias conditions. To allow synchronizing information to be transmitted, or receiver audio output to be removed during sync periods, a logic ‘1’ will enable, a logic ‘0’ will disable the selected (Rx/Tx) audio path. See Table 1. 1MQ internal pullup resistor (Enable). ~ 14 10 13 Serial Clock Input: This is the externally applied data clock frequency used | to shift input data along on devices wired in the Serial loading mode. One full data clock cycle is required to shift one data bit completely into the register. See Timing Diagram Figure 7. This pin has a 1MQ internal pullup resistor. 15 nN u 1 14 Load/Latch: This pin controls the loading of the 8 digital function inputs; ENABLE; CLEAR; Rx/Tx; Ag—A, into the internal register. When this pin is at logic ‘1’ all 8 inputs are transparent and new data acts directly. For controlled changing of parameters in the parallel mode Load/Latch must be kept at logic ‘0’ whilst a new function is loaded, then Load/Latch strobed 0-1-0 to latch the inputs in. For serial loading the serial data should be loaded with Load/Latch at logic ‘0’ and then Load/Latch strobed 0-1-0 on completion of data loading. 1MQ internal pullup resistor (Load). See Figure 7. NOTE: Serial and/or parallel loading functions are dependant upon device type (see pages 9 and 10). 16 12 12 12 15 Around (Powersave)/Through: This digital input is used, when at logic ‘1’ to put the device into the Powersave condition where all parts of the device except the 1MHz oscillator circuits are shut down, and signal input and output lines made open circuit, free of all bias. This allows signal paths to be | routed externally around the device, whilst reducing current consumption. A logic ‘0’ at this input enables the device to work normally as shown in Table ki 1MQ internal pullup resistor (Around). |

214J | 214LG| 224J | 224LG/234LH 7 13 13 13 16 Vgg: Negative Supply (GND). 18 14 14 14 7 Internal Connection: This pin is internally connected, leave open circuit. 19 15 15 15 18 Rx Output: This is the processed received audio signal output. This pin is held at a D.C. ‘bias’ voltage for all functions except Powersave. This buffered output is driven by the Summer circuit in the Rx mode. Signal paths and bias levels are detailed in Table 1 and Figure 6. 20 16 16 16 19 Tx Output: This is the processed audio output for the transmission channel. This pin is held at a D.C. ‘bias’ for all functions except Powersave. This summed and buffered signal is passed through the CTCSS High Pass Filter to the output pin in the Tx mode. Signal paths and bias levels are detailed in Table 1 and Figure 5. 21 7 7 7 20 Vaias: Normally at Vpp/2 this pin requires an external decoupling capacitor ~ Cz, to Vsg 22 18 18 18 21 Rx Input: This is the analogue received audio signal input. This pin is held at a D.C. ‘bias’ voltage by a 300k2 on-chip bias resistor which is selected for all functions except Powersave, and therefore requires to be connected to external circuitry by a capacitor, C3. See Figure 2. This input is routed through the CTCSS High Pass Filter in Rx mode to remove sub audio frequencies from the voice band. Signal paths and bias levels are detailed in Table 1 and Figure 6. 1 19 19 19 22 | Highband Filter Output: The output of the Input Filter of the Upperband arm. The Rx/Tx function sets the lowpass filter at 3400Hz or 2700Hz respectively. This output must be connected to the Highband Balanced Modulator input via capacitor C,. See Figure 2. 2 20 20 20 24 Highband Balanced Modulator Input: The input to the Balanced Modulator of the Upperband arm. This input must be connected to the Highband Filter Output via capacitor C,. (a) 3 21 21 21 25 Lowband Balanced Modulator Input: The input to the Balanced Modulator of the Lowerband arm. This input must be connected to the Lowband Filter | Output with capacitor Cg. See Figure 2. 4 22 22 22 26 ~=—- Tx Input: This is the analogue ‘Clear’ audio input for the VSB scrambler. | This pin is held at a D.C. ‘bias’ voltage by a 300k2 on-chip bias resistor which is selected for all functions except Powersave, and therefore requires to be connected to external circuitry by a capacitor, C,. See Figure 2. This | input, in the Tx mode, is connected to Upper and Lowerband input filters, signal paths and bias levels are detailed in Table 1 and Figure 5. 5 23 23 23 27 | Lowband Filter Output: The output of the Input Filter of the Lowerband arm, the Rx/Tx function determines which filter is used (Filter 1 or 2). See Figures 5 and 6. This output must be connected to the Lowband Balanced Modulator Input via capacitor Cg. See Figure 2. 6 24 | 24 | 24 | 28 (Vpp: A single +5V supply is required. | 2 | 7.9 23 | Not Connected |

Fig. 2(a) Serial Load Options y oo Ss (a Not Connected Lae am ont Veus FX214LG 4,5,6,7,9, 14 Tx OUT FX224J) 14 & Ts? 3 (21) (16) 20 FX224LG 14" TeIN Lap (22) (15) 9 AXOUT FX234LH 17", 23 5 (23) (14) re AS (cr “Internally connected, do not 6 (24), fase (vay 17 a connect to. XTAL/CLOCK mye 12) 16 beg AROUND THROUGH XTAL 8 (2) a 15 ae LATCH SERIAL 9 (3) (10) 14 SERIAL CLOCK IN DATAIN PAR/SER nc—f10 (8) 13 ee n/c W 12 Nic Ves. Fig. 2(b) Parallel Load Options Yoo XTAL/CLOCK a XTAL/CLOCK 1 24 —- Sx, | XTAL 2 23 Cg c 7 Ay 3 2 Jt in As 4 2 = — = PROGRAMMING Cs R, XTAL INPUTS. Aa 5 2 ¢ ¢ os A, 6 -FX224— ig c 2 1 — Ao 7 DSRS is |x nv Axi Tx 8 17 Vas Vss CLEAR/SCRAMBLE Tx OUT = 9 16 oe ENABLE/MUTE Fa a Recommended Xtal Circuitry LOAD/TATCH i wa fC Xtal circuitry shown is in accordance with aROUND/ THROUGH |. be CML Application Note D/XT/1 April '86. Ves C. Vss Fig. 2(c) Parallel/ Serial Load Option ¥ Component References LOWER UPPER a BAN! BAND a | [ewe | we | Veins c Ge c c R, iM Tx OUT a, Selectable c 33p Fo 24 3B 2 21 20 19, Rx OUT & pad : fn is =| 7 fe 1s 28 16}— & ie XTAL/CLOCK te FX234LH 15 AROUND THROUGH q 10, XTAL 2 14 LOAD/LATCH ca x MHz SERIAL DATA IN 3 13] SERIAL CLOCK IN| ni a 12 beg ENABLE/ MUTE 66 7891011 ot CLEAR/SCRAMBLE PROGRAMMING § As INPUTS: A =~, Tolerance Resistors + 10% * PARALLEL/SERIAL_o Capacitors + 20% | ie ante Cs and Cg are coupling capacitors Ay between filter outputs and | balanced modulator inputs. Vss | Fig. 2. External Component Connections

Application Information

This device can be used in ‘Scramble’ (frequency During the Clear speech function both Lower and inversion) or ‘Clear’ speech modes. The inversion Upperband filter arms are selected (figures 5 or 6), the frequencies, when selected are controlled by the ROM carrier frequencies are turned off and the balanced address code (table 2). Keeping the code in one state modulators are bypassed internally. The Low band (fixed) is the simplest form of operation. A more audio is removed from the output signal prior to secure method is to continually change the ROM summation. address code (rolling code) therefore changing split- point and carrier frequencies. This method requires some external form of code change generation with Enable/Mute synchronization between transmit and receive stations. To enable code synchronization to be transmitted the Many variations of code sequence are possible. speech output can be interrupted with the Enable/Mute function. A logic ‘0’ will isolate the whole device whilst leaving the audio input and output pins at bias level. See Table 1. The recommended external component connections Powersave are shown in figure 2. In the Scramble mode, Split- When the Around/Through function is at a logic ‘1’ point and Low and High band carrier frequencies (F.1, the device is in the powersave condition. Audio F.2) are selected and set in accordance with the ROM signals may be hardwired around the device normally address code present at the inputs Ap to Ay, See as the input and output pins are open circuit. See Table 2. Table 1.

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3V to 7.0V Input voltage at any pin (ref Ms = OV) —0.3V to (yp + 0.3V) ‘Sink/source current (supply pins) + 30mA (other pins) + 20mA Total device dissipation @ 25°C 800mW Max. Derating 10mW/°C Operating temperature range: FX214J/224J —30°C to +85°C (Ceramic) FX214LG/224LG/234LH —30°C to +70°C (Plastic) Storage temperature range: FX214J/224) —55°C to + 125°C (Ceramic) FX214LG/224LG/234LH —40°C to +85°C (Plastic) Operating Limits All characteristics measured using the following parameters unless otherwise specified: Vop = 5:0V, Tam = 25°C, Fy = 1.0MHz, Audio Level Ref: 0dB = 775mVrms. Characteristics See Note Min. Typ. Max. Unit ———— a Static Values Supply voltage 45 5 5.5 v ‘Supply current (Enabled) - 8 _ mA Supply current (Powersave) - 1.2 - mA Analogue Input impedances Tx/Rx Input (Enabled) - 100 - =- kQ Tx/Rx Input (Powersave) 1 - = MQ Balanced Modulator - 40 - kQ Analogue Output impedances Rx Output (Tx Mode) - 100 - kQ Rx Output (Rx Mode) = - 2 kQ Rx Output (Powersave) 1 = = MQ Tx Output (Tx Mode) - = 2 kQ Tx Output (Rx Mode) = 100 bod kQ Tx Output (Powersave) if - = MQ Input LPF - - 4 kQ Digital Values Digital Input Impedance 100 - - kQ Dynamic Values ~ Input Logic ‘1’ 3.5 - — v Input Logic ‘0° = = 1.5 Vv Xtal/Clock Frequency = 1 = MHz Analogue Input Level ~18 — +6 «dB Carrier Breakthrough 1 = ~5 = dB Baseband Breakthrough 1,20r3 - -33 - dB Filter Clock Breakthrough 1,20r3 =_ —50 = dB Output Noise 14 = -45 — @B Passband Characteristics Clear Mode 7 Passband Gain - oO - dB Output Lower 3dB Point (Rx or Tx) = 300 - Hz Output Upper 3dB Point (Rx or Tx) - 3400 - Hz Scramble-Descramble 5 Received Signal Passband Gain 6 = 0 =- dB Received Signal Lower 3dB Point - 400 - Hz Received Signal Upper 3dB Point =- 2700 - Hz Transmitted Signal Lower 3dB Point = 300 - Hz Transmitted Signal Upper 3dB Point - 3400 - Hz CTCSS (Highpass Filter) ~3dB Point = 300 - Hz Passband Gain - i) - dB Stopband Attenuation at f>250 Hz - 40 - dB

Electrical Specifications (continued) eae Le Characteristics See Note Min. Typ. Max. Unit ei et SS Ri sheet ld Timing (Figure 7) Serial Mode Enable Set Up (teyyc) 250 = - rs Serial Clock ‘High’ Pulse Widi\\ ftyy,,) 250 = — ons Serial Clock ‘Low’ Pulse Width (ta 1 250 = — ns Data Set Up Time (t<) 150 = = ns Data Hold Time (ty,,c) 50 = — ns Load/Latch Set Up'Fime (t,,) 250 = — ons Load/Latch Pulse Width (t,; wy) 150 - — ns Data Set Up Time (ty<p) 150 = - ns Data Hold Time (top) 20 ~ — ns ee ee ee Notes: 1. Measured at the output of a single device. 2 Tx Mode. 3. Rx Mode. 5. Measured at the output of a receiving device in a scrambler-descrambler system with a transmission channel having a flat amplitude response and a bandwidth of 300Hz to 3400Hz and measured relative to the input signal at the transmitting device. ~~ 6. Excluding split point + 150Hz. 7. Measured at the Rx or Tx output pin of a single device. Serial Loading PARALLEL/SERIAL \\ & $$ — eo He trv ‘SERIAL 2 ‘ ‘ " . ‘ ; { y ka— ths — y Sxipor KXXKXX tet’ Xt) : patnwpur XXX) } Casto _ ENABLE CLEAR Rx ‘ zs m Ce) ': ' * ' ' Loap/TATCH ty Parallel Loading Th LOAD/LATCH ” boo Me hoy PARALLEL { x DATA INPUTS NOTE: For ‘Serial Load’ devices the data loading sequence is: — Enable—Clear—Rx/Tx—A,—A,—A,—Ay—Ag Fig. 7 Loading Timing Diagram

Package Outlines (continued Fig. 10 FX214LG and FX224LG 24-pin Package Fig. 11 FX234LH 28-lead Package Ben one F , ; c oll ¥ * feet rd : . NOTE: All dimensions in mm. Angles in degrees. f “i , =o LA a .. B | Datum & Symmetry Crnnents i tb Be Me HOTA dans ven Aegis cope Yo F We ‘a7 ~ aed | : r re ia = ne Ne oe tf ge $e 4 & } Toca i H Fa 5 iz ate x Bree wir we 7 Sa re oe Ly on Serial or Parallel Load Option Serial and Parallel Load Option

Ordering Information

FX214J =. 22-pin cerdip DIL Serial Load Only FX224J =. 24-pin cerdip DIL Parallel Load Only FX214LG | pean quad plastic encapsulated — Serial Load Only (FX214LG) FX224LG | bent and cropped Parallel Load Only (FX224LG) ba] 4 aul wo ome foeen Serial and Parallel Load CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry,