FX601A

FX601A CMLMICRO | Alldatasheet

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PRODUCT INFORMATION - For Information Only - FX601A Tone Operated Monostable Timer Publication D/601A/2 August 1983 Choice of high sensitivity or High noise immunity on Schmitt inputs Schmitt input Fast response time Wide choice of VDD operating range Operation over a wide range of Operational parameters set by frequencies external components = VESUPPLY (vOD) TS | | | l rer | > Ls) Lo | Sacer ~ ; | ‘ ova ; i D : a 5 | FX601A commune | 2 PAR. Bay | ' | | oureur | > 1 + VE SUPPLY (GROUND) Fig. 1 FX601A Internal Block Diagram The FX601A is constructed in monolithic timer, where the integral output switch is microcircuit form using PMOS technology. It turned ON for an accurately defined time is designed for use as a tone decoder in following receipt of an inband trigger tone. remote control, instrumentation, automation, This timed period is externally adjustable communications and telemetry systems, from a few milliseconds to one hour at duty where specific tone frequencies are used to cycles of up to 90%. The trigger tone control remote switching functions, such as frequency, bandwidth and output monostable SPM (Subscriber's Private Metering). period are externally set using simple RC The FX601A is a tone triggered monostable networks.

(See Fig. 1 Block Diagram. Fig. 7 Pin Data and External Component Connections) NOTE: External capacitors are to be low-leakage type and resistors are to be high-stability type. In the following formulae, the resistor values are in MQ. and capacitor values are in uF. 1. SET f’b Dual Monostable is set to Lower Bandedge (f'b) which is determined by fib =_1 (Hz) where 0.69 is a design constant K, recommended

0.69 R1C1

minimum values of *R1 = 360kQ, C1 = 470 pF (See Fig. 2). * For R1 values less than 360kQ, refer to Fig. 3 for ‘K’ factor 2. SET MONOSTABLE Monostable Output period at pin 3 is set by a network R2 and C2 connected to this PERIOD pin as shown in Fig. 7. 3. MONOSTABLE An ‘Open drain’ output which requires a load resistor between this pin and VDD. OUTPUT Monostable Output period (Tm) is determined by components attached to pin 2. Tm = 0.69 R2C2, where 0.69 is a design constant K, recommended minimum values of R2 = 360kQ and C2 = 470 pF. (See Fig. 4). 4. SCHMITT INPUT High Impedance Input with a logic ‘0’ of 33% of VDD and a logic ‘1’ of 66% of VDD. This input is a.c. coupled and biased to a 50% VDD by means of a potential divider using two 1MQ resistors. (See Figs. 7 and 5). 5. CONTROL INPUT Selects either Low-Level Input (pin 7) when this pin is open circuit or negative , (logic ‘1') or Schmitt Input (pin 4) when positive (logic ‘0’). 6. +VE SUPPLY The device uses negative logic (i.e. logic ‘1’ = negative and logic ‘0’ (GROUND) = positive). Either positive or negative supplies may be connected to earth. The can of the device is internally connected to the positive supply pin. 7. SIGNAL INPUT A high sensitivity signal input. Low-level signals should be a.c. (Low-Level Input) coupled. High-level pulse signals > (—6V) can be directly coupled, The signal input can be sinewave, squarewave or pulse (See Figs. 7 and 6). 8. —VE SUPPLY (VDD) 9. REF. LO External network RK1, RK2 and RK3 connected as shown in Fig. 7 to set the 10. REF. HI required bandwidth. The bandwidth is determined by the ratio of RK2 to RK1. _ RK1 x BW(%) RK2 = 1.6 x 100 where RK1 = 10kQ2, RK3 = (RK1 + RK2) and 1.6 is a constant factor. The tolerance on this factor is + 15% when measured at a bandwidth of 10%. Tone Reject f'a = Upper Bandedge Fig.2. FX601A Typical Tone idth Channel Bandwi rt Tone Accep| f'b = Lower Bandedge Tone Reject -

Typical Performance Curves Fig. 3 FX601A Typical E Sang ee el R1 (kQ) Fig. 4 FX601A i t { H Output Switching Monostable, _OFF_beTs9| ‘ON OFF ited ON Waveform Switch Output Tm Ts _ typically 6 cycles of Input Tone. Tm variable depending on R2 C2 values. ie See ee eee Ps de ee a EU ee HE Se a eer ee : eee aE . it Be fier ccisssricicsanitettin tists ratte SrtA HEIETI| an ft tea Schmitt Input Thresholds a5 See ee ee asa Hea aqusinumercwaraeiiie| A eee a4 oe Oy Sn ep i EES, ye ea etre NA ESE ee

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—10 11 =12 = = at Supply Voltage (V) ene aE a a Fat Papier stipes a ee es A a Et =e , 2 eee a as saeaee a 0° ensitvty Low-Level Input 4 a ee eat A See

0 Tt He ee i

Co tirt de aes rt ae et Bru Hi —10 -i 12 =13 =14 -15 Supply Voltage (V)

Max. voltage between any pin and + VE supply pin —20V & +0.3V. Max. output switch load current -—10mA Max. device dissipation @ 25°C ambient temperature 400mW Operating temperature range —30°C to + 85°C Storage temperature range —55°C to + 125°C Characteristics (Ambient temperature = 20°C, VDD = —-12.0V, operating frequencies 10Hz to 3kHz unless specified) Symbol Parameter Conditions & Notes Min. Typ. Max. Unit VDD Supply voltage Operating range —10.0 -12.0 - 15.0 Vv IDD Supply current 3.5 6 mA Sensitivity Low Level Input mV (Pin 7) 50 20 pk-pk Schmitt Input (Pin 4) Low threshold -3.6 -4.0 -4.4 Vv _ (Pin 4) High threshold —7.6 —8.0 —8.4 Vv Ts Response Time 5 6 7 Cycle Vin Schmitt input leakage current 100 nA (Pin 4) R’in Input Impedance 35 70 110 kQ (Pin 7) R’on Output ON 400 1k Q Resistance Control input -2.5 —3.0 -3.5 Vv logic threshold K Constant K R1 and R2 >360kQ 0.66 0.69 0.72 ee Fig. 7 Pin Data External Component Package Outline Connections FX601A (Package Type TO — 100) -- Pin No. Connection | 1 Set fb | . 2 Set Monostable Period —_-vesurv.voo) : wr 7 .

3 Monostable Output t |

4 Schmitt Input [Jana ry =

5 Control Input er wu :

6 +VE Supply (Ground) va a{| (}r. 7 Low Level Input [Jove ( i . 8 —VE Supply (VDD) ser | 9 Reference LO ee Ne . I 35

10 Reference HI SIGNAL INPUT as ourpur é ie a a

cage | | NRA | on i Be - INPUT, cr OF : Handling Precautions wo] [Je« RY 1 The FX601A is a PMOS integrated as li oa circuit which includes input 7 tM protection. However, precautions ‘+ VE SUPPLY (GROUND) 10 Cee 4 should be taken to prevent eee a static discharge which can cause + bes damage. . se View from pinside CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change said circuitry.