FX589

FX589 CMLMICRO | Alldatasheet

Document overview

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Technical content

Features

Full-Duplex Gaussian Minimum Shift Keying (GMSK) Operating from 3 Volts to 5.5 Volts Data Rates 4kb/s to 64kb/s Selectable BT (0.3 or 0.5) Low-Current Analogue/Digital Non-DSP Solution Meets RCR STD-18

Applications

Low-Power Wireless Data Link for PCs, Laptops and Printers Point-Of-Sale Terminals Wireless Bar-Code Readers and Stock Controllers Brief Description The FX589 is a single-chip modem employing Gaussian Minimum Shift Keying (GMSK) modulation. Data rates of 4kb/s to 64kb/s and the choice of BT to 0.3 or 0.5 are pin-programmable functions to suit radio data channel bandwidth requirements. The Rx and Tx digital data interfaces are bit-serial and synchronised to Rx and Tx data clocks generated by the modem. Separate Rx and Tx Powersave/Enable inputs allow for full- or half-duplex operation. Rx input levels can be set by a suitable ac and dc level adjusting circuit built, with external components, around an on-chip Rx input amplifier. FX589 Tx PS Rx PS BT Tx DATA ClkDIVA PLLacq RxDCacq Rx SIGNAL IN Rx FEEDBACK ClkDIVB XTAL/CLOCK Tx ENABLE XTAL VDD VBIASVBIAS VBIAS VBIAS VSS RxHold DOC1 Rx CLOCK Tx CLOCK Tx OUT Rx DATA Rx S/N DOC2 DATA RETIME LEVEL SHIFT Tx FILTER CLOCK DIVIDER Rx CIRCUIT CONTROL Rx FILTER Rx LEVEL MEASURE Rx CLOCK EXTRACT Rx S/N DETECTION Rx DATA EXTRACT Low-Voltage/High-Speed GMSK Modem Fig.1 Functional Block Diagram Acquisition, lock and hold of Rx data signals is made easier and faster by the use of Rx Control Inputs to clamp, detect and/or hold input data levels and can be set by the system µProcessor as required. Indication is available, from the Rx S/N output, as to the quality of the received signal. The FX589 design features a low-current analogue/digital ASIC process offering significantly lower current consumption than DSP technology. For data rates up to 32kb/s the FX589 draws typically 1.5mA at 3.0 volts V DD and for data rates up to 64kb/s at 5.0 volts, typically 4.0mA. This low-power CMOS microcircuit is available in both 24-pin plastic DIL and Small Outline (SOIC and SSOP) packages. Publication D/589/7 January 1998

Xtal: The output of the on-chip clock oscillator. Xtal/Clock: The input to the on-chip Xtal oscillator. A Xtal, or externally derived clock (fXTAL ) pulse input should be connected here. If an externally generated clock is to be used, it should be connected to this pin and the Xtal pin left unconnected. Note that operation of the FX589 without a suitable Xtal or clock input may cause device damage. ClkDivA: Two logic level inputs that control the internal clock divider and hence the transmit and receive data rate. See Table 1. ClkDivB: Rx Hold: A logic “0” applied to this input will ‘freeze’ the Clock Extraction and Level Measurement circuits unless they are in ‘acquire’ mode. RXDCacq: A logic “1” applied to this input will set the Rx Level Measurement circuitry to the ‘acquire’ mode. PLLacq: A logic “1” applied to this input will set the Rx Clock Extraction circuitry to ‘acquire’ mode (see Table 2). Rx PS: A logic “1” applied to this input will powersave all receive circuits except for “Rx Clock” output (which will continue at the set bit-rate) and cause the “Rx Data” and “Rx S/N” outputs to go to a logic “0”. V BIAS : The internal circuitry bias line, held at VDD /2, this pin must be decoupled to VSS by a capacitor mounted close to the pin. Rx Feedback: The output of the Rx Input Amplifier/the input to the Rx Filter. Rx Signal In: The input to Rx Input Amplifier. VSS : Negative supply rail. Signal ground.

Doc1: Connections to the Rx Level Measurement Circuitry. A capacitor should be connected from each pin to VSS . See Figure 2. Doc2: BT: A logic level to select the modem ‘BT’ (the ratio of the Tx Filter's -3dB frequency to the Bit- Rate). A logic “1” sets the modem to a BT of 0.5, a logic “0” to a BT of 0.3. Tx Out: The Tx signal output from the FX589 GMSK Modem. Tx Enable: A logic “1” applied to this input enables the transmit data path through the Tx Filter to the “Tx Out” pin. A logic “0” will put the “Tx Out” pin to VBIAS via a high impedance. Tx PS: A logic “1” applied to this input will powersave all transmit circuits except for the “Tx Clock”. Tx Data: The logic level input for the data to be transmitted. This data should be synchronous with the “Tx Clock”. Rx Data: A logic level output carrying the received data, synchronous with the “Rx Clock”. Rx Clock: A logic level clock output at the received data bit-rate. Tx Clock: A logic level clock output at the transmit-data rate. Rx S/N: A logic level output which may be used as an indication of the quality of the received signal. VDD : Positive supply rail. A single, stable power supply is required. Levels and voltages within this modem are dependent upon this supply. This pin should be decoupled to VSS by a capacitor mounted close to the pin.

Application Information

R 1 Note 1 ±5% R 2 1.0MΩ ±10% R 3 Note 2 ±10% R 4 100kΩ ±10% C 1 Note 1 ±10% C 2 Note 5 C 3 Note 5 C 4 100nF ±20% C 5 1.0µF ±20% C 6 22.0pF ±20% C 7 Note 4 C 8 Note 4 X1 Note 3 Fig.2 Recommended External Components 2. R3, R4 and C6 form the gain components for the Rx Input signal. R3 should be chosen as required by the signal input level. 3. The FX589 can operate correctly with Xtal/Clock frequencies of 1.0MHz to 8.2MHz (VDD = 5.0V) and 1.0MHz to 5.0MHz (VDD = 3.0V); see Table 1 for examples. Operation of this device without a Xtal or Clock input may cause device damage. 4. C7 and C8 should both be 15.0nF for a data rate of 8kb/s, and inversely proportional to the data rate for other data rates, e.g. 30.0nF at 4kb/s, 1.8nF at 64kb/s. 5. The value chosen for C2 and C3 (including stray capacitances) should be suitable for the applied VDD and the frequency of X1. As a guide: C2 = C3 = 33.0pF at 1.0MHz falling to 18pF at the maximum frequency. At 3 volts, C2 = C3 = 33.0pF falling to 18pF at 5.0MHz. The equivalent series resistance of X1 should be less than 2.0kΩ falling to 150Ω at the maximum frequency. Stray capacitance on the Xtal/clock circuit pins must be minimised. Notes 1. The RC network formed by R1 and C1 is required between the Tx Out pin and the input to the modulator. This network, which can form part of any dc level shifting and gain adjustment circuitry, forms an important part of the transmit signal filtering. The ground connection to the capacitor C 1 should be positioned to give maximum attenuation of high- frequency noise into the modulator. The component values should be chosen so that the product of the resistance (Ohms) and the capacitance Data Rate BT = 0.3 BT = 0.5 (b/s) R1 (k Ω ) C1 (pF) R1 (k Ω ) C1 (pF) 4000 120 680 120 470 4800 100 680 100 470 8000 91 470 120 220 9600 91 390 47 470 16000 47 470 91 150 19200 100 180 91 120 32000 47 220 47 150 38400* 47 180 47 120 64000* 56 100 51 68 * VDD >= 4.5V Note that in all cases, the value of R1 should be not less than 47.0kΩ and that the calculated value of C1 includes calculated parasitic (circuit) capacitances.

Fig.4 Minimum µController System Connections Note the device operation is not guaranteed above 64,000 bits/s or below 4,000 bits/s at the relevant supply voltage Table 1 Clock/Data Rates * VDD >= 4.5V A division ratio to facilitate data-rate setting is controlled by the logic level inputs on the ClkDivA/B pins, and is shown in Table 1 (below) - together with examples of how various ‘standard’ data-rates may be derived from common µP or Xtal frequencies. Data Rate = Xtal/Clock Frequency Division Ratio (ClkDivA/B) FX589 GMSK MODEM Rx CIRCUITS Tx CIRCUITS Rx DATA Rx CLOCK Tx DATA Tx CLOCK Tx OUT SIGNAL AND DC LEVEL ADJUSTMENT SIGNAL AND DC LEVEL ADJUSTMENT Rx SIGNAL IN Rx FEEDBACK Rx FREQUENCY DISCRIMINATOR RxD RxC TxD TxC µCONTROLLER or UART FREQUENCY MODULATOR Fig.3 External Signal Paths Clock Oscillator and Dividers The Tx and (nominal) Rx data rates are determined by division of the frequency present at the Xtal pin, which may be generated by the on-chip Xtal oscillator or be derived from an external source. Any Xtal/clock frequency in the range 1.0MHz to 5.0MHz (V DD = 3.0V) or 1.0MHz to 8.2MHz (VDD = 5.0V) may be employed, depending upon the desired data rate. Xtal/Clock Frequency (MHz) Inputs Division Ratio: ClkDiv ClkDiv Xtal Freq Data Rate (b/s) A B Data Rate 0 0 128 64000* 38400* 32000 19200 16000 0 1 256 32000 19200 16000 9600 8000 1 0 512 16000 9600 8000 4800 4000 1 1 1024 8000 4800 4000

Rx Signal Path Description The function of the Rx circuitry is to: 1. Set the incoming signal to a usable level. 2. Clean the signal by filtering. 3. Provide dc level thresholds for clock and data extraction. 4. Provide clock timing information for data extraction and external circuits. 5. Provide Rx data in a binary form. 6. Assess signal quality and provide Signal-to-Noise information. The output of the radio receiver's Frequency Discriminator should be fed to the FX589's Rx Filter via a suitable gain and dc level adjusting circuit. This gain circuit can be built, with external components, around the on-chip Rx Input Amplifier, with the gain set so that the signal level at the Rx Feedback pin is nominally 1 Volt peak-to-peak (for V DD = 5.0 V) centred around VBIAS when receiving a continuous “1111000011110... ” data pattern. Positive going signal excursions at Rx Feedback pin will produce a logic “0” at the Rx Data Output. Negative going excursions will produce a logic “1.” The received signal is fed through the lowpass Rx Filter, which has a -3dB corner frequency of 0.56 times the data bit-rate, before being applied to the Level Measure and Clock and Data extraction blocks. The Level Measuring block consists of two voltage detectors. One of which measures the amplitude of the ‘positive’ parts of the received signal; the other measures the amplitude of the ‘negative’ portions. External capacitors are used by these detectors, via the Doc 1/2 pins, to form voltage- ‘hold’ or ‘integrator’ circuits. Results of the two measurements are then processed to establish the optimum dc level decision- thresholds for the Clock and Data extraction, depending upon the Rx signal amplitude, BT and any dc offset present. Rx Circuit Control Modes The operating characteristics of the Rx Level Measurement and Clock Extraction circuits are controlled, as shown in Table 2, by logic level inputs applied to the ‘PLLacq,’ ‘Rx Hold’ and ‘RxDCacq’ pins to suit a particular application, or to cope with changing reception conditions. With reference to Figure 5, the Rx Mode Control diagram: In general, a data transmission will begin with a preamble of, for example, “1100110011001100,” to allow the receive modem to establish timing -and level-lock- as quickly as possible. After the Rx carrier has been detected, and during the time that the preamble is expected, the ‘RxDCacq’ and ‘PLLacq’ inputs should be switched from a logic “0 to 1” so that the Level Measuring and Clock Extraction modes are operated and sequenced as shown. The ‘Rx Hold’ input should normally be held at a logic “1” while data is being received, but may be driven to a logic “0” to freeze the Level Measuring and Clock Extraction circuits during a fade. If the fade lasts for less than 200 bit periods, normal operation can be resumed by returning the ‘Rx Hold’ input to a logic “1” at the end of the fade. For longer fades, it may be better to reset the Level Measuring circuits by placing the ‘RxDCacq’ to a logic “1” for 10 to 20 bit periods. ‘Rx Hold’ has no effect on the Level Measuring circuits while ‘RxDCacq’ is at a logic “1”, and has no effect on the PLL while ‘PLLacq’ is at a logic “1”. A logic “0” on ‘Rx Hold’ does not disable the ‘Rx Clock’ output, and the Rx Data Extraction and S/N Detector circuits will continue to operate. PREAMBLE DATA ’ACQUIRE’ Rx SIGNAL INPUT Rx CAR DET (RSSI) INPUT CLOCK EXTRACTION CCT MODE ’MEDIUM BW’ ’NARROW BW’

30 BITS

’CLAMP’ ’FAST PEAK DETECT’ ’AVERAGING PEAK DETECT’ RxDCacq PLLacq Rx LEVEL MEASURE MODE Fig.5 Rx Mode Control Diagram

“1” “1” to “0” “0” “0” RxDCacq “0” to “1” “1” “0” “0” Rx Hold X “1” “1” “0” Rx Hold X X “1” “0” PLL Action Acquire: Sets the PLL bandwidth wide enough to allow a lock to the received signal in less than 8 zero crossings. This mode will operate as long as PLLacq is a logic “1”. Medium Bandwidth: The correction applied to the extracted clock is limited to a maximum of ±1/16th bit-period for every two received zero-crossings. The PLL operates in this mode for a period of about 30 bits immediately following a “1” to “0” transition of the PLLacq input, provided that the Rx Hold input is a logic “1”. Narrow Bandwidth: The correction applied to the extracted clock is limited to a maximum of ±1/64th bit-period for every two received zero-crossings. The PLL operates in this mode whenever the Rx Hold Input is a logic “1” and PLLacq has been a logic “0” for at least 30 bit periods (after Medium Bandwidth operation for instance). Hold: The PLL feedback loop is broken, allowing the Rx Clock to freewheel during signal fade periods. Rx Level Measure Action Clamp: Operates for one bit-time after a “0” to “1” transition of the RxDCacq input. The external capacitors are rapidly charged towards a voltage mid-way between the received signal input level and V BIAS, with the charge time-constant being of the order of 0.5bit-time. Fast Peak Detect: The voltage detectors act as peak-detectors, one capacitor is used to capture the ‘positive’-going signal peaks of the Rx Filter output signal and the other capturing the ‘negative’-going peaks. The detectors operate in this mode whenever the RxDCacq input is at a logic “1,” except for the initial 1-bit Clamp-mode time. Averaging Peak Detect: Provides a slower but more accurate measurement of the signal peak amplitudes. Hold: The capacitor charging circuits are disabled so that the outputs of the voltage detectors remain substantially at the last readings (discharging very slowly [time-constant approx. 2,000bits] towards VBIAS). Table 2 PLL and Rx Level Measurement Operational Modes X = don't care Rx Clock Extraction Synchronized by a phased locked loop (PLL) circuit to zero-crossings of the incoming data, the ‘Rx Clock Extraction’ circuitry controls the ‘Rx Clock’ output. The Rx Clock is also used internally by the Data Extraction circuitry. The PLL parameters can be varied by the ‘Rx Circuit Control’ inputs PLLacq and Rx Hold to operate in one of four PLL modes as described in Table 2. Rx S/N Detection The ‘Rx S/N Detector’ system classifies the incoming zero-crossings as GOOD or BAD depending upon the time when each crossing actually occurs with respect to its expected time as determined by the Clock Extraction PLL. This information is then processed to provide a logic level output at the ‘Rx S/N’ pin; a ‘high’ level indicates a series of GOOD crossings, a ‘low‘ level indicates a BAD crossing. By averaging this output it is possible to derive a measure of the Signal-to-Noise-Ratio and hence the Bit-Error-Rate of the received signal. Rx Data Extraction The ‘Rx Data Extraction’ circuit decides whether each received bit is a “1” or “0” by sampling the output of the Rx Filter in the middle of each bit-period, and comparing the sampled voltage against a threshold derived from the ‘Level Measuring’ circuit. This threshold is varied on a bit-by-bit basis to compensate for intersymbol interference depending on the chosen BT. The extracted data is output from the ‘Rx Data’ pin, and should be sampled externally on the rising edge of the ‘Rx Clock.’

Bit Error Rate Performance 10-6 10-5 10-4 10-3 10-2 10-1 BER S/N (dB) [Noise Bandwidth = Bit Rate] BT = 1.0 (Theoretical) FX589 BT = 0.5 FX589 BT = 0.3 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Fig.6 Typical Bit-Error-Rate Performance 100 %H i g hT i m e S/N (dB) BT = 0.5 BT = 0.3 456789 1 0 1 1 1 2 1 3 Rx Signal Quality Figure 7 shows, diagrammatically, the effect of input Rx signal quality on the “Rx S/N” output. Fig.7 Typical Rx S/N Output ‘High-Time’ (%) vs Input S/N

Tx Signal Path Description The binary data applied to the ‘Tx Data’ input is re-timed within the chip on each rising edge of the ‘Tx Clock’ and then converted to a 1 Volt peak-to-peak binary signal centred about VBIAS (for VDD = 5.0 V). If the ‘Tx Enable’ input is ‘high,’ then this internal binary signal will be connected to the input of the lowpass Tx Filter, and the output of the filter connected to the ‘Tx Out’ pin. Tx Enable Tx Filter Input Tx Out Pin “1” (high) VDD /5Volt p-p Data Filtered Data “0” (low) V BIAS VBIAS via 500kΩ Fig.8 Rx and Tx Clock Data Timings A ‘low’ input to the ‘Tx Enable’ will connect the input of the Tx Filter to VBIAS, and disconnect the ‘Tx Out’ pin from the filter, connecting it instead to VBIAS through a high resistance (nominally 500kΩ ). The Tx Filter has a lowpass frequency response, which is approximately gaussian in shape as shown in Figure 9, to minimise amplitude and phase distortion of the binary signal while providing sufficient attenuation of the high frequency-components which would otherwise cause interference into adjacent radio channels. The actual filter bandwidth to be used in any particular application will be determined by the overall system requirements. The attenuation-vs-frequency response of the transmit filtering provided by the FX589 have been designed to meet the specifications for most GMSK modem systems, having a -3dB bandwidth switchable between 0.3 and 0.5 times the data bit-rate (BT). Note that an external RC network is required between the ‘Tx Out’ pin and the input to the Frequency Modulator (see Figures 2 and 3). This network, which can form part of any dc level shifting and gain adjustment circuitry, forms an important part of the transmit signal filtering, and the ground connection to the capacitor C 1 should be positioned to give maximum attenuation of high-frequency noise into the modulator. The signal at ‘Tx Out’ is centred around VBIAS, going positive for logic “1” (high) level inputs to the ‘Tx Data’ input and negative for logic “0” (low) inputs. When the transmit circuits are put into a ‘powersave’ mode (by a logic “1” to the ‘Tx PS’ pin) the output voltage of the Tx Filter will be undefined. When power is subsequently restored to the Tx Filter, its output will take several bit-times to settle. The ‘Tx Enable’ input can be used to prevent these abnormal voltages from appearing at the ‘Tx Out’ pin.

Fig.9 Tx Filter Response -70 -60 -50 -40 -30 -20 -10 0 1.0 2.0 Gain (dB) Frequency/Bitrate BT = 0.3 BT = 0.5 BT = 0.5 BT = 0.3 Fig.10 Typical Transmit Eye Patterns Fig.11 Tx Output Spectrum (Random Data) -70 -60 -50 -40 -30 -20 -10 0.01 0.1 1 10 Frequency/Bitrate Gain (dB) BT = 0.3 BT = 0.5

Radio Channel Requirements To achieve legal adjacent channel performance at high bit-rates, a radio with an accurate carrier frequency and an accurate modulation index will be required. To achieve optimum channel utilization, (eg. low BER and high data-rates) attention must be paid to the phase and frequency response of both the IF and baseband circuitry. Bitrate, BT and Bandwidth The maximum data rate that can be transmitted over a radio channel depends on: - Channel spacing - Allowable adjacent channel interference - Tx filter bandwidth (BT) - Peak carrier deviation (Modulation Index) - Tx and Rx carrier frequency accuracies - Modulator and Demodulator linearity - Rx IF filter frequency and phase characteristics - Use of error correction techniques - Acceptable error-rate FM Modulator, Demodulator and IF For optimum performance, the ‘eye’ pattern of the received signal (when receiving random data) applied to the FX589 should be as close as possible to the Transmit ‘eye’ pattern examples shown in Figure 10. Of particular importance are general symmetry, cleanliness of the zero-crossings, and for a BT of 0.3, the relative amplitude of the inner eye opening. To achieve this, attention must be paid to - - Linearity and frequency/phase response of the Tx frequency modulator. Unless the transmit data is especially encoded to remove low frequency components, the modulator frequency response should extend down to a few Hertz, two-point modulation being necessary for synthesised radios. - Bandwidth and phase response of the Rx IF filters. - Accuracy of the Tx and Rx carrier frequencies - any difference will shift the received signal towards one of the skirts of the IF filter response. As a guide, a raw data-rate of 8,000b/s at 12.5kHz channel spacing may be achievable -depending on local regulatory requirements- using a BT of 0.3 +/- 2kHz maximum deviation and no more than 1.5kHz discrepancy between Tx and Rx carrier frequencies. Forward Error Correction (FEC) could then be used with interleaving to reduce the effect of burst errors. Reducing the data-rate to 4,800b/s would allow the BT to be increased to 0.5, improving the error-rate performance. Ideally, the Rx demodulator should be dc coupled to the FX589 ‘Rx Signal In’ pin (with a dc bias added to centre the signal at the Rx Feedback pin around V DD /2 [VBIAS] ), however ac coupling can be used provided that: - The 3dB cut-off frequency for 8kb/s is 20Hz or below (i.e. a 0.1µF capacitor in series with 100kΩ ). - The data does not contain long sequences of consecutive ones or zeroes. - Sufficient time is allowed after a step change at the discriminator output (resulting from channel changing or the appearance of an RF carrier) for the voltage into the FX589 to settle before the ‘RxDCacq’ line is strobed.

S/N (dB) (noise in 8kHz bandwidth) 10-5 10-4 10-3 10-2 10-1 456789 1 0 1 1 1 2 1 3 Tx and Rx DC coupled Tx 5Hz, Rx DC coupled Tx 5Hz, Rx 10Hz Tx 5Hz, Rx 30Hz Tx 5Hz, Rx 100Hz BER Fig.12 Effect of AC Coupling on Typical Bit-Error Rate AC Coupling of Rx and Tx Signals In practical applications, it will usually be possible to arrange for any ac coupling between the FX589 Tx Output and the frequency modulator to cut-off at a very low frequency such as 5.0Hz, but ac coupling between the receive discriminator and the input of the FX589 may need to have a shorter time-constant to avoid problems from voltage steps at the output of the discriminator when changing channels or when the distant transmitter turns on. For these reasons, as well as to maintain reasonable BER, the optimum -3dB cut-off frequencies are around 5.0Hz in the Tx path and 20.0Hz in the Rx path. The chart in Figure 12 (above) shows the typical static Bit-Error-Rate performance of the FX589 operating under nominal conditions for various degrees of ac coupling at the Rx Input and the Tx Output: Data Rate = 8kb/s V DD = 5.0V Tamb = 25 oC Tx BT = 0.3 Two Point Modulation In a radio employing a frequency synthesiser, to prevent the radio's PLL circuitry counteracting the modulation process, and to provide a clean flat modulation response down to dc, it is recommended that a two-point modulation technique is employed when using the FX589. Figure 13 shows a suggested basic configuration to provide a two-point modulation drive at 8kb/s from the FX589 Tx Output using the FX019 (a CML product) Digitally Controlled ‘Quad’ Amplifier Array. The FX019 elements will provide individual setting-up, calibration and dynamic control of modulation levels. Level setting control of the amplifiers/attenuators of the FX019 is via an 8-bit data word. With reference to Figure 13: The buffer amplifier is required to prevent loading of the FX589 external RC circuit. Stage B, with R1/R2, provides suitable signal and dc levels for the VCO varactor; C1 is RF decoupling. The drive level should be adjusted (digitally) to provide the desired deviation. Stage C, with R3/R4, provides the Reference Oscillator drive (application dependant). This parameter is set by adjusting for minimum ac signal on the PLL control voltage with a low-frequency modulating signal (inside the PLL bandwidth) applied. Stage D, with its attendant components, could be employed if a negative reference drive is required. Stage A provides buffering and overall level control.

+14dB to -14dB Buffer +3dB to -3dB CONTROL +3dB to -3dB +3dB to -3dB A B C D Tx VCO To Tx REF Osc (+) To Tx REF Osc (-) VSS VSS VSS VSS VVCO C 1 R 1 Fig.2 External RC R R 2 R 4 VREF (+) VREF (-) With reference to the FX019 Data Sheet Stage A = FX019 Channel 4 Stage B = FX019 Channel 1 Stage C = FX019 Channel 2 Stage D = FX019 Channel 3 Note that ALL stages of the FX019 are ’Inverting’ stages ‘Acquisition’ and ‘Hold’ Modes The ‘RxDCacq’ and ‘PLLacq’ inputs must be pulsed ‘High’ for about 16 bits at the start of reception to ensure that the dc measurement and timing extraction circuits lock-on to the received signal correctly. Once lock has been achieved, then the above inputs should be taken ‘Low’ again. In most applications, there will be a dc step in the output voltage from the receiver FM discriminator due to carrier frequency offsets as channels are changed or when the distant transmitter is turned on. The FX589 can tolerate dc offsets in the received signal of at least +/- 0.5V with respect to V BIAS, (measured at the Rx Feedback pin) however to ensure that the dc offset compensation circuit operates correctly and with minimum delay, the ‘Low’ to ‘High’ transition of the ‘RxDCacq’ and ‘PLLacq’ inputs should occur after the mean input voltage to the FX589 has settled to within about 0.1V of its final value. (Note that this can place restrictions on the value of any series signal coupling capacitor.) As well as using the ‘Rx Hold’ input to freeze the Level Measuring and Clock Extraction circuits during a Where data is transmitted in bursts, each burst should be preceded by a preamble designed to allow the receive modem to establish timing and level lock as quickly as possible. This preamble should be at least 16 bits long, and should preferably consist of alternating pairs of ‘1’s and ‘0’s i.e. ‘110011001100 not be used. Data Formats The receive section of the FX589 works best with data which has a reasonably ‘random’ structure --the data should contain approximately the same number of ‘ones’ as ‘zeroes’ with no long sequences of consecutive ‘ones’ or ‘zeroes’. Also, long sequences (>100 bits) of ‘10101010 ...’ patterns should be avoided. For this reason, it is recommended that data is scrambled in some manner before transmission, for example by ‘exclusive-ORing’ it with the output of a binary pseudo-random pattern generator. Fig.13 An Example of Two-Point Modulation Drive with Individual Adjustment Using the FX019 signal ‘fade’, it may also be used in systems which employ a continuously transmitting control channel to freeze the receive circuitry during transmission of a data packet, allowing reception to resume afterwards without losing bit synchronisation. To achieve this, the FX589 ‘Xtal’ clock needs to be accurate enough that the derived ‘RxClock’ output does not drift by more that about 0.1 bit time from the actual received data-rate during the time that the ‘RxHold’ input is ‘Low’. The ‘RxDCacq’ input, however, may need to be pulsed ‘High’ to re-establish the level measurements if the ‘RxHold’ input is ‘Low’ for more that a few hundred bit-times. The voltages on the Doc1 and Doc2 pins reflect the average peak positive and negative excursions of the (filtered) receive signal, and could therefore be used to derive a measure of the data signal amplitude. Note however, that these pins are driven from very high-impedance circuits, so that the dc load presented by any external circuitry should exceed 10MΩ to V BIAS.

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3 to 7.0V Input voltage at any pin (ref V SS = 0V) -0.3 to (V DD + 0.3V) Sink/source current (supply pins) +/- 30mA (other pins) +/- 20mA Total device dissipation (DW/P) @ TAMB 25°C 800mW Max. (D5) @ TAMB 25°C 550mW Max. Derating (DW/P) 13mW/°C (D5) 9mW/°C Operating temperature range:FX589DW/D5/P -40°C to +85°C Storage temperature range:FX589DW/D5/P -40°C to +85°C Operating Limits Correct operation of the device outside these limits is not implied. Remarks Min. Max. Unit Supply Voltage (VDD ) 3.0 5.5 V Operating Temperature -40.0 +85.0 °C Rx and Tx Data Rate (V DD ≥ 3.0V) 4,000 32,000 bits/sec (VDD ≥ 4.5V) *Note 13 4,000 64,000 bits/sec Xtal/Clock Frequency (V DD ≥ 3.0V) 1.0 5.0 MHz (VDD ≥ 4.5V) 1.0 10.3 MHz “High” Pulse Width Note 10 40.0 ns “Low” Pulse Width Note 10 40.0 ns Operating Characteristics All device characteristics are measured under the following conditions unless otherwise specified: Noise Bandwidth = Bit Rate. Characteristics See Note Min. Typ. Max. Unit Static Values Supply Current ((IDD ) VDD = 3.0V)Tx PS Rx PS 1 1 1 - 0.5 - mA 0 1 - 1.0 - mA 1 0 - 1.0 - mA 0 0 - 1.5 - mA ((I DD ) VDD = 5.0V) 1 1 - 1.0 - mA 0 1 - 2.0 - mA 1 0 - 3.0 - mA 0 0 - 4.0 - mA Input Logic Levels Logic “1” 3.5 - - V Logic “0” - - 1.5 V Logic Input Current 2 -5.0 - 5.0 µA Logic “1” Output Level at IOH = -120µA 4.6 - - V Logic “0” Output Level at IOL = 120µA - - 0.4 V Transmit Parameters Tx OUT, Output Impedance 3 - 1.0 - k Ω Tx OUT, Level 4, 11 0.8 1.0 1.2 V p-p Tx Data Delay (BT = 0.3) 5 - 2.0 2.5 bit-periods (BT = 0.5) 5 - 1.5 2.0 bit-periods Tx PS to Output-Stable Time 6 - 4.0 - bit-periods

Characteristics See Note Min. Typ. Max. Unit Receive Parameters Rx Amplifier - Input Impedance 1.0 - - M Ω Output Impedance 7 - 10.0 - k Ω Voltage Gain - 50.0 - dB Rx Filter Signal Input Level 8, 11 0.7 1.0 1.3 V p-p Rx Time Delay 9 - - 3.0 bit-periods On-Chip Xtal Oscillator R IN 10.0 - - M Ω R OUT 12 - 50.0 - k Ω Voltage Gain 12 - 25.0 - dB Notes 1. Not including current drawn from the FX589 pins by external circuitry. See Absolute Maximum Ratings. 2. For V IN in the range VSS to VDD . 3 For a load of 10kΩ or greater. Tx PS input at logic “0”; Tx Enable = “1”. 4. Data pattern of “1111000011110000 ..” 5. Measured between the rising edge of ‘Tx Clock’ and the centre of the corresponding bit at ‘Tx Out.’ 6. Time between the falling edge of ‘Tx PS’ and the ‘Tx Out’ voltage stabilising to normal output levels. 7. For a load of 10kΩ or greater. Rx PS input at logic “0”. 9. Measured between the centre of bit at ‘Rx Signal In’ and corresponding rising edge of the ‘Rx Clock’. 10. Timing for an external clock input to the Xtal/Clock pin. 11. 'Typical' level shown is at V DD = 5.0V; actual levels are proportional to applied VDD . 12. Small signal measurement at 1.0kHz with no load on Xtal output. Xtal may be used, care must be taken with the external components.

The FX589 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage. Package Outlines The FX589 is available in the package styles outlined below. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. FX589DW 24-pin plastic S.O.I.C. (D2) E L X T W PIN 1 A B P F J Y ALTERNATIVE PIN LOCATION MARKING NOTE : All dimensions in inches (mm.) Angles in degrees A B C E F H TYP . MAX.MIN.DIM. J P X W T Y K L 0.419 (10.64) 45° 0° 8° 0.050 (1.27) 0.046 (1.17) 0.046 (1.17) 0.613 (15.57) 0.299 (7.59) 0.050 (1.27) 0.016 (0.41) 0.394 (10.01) 0.566 (14.37) 0.036 (0.91) 0.036 (0.91) 0.597 (15.16) 0.291 (7.39) C H K1 K FX589D5 24-pin plastic S.S.O.P. E Z L X TPIN 1 A B C H P F J Y NOTE : All dimensions in inches (mm.) Angles in degrees A B C E F H TYP. MAX.MIN.DIM. J P X T Y Z L 0.311 (7.90) 10° 0.037 (0.95) 0.328 (8.33) 0.212 (5.38) 0.026 (0.65) 0.022 (0.55) 0.301 (7.65) 0.286 (7.15) 0.318 (8.07) 0.205 (5.20)

CONSUMER MICROCIRCUITS LIMITED

1 WHEATON ROAD

WITHAM - ESSEX CM8 3TD - ENGLAND © 1998 Consumer Microcircuits Limited Telephone: +44 1376 513833 Telefax: +44 1376 518247 e-mail: sales@cmlmicro.co.uk CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry. FX589P 24-pin plastic DIL (P4) H K L Z F J1J P CK1 T B M A EE1 PIN1 Y NOTE : All dimensions in inches (mm.) Angles in degrees A B C E F H TY P. MAX .MIN .DIM. J P Y T Z K L M 0.220 (5.59) 0.552 (14.02) 0.670 (17.02) 0.150 (3.81) 1.270 (32.26) 0.151 (3.84) 0.100 (2.54) 0.121 (3.07) 0.180 (4.58) 0.600 (15.24) 1.10 (27.94) 0.066 (1.68) 0.060 (1.52) 0.074 (1.88) 0.074 (1.88) 1.200 (30.48) 0.500 (12.70)

Ordering Information

FX589DW 24-pin plastic S.O.I.C. (D2) FX589D5 24-pin plastic S.S.O.P. FX589P 24-pin plastic DIL (P4)

In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Micro- circuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. Company contact information is as below: CML Microcircuits (UK)Ltd COMMUNICATION SEMICONDUCTORS CML Microcircuits COMMUNICATION SEMICONDUCTORS CML Microcircuits (Singapore)PteLtd COMMUNICATION SEMICONDUCTORS CML Microcircuits (USA) Inc. COMMUNICATION SEMICONDUCTORS Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com

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Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com No 2 Kallang Pudding Road, 09-05/

06 Mactech Industrial Building,

Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com D/CML (D)/1 February 2002