FX4070A CMLMICRO | Alldatasheet

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Technical content

  • For Information Only - _ FUNCTIONAL SCHEMATIC PUBLICATION D/4071/2/280 S a moe outer SS 20 Address Output F X 50 1 A Sequence calibrate INTEGRATED SS] ee a wee 5 TONE Seles , ENCODER/ ih DECODERS FEATURES @ FULLY FUNCTIONAL 5-TONE SELECTIVE CALLING SYSTEM @ THICK FILM HYBRID CONSTRUCTION © USES CML FX407A/FX507A CHIP @ FIXED OR VARIABLE SYSTEM TIMING @ ENCODER, DECODER AND TRANSPONDER @ CHOICE OF PACKAGE STYLE The FX 4070A, FX 5070A, FX 4071A and FX 5071A are integrated circuits fabricated using thick film hybrid techniques and include a monolithic LS! semiconductor chip. The circuit comprises all necessary components to provide a 5-tone selective calling encoder/decoder which complies with the requirements of the CCIR standard (FX 4070A or FX 4071A) or the ZVEI standard (FX 5070A or FX 5071A). In all respects the operation of these devices is identical to the recommended circuit used in the application of the CML FX 407A/FX 507A integrated circuit. The hybrid circuits include passive components necessary for correct system operation, the trimmer potentiometer required to set frequency calibration is externally connected and external components may also be used to modify internally set system timing parameters.

CIRCUIT DIAGRAM INTERNAL CIRCUIT DIAGRAM OF HYBRIDS. o1GIT SELECT INPUTS DIGIT SEQUENCE OUTPUTS SS SS TT —_F 7 6 5 6 7 6 G$ WO 1 12 13 16 15 16 naa FX407A OR FXSO7A CHIP 3 2) owe 6 8 2s m2 2 ca [) ol} j Hl lo} so Probe FOP be] b er voo 4 vss TX iG ante 1X TONE RESET GRP ADD TxE oR oe te pemiod —oetay PERIOD orp OF Fie HYBRID COMPONENT LIST (This information can be read in conjunction with Production Information on FX 407A) RESISTORS CAPACITORS CIRCUIT DIAGRAM VALUE TOLERANCE| CIRCUITDIAGRAM VALUE TC TOLERANCE REF. REF. R1 100K 5% c1 0.022uf X7R 10% R2 100K 5% C2A=C2B 470pf X7R 10% R3 22K 5% C3A=C3B 0.01 X7R 10% R'O 100K 5% C4 0.22uf X7R_ 10% Rin 330K 10% cS 0.01uF X7R 20% RD 680K 10% cé 68pf NPO 5% RS(FX4070A/FX4071A) 1.22M 2% co 0.01yf NPO 5% RS(FX5070A/FX5071A) 857K 2% Cin 0.01 uF X7R 20% RT 355K 2% Cs 0.22uf X7R_ 20% RL 6002 10% R’b 330K 10% CALIBRATION PROCEDURE Conditions: VDD = 12,5V, TA = 20° + 5°, no input signals. 1) Programme code 6XXXX(FX4070A/FX4071A) or 5XXXX(FX5070A/FX507 1A), where ‘X’ is any convenient digit. 2) Apply VDD. Wait several seconds, then connect a shorting link between pins 23 and VSS. 3) Press the TX Enable button and read the frequency at the TX output. The signal is a continuous tone. 4) Adjust the R’o calibration potentiometer until the frequency is exactly 1541Hz (FX4070A/FX407 1A) or 1530Hz (FX5070A/F X5071A). 5) Remove the shorting link between pins 23 and VSS. Calibration is now completed for all channels for both RX and TX.

EXTERNAL COMPONENT CONNECTIONS 1, The address and group outputs are open drain MOS transistors. This allows the outputs to be linked to give a wire — OR if required. Load resistors (10KQ nom.) are required for these outputs from pin 20 and pin 21 to -Ve supply. 2. A22KQ trimmer potentiometer with a temperature coefficient <100ppm must be connected from R’O to -Ve supply (pin 22), This is used to calibrate frequency as described above. 3. The Output Reset input has an on-chip 1MQ (nominal) resistor to VDD and a 3KQ2 M.O.S. transistor to VSS which is disabled when the outputs are activated. With this input held at VSS the outputs will turn on at power-up. To reset the outputs and to ensure they are off at power-up the pin must be momentarily taken to VDD. An automatic time-out commencing from when the outputs are activated is provided with a resistor in parallel with a capacitor between pins 22 and 32. The interval T’on 70.65, RC seconds, and should be longer than one tone period. 4. Acapacitor (CT) must be provided between pin 23 and the positive supply (VSS) to set the transmitted tone period. The period is given by: Tp = 0.355K CT seconds. where CT is measured in uF K = 0.6 + 0.03 typ. (a constant of the monolithic chip) For CCIR tone period = 100 mS (FX4070A or FX4071A) then CT = 0.47uF For ZVEI tone period = 70 mS_(FX5070A or FX5071A) then CT = 0.33uF 5. Optionally: i) A capacitor (CD) can be connected between the TX Delay pin and the positive supply (VSS) to provide a delay prior to the start of transmission. TX delay period = 0,68K CD seconds * ii) The RX gate period (internally set to 1.75 Tp) can be varied by external components connected in parallel to RS and CS. RX gate period = K RS’ CS’ seconds * * where K = 0.65 + 0,033 typ. RS’ and CS’ are resultant values of internal and external components, CD and CS’ are measured in uF RS’ is measured in Megohms PACKAGE DETAILS F14n104/ 4160108 Pum CORFIEURATION fx407s4/ras0718 pm courientaTiON wwe Pi 32 C]-ve sreee cv wwe 3] “ve seer coy roms Ps a8 [x ocrmr rons fs 2a ({ siom meer rons Po rxaoren 25 (for sear rents wer fs rane 25 (| wx cane rentoo rors fe ” 24 |r ew wwe fo ps 26 (| m nay rente yor o |i Leeionl 23 (rome Pretoo, one fie musena 23] tone renuoo

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ELECTRICAL CHARACTERISTICS

MIN. TYP. MAX. NOTE Supply voltage -10V -15V Supply current 15mA Operating Temperature -20°C +60°C ELECTRICAL CHARACTERISTICS AT VDD = 12 volts & T’amb = 20°C unless otherwise specified. Input voltage logic ‘1’ -8.0V Note 1. Input voltage logic ‘0’ -1.5V Output voltage logic ‘1’ -10,0V Note 2. Output voltage logic ‘0’ -1,0V OPERATING FREQUENCIES (fo of bandpass filters and Tx O/P) see Calibration Procedure. Digit 1 1121Hz 1057.5Hz 2 1200.5Hz | 1163Hz 3 1278Hz 1269Hz 4 1357Hz 1402Hz 5 1444Hz 1530Hz 6 FX4070A 1541Hz 1665.5Hz FX5070A

7 FX4071A 1638Hz 1828Hz FX5071A

9 1856.3Hz | 2203Hz 0 1983Hz 2403Hz R 2113Hz 2601Hz G 2401Hz 2796Hz Frequency stability Af/°C 0.015% Temperature range -20° +60°C Frequency stability Af/Vsupply 0.015% Supply voltage range -10 to -15V DECODER OPERATION Sensitivity 50mV nm.s Max. Signal Handling 700mV rm.s. 3% FX4070A & FX4071A 100% decode BW 4% FX5070A & FX5071A referred to fo 6% FX4070A & FX4071A_ O% decode BW 9% FXBO70A & FX5O71A Feferred to fo Input impedance 100K ENCODER OPERATION Output voltage 1V peak to peak output ; 90ms 100ms 110ms_| FX4070A & Fx4071A} With ded Tone period 63mS 70mS 77mS | FX5O70A & FX5071A} Mende value of CT Output impedance 6002 Note 1. Pins 1-10, 16-19, 22 FX4070A & FX5070A Pins 1-12, 18, 19, 22 FX4071A & FX5071A 2. RLOAD=10KQ Pins 11-15, 20,21 FX4070A & FX5070A RLOAD=10KQ Pins 13-17, 20, 21 FX4071A & FX5071A

Programming is achieved by links between the sequence outputs and the digit select inputs, The repeat code (R) is substituted for consecutive identical digits, e.g. 39999 is coded 39RQR. Should the fifth digit be common to any other digit it must be linked via a diode as shown. Shortened codes are achieved by linking S5 directly to the last digit. EXAMPLES OF CODING SEQUENCE OUTPUTS || S1 S2 S354 S5|S1 52 53 S4 S5 | S1 S2 $3 $4 $5| $1 S2 $3 S4 S5 procramminc Links| | | | | | ltHedild tly 11] t— DIGIT INPUTS 209 64/2 1 -R 0o;1 569 3.65 PROGRAMMED CIRCUIT ARRANGEMENT ' GROUP CALLING sto 20 ADDRESS 01 iweut coves voo + {PULSE INTO PIN 18) r0KA oV Ink ' ° LS [ ‘o'TONE RECEWED WAVEFORM AT PIN 9 When an input code contains a ‘G’ tone, the FX105 switches ON and the 120 edge is coupled to the Group Initiate input (pin 18) of the hybrid. This causes the hybrid to change from the Address code programmed, | to an internal Group programme for the remaining digits of the input code, If the Group code is correctly completed, the Group output of the hybrid switches ON. The Group Initiate is effective only if the correct first two digits of the Address code have been received. The Group Initiate input is disabled during transmit mode, a Group call is transmitted by encoding the ‘G’ tone via the Digit Select inputs. EXAMPLES OF GROUP CALLING 25784 25784 only 1 ADDRESS 2578G 25780 to 25789 10 GROUP 257GR 25700 to 25799 100 GROUP 25GRG 25000 to 25999 1000 GROUP CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change said circuitry.