FX503A

FX503A CMLMICRO | Alldatasheet

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Publication D/503A/1 October 1983 * EIA TONESET VERSION * LOW DISTORTION SINEWAVE OUTPUT * GENERATES FULL QTC CHARACTER *% AUTO REPEAT-TONE ENCODING TONESET * TONE PERIOD TIMING OUTPUT % LOW POWER CMOS PROCESS * DELAYED ~- TX OUTPUT BIAS FACILITY Obsolete Product - For Information Only - DATA. = DATA. OUTPUT ‘oureut INPUTS (CHANGE ENABLE 1 mas AUTO REPEAT ase urces [reoceanne | _ Tl el FX503A ce hp ourPuT Do TONE OUTPUT Fig. 1 Internal Block Diagram The FX503A is a 15 tone generator for use as defined by the EIA international with the EIA toneset, as specified in the toneset. At the end of the tone HSC character tone table. The output tone period the Tp (Tone Period Expired) is a low distortion 16-step pseudo sine output goes to Logic 1 and remains wave of VDD-VSS peak-peak amplitude from there until the next DATA CHANGE which a nominal 1k@ source impedance. The total resets the output and commences next. harmonic distortion is less than 10% and timing period. The output tone can be all harmonics are less than 120dB. Output delayed by a period (Td) after the OUTPUT tones and timing signals are provided by ENABLE function is activated. This is a reference oscillator of 560kHz, achieved by an external RC time constant comprising an on-chip inverter and (see Fig. 6) and a Schmitt trigger input external ceramic resonator: an external on the OUTPUT ENABLE pin. Note that if clock may be used if required (Fig 2 diode (D1) is present, the tone output and 3). will go to VSS as soon as OUTPUT ENABLE : goes from 1 - 0. The device uses nominal The output periods are controlled by 5V supply. on-chip circuitry. Timing periods are

PIN DESCRIPTION ‘FUNCTION FX503A (16-pin D.I.L. package only) 1 Tone Output: Pseudo-sinewave: (approx. 16 steps). Zo ~ 1kM. VDD-VSS peak-to-peak. Total harmonic distortion <10%, individual harmonics <-20dB. Can be biased to approx. 40% VDD by use of output bias (pin 3), or disabled (to VSS) by use of output enable (pin 4). Output periods controlled by on-chip circuitry. 2 Tp Output: Tone period timer - goes to 1 (i.e. 33 ms) after receipt of output enable 0 ~ 1 edge or D/C 0 - 1 edge. Is reset to logic 0 and timing restarts at subsequent D/C 0 - 1 edge.

3 Output Bias: Logic 1 (with output enable at logic 0) will set tone output

to approx. 40% VDD. 4 Output Enable: Schmitt input. Logic 0 (with output bias at logic 0) will set tone output to VSS + this also reduces current consumption, Will also disable Tp output. Logic 1 + tone is output. 5. Data Change: Controls the output in two ways: Logic 1 + output tone controlled by data inputs; 1 + 0 latches input data.

6 Auto Repeat: Logic 1 will enable auto repeat circuitry: two consecutive

equal data characters will output character tone followed by repeat tone, i.e. data is input TRUE as read.

7 Tp Output: This output is the inverted form of pin 2,

8 vss: Negative Supply.

9 Do ) Data These inputs are strobed by data change or output enable

10 Dj ) Inputs: 0 - 1 edge. i D2)

12 Ds )

13 Char: Acts as a fifth data input. Logic 1 overrides D,-D, (but still strobed by D/C) and sets tone output to 40% VDD until new data is loaded. 14 560 kHz ) It uses an on-chip inverter for use with a 560 kHz ceramic Xtal I/P ) resonator [or external clock can be fed into $-in pin {clock I/P) ) (pin 14)). . 15 Xtal Osc. } ‘ o/P ) (Clock 0/P) ) 16 VDD: Positive supply. VDD (+5V) Tone output [7 i Tp Output 2 is [Steck O/P 5.) see Note 1 Output Bias | , Clock 1/P Internal Inverter 14 | [>° | Output_Enable. Char (Schmitt T7P)] 4 Fxs038 13 L— dein 14,49 Pin 15 §— —! Data Change Ds — 5 12 Auto Repeat J. a fe22 ' (a= kHz Tp Output bt Data Inputs Xta 7 10 3 9 be _ arr 5-65 pF Farpr NOTE 1: Output frequency and tone VSS period are internally derived . : from the input clock frequency. Fig. 2 External Component Output stabilities with time, Connections temperature and supply voltage are directly proportional to input clock accuracy.

Exceeding the maximum rating can result in device damage, Operation of the device outside the operating limita is not implied. Supply voltage ..sesssecesseseeeeeeeseseeereseeess 4:5V to 5.5V Input voltage at any pin (ref Ves = OV) : Output sink/source current (total) = mA, Operating temperature range -30°C to +85°C Storage temperature range -55°C to +125°C . Maximum device dissipation 100m OPERATING LIMITS VDD = SV, Ta = 25°C, @= 5S60kHz, Afo = 0 All characteristics measured using the standard test circuit. vpD Supply voltage (Vss = 0) 45 5 5.5 v top | Supply current - no output tone .. 700. pA |) no lead vp | supply current - generating tone 2 ma |} connected fo Output frequency(from nominal) 70.2 +0.25 % > = S60kHz Tp Output tone period Loe 33 ms H See Note 1 von | Logic '1' output level Isouree = 0.1mA | 4.0 vo jy Fle 2 voL’| Logic '0' output level Isource = 0.1mA 1,0 v 3 pins 2,7 vin | Logic '1' input level 3.5 . v pins 5,6 VIL | Logie '0' input level us | ov 5-13 Input level to activate pins 3 & 4 3.25 Vv ) Scbmitt : . PErgger Input level to deactivate pins 3 & 4 1.75 v 3 anpuls TA Working temperature range ~30 +85 % . Tstg | Storage temperature range . -55 +125 °c : Fig? — : S60 kHz Resonator Circuit." Calibration Procedure for Ceramic Resonator Oscillator Internal Inverter as >< | ‘To ensure that the generated outputs are correct the | pin 14. pin 15 | oscillator frequency must be 560.0kHz. ‘The loading of ima Y a frequency counter on the oscillator circuitry can cause —. an error, The preferred method is to wonitor Pin 1 while 560 kHz the FX 503A is generating Tone E (exact set-up condicicns OF eer + willdepend on the system arrangement). Adjust the oscillator to obtain a tone output of 459.0Hz. . Tarr 5-65 pr. Dazpp Ti8- S| Cincutt to provide (pig: 7: FXSOSA - earn = = 47PF Tranamit Delay Funétion _- “Package ‘Outiines ¢ i a a ~ Package Qutlines 2 yo. B ta voo . 1 &: : Transmit Delay Function $ oo SON Sh! A transmit delay can be ENABLE SWITCH 9 | ee a ee arranged as shown in Fig. outeur BIAS q_— _- The tone output will step to rs ; “ pr the bias condition for the OUTPUT ENABLE, y delay period before . . commencing to generate tones. - : : che op HANDLING PRECAUTIONS i = aa The FX5SO3A is.:a CMOS-LSI integrated s-F circuit which includes input protection. i t However, precautions should be taken to . * dae | 4 prevent static discharges which can cause ..!_~—__ 2 wd wad b. damage, : ' aad be,