FX429

FX429 CMLMICRO | Alldatasheet

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CML Semiconductor Products PRODUCT INFORMATION FX 429 Band III FFSK Modem for Trunked Radio Systems Publication D/429/6 July 1994 Features/Applications © Band III and General Purpose @ Frame SYNC and SYNT Detection Trunked Radio Applications © Preamble Generation © Full-Duplex 1200 Baud Operation. processor Compatible Interface

2 High Intelligence © Carrier Detection On-Chip

Error Checking in Receive © Low Power Consumption e . Error Check Word Generation © General Purpose Timer Skid “3 NEw me (ef fee Gap Ya cate % | here atery— | ~ oe Fxg Availapy _— sym “se es. = SFXa2oq 5 acanmuen = sronranoy = ES eV aes he noe = ES = | FX429 seoaren ‘apie : sone Tr ssa] : ison omar LT smmnsurren —9 (Er Se a ES bod ToRS_}1 000 ae ca [ae] Fig.1 Internal Block Diagram Brief Description ‘The FX429 is a single-chip CMOS 1200 baud FFSK Preamble and an error-check word are automatically Modem, designed primarily for use in trunked radio generated in the transmit mode. systems but may also be employed in other general Error checking is performed and the 16-bit SYNC or Purpose radio or line data communication SYNT words are detected in the receive mode. applications. ‘An on-chip Xtal/clock generator requiring an external The device has been designed to conform to the UK 4.032MHz Xtal or clock input provides all microcircuit Band III trunked radio protocols MPT 1317/1327. filter sampling clocks and modem timings whilst also The FX429 is full duplex at 1200 baud and includes supplying a “Clock + 4” output (1.008MHz).. an 8-bit parallel microprocessor interface and a The FX429, which has a powersaving facility, requires a programmable timer which may be set for interrupt single 5-volt power supply and is available in both Periods of 8 to 120 bits. cerdip DIL and plastic SMD packages.

1 1 Veg ? The internal circuitry bias line, held at V,,/2 this pin must be decoupled to V,, by capacitor C,, $00 Figure 3. Warning Note ~ In order to reduce current consumption, the potential at this pin is lowered to V,, when both Tx and Rx are disabled. 2 2 ‘Transmit Output : The 1200 baud, 1200Hz/1800Hz FFSK Tx output. When not enabled by the Control Register ( D,) its output impedance is set high. 3 4 Receiver input : The 1200 baud received FFSK signal input. The 1200Hz/1800Hz audio to this pin must be a.c. coupled via capacitor C,, see Figure 3. 5 5 Vip 3 Positive Supply. A single +5V regulated supply is required. It is recommended that this power tail be decoupled to V,}, by capacitor C,, see Figure 3. 6 6 Carrier Dotect Time Constant : The on-chip Carrier Detect integration function requires two ‘external components on this pin. A capacitor, C,, to Vg, together with a resistor, Ri, to Viq. See Figure 3. 7 7 Xtal/Clock : The input to the clock oscillator inverter. A 4.032 MHz Xtal or extemally derived clock Pulse input should be connected here. See Figure 3. 8 8 ‘Xtal : The output of the 4.032 MHz clock oscillator, 9 9 D,: Microprocessor Data Interface 10 10 D): n "1 D: 12 12 0: ‘These 8 lines are used by the device to communicate with a microprocessor 13 13 D,: with the A,, A, and A, inputs determining register selection. 4 4 Dy: 15 18 Dy: 16 16 D,: 7 7 ‘A, Register Selection. Those inputs, with the A, input, select the required register to 18 18 A: the data bus as shown in Table 1 (below). ee [ Register A A A, Control 0 1 1 | Status 1 1 1 Table 1 Rx Data 1 0 1 Tx Data 0 0 1 Syndrome Low 1 0 ° Syndrome High 9 ___0 19 19 ‘Strobe : Performs the dual functions of selecting the device for Read or Write and strobing data in OF out. It should be generated by gating high-order address bits with a readiwrite clock. The FX429 is selected when Strobe = logic “0.” See Figure 5. 20 20 fs Used in coniunction wih A, and A. 10 determine which intarnal egistrs are connected tothe data intertace pins (D, - D,) during (see Table 1 and Figure 5). a 2 TRG : interrupt Request. This line will go to a logic '0' when an interrupt occurs. This output can be “wire OF'd" with other active low components (100k@ pullup to V,.). The conditions that cause the interrupts are indicated at the Status Register and are as follows: Timer Expired Rx Data Ready Tx Data Ready Tx idle Rx SYNC Detect Rx SYNT Detect 23 22 Vsa : Negative Supply (GND). 24 23 Clock + 4 : A 1,008 MHz (X, + 4) clock is available at this output for external circuit use, note the source impedance and source current limits. 4,22 3,24 These pins are not connected internally, leave open circuit.

The recommended Digital Code Format for use over Land Mobile Radio Systems is detailed in the Department of Trade and Industry, Radio Regulatory Division's publications MPT 1317 and MPT 1327, and is as described briefly below. Fig. 2 The Data stream — Rx and Tx at 1200baud, the minimum, overall transmission length is 96 bits. Preamble SYNC or SYNT For bit sync. SYNC Word ‘Address Code 101010...10, reversals} 110091001 1010111 Word Optional Data Minimum 16 bits, ending in SYNT Word Words logic’o” 0011101100101000 64 Bits ‘Address Code Word Structure (Bit number 1 is transmitted first) see fos Te ee Te ew Te ee] a a ‘Address Logic ‘1’ Users identi ‘Check Bits structure | "9 " pita (Checksum) Operation ‘The FX429 can be used for Full-Duplex operation with the host microprocessor only having to operate on the data whilst the modem (FX429) handles all other signalling routines and requirements. In the Tx mode the FX429 will In the Fx mode the FX429 will (1) Internally generate and transmit a preamble — bit (1) Detect and achieve bit synchronization within 16 bits. reversals, for system bit synchronization. (2) Search for and detect the 16-bit 'SYNC//SYNT word. (2) Accept trom the host, and transmit, a 16-bit ‘SYNC’ or (3) Output all received data after ‘SYNC/SYNT,'in byte form. ‘SYNT word. (4) Upon a software command (Rx Message Format), use the (3) Accept from the host, and transmit, 6 bytes of data received checksum to calculate the presence (if any) of (Address Code Word). errors, and advise the host with an interrupt and a 16-bit (a) Upon a software command, internally calculate and ‘Syndrome word. transmit a 2-byte checksum based on the previous 6 data Note — In Rx a software command is used to determine bytes. -or= whether a'SYNC''SYNT word is required after every 8 (6 data (0) Upon a software command, disable internal checksum +2 checksum ) received bytes, or “data” is received generation and allow continuous data transmission. continually. 7+ Transmit + hang bit’ and go idle when all loaded data ‘Normally the ‘SYNC’ word is used on the Control data channel traffic has been sent (followed by a "Tx Idle" interrupt). and the ‘SYNT' word is used on the Traffic data channel. Non MPT Application - Full-Duplex The functions described in this section, to allow the FX429 modem to operate as a general purpose device, are obtained using the commands and indications detailed in the “Register Instructions” pages. preamble until data for transmission is loaded by the host (see notes) before outputting data bytes. The modem receiver microprocessor. will then output continuous bytes of data, after every 6 bytes Transmits 6 bytes of the loaded data followed by a received a 2-byte checksum word will be output and can be 2-byte checksum based on that data. As long as Tx data is _ignored or used for error checking, loaded the transmitter will transmit, the 2-byte checksum being produced after evary 6 bytes (8 byte packages). ‘Automatic checksum generation can be inhibited by a software command to allow transmission of continuous data ‘streams.

Control Register A,=1 Aye A,=0 Write Only The Control Register, when selected, directs the modem's operation as described below. Bit __ Description Function Set = logic '1' (High) Clear = logic ‘0’ (Low) BitO Tx Enable* ‘Set - D, enables the transmitter for operation. A ‘0 — 1" transition causes bit synchronization. be transmitted. If data is loaded into the Tx Data Butter before one byte has been sent then that data will folow, otherwise whole bytes of preamble will continue until data is loaded. Cleer — The Transmitter Output pin is set toa high impedance and no transmitter interrupts are produced. Bitt Tx Parity Enable Set D, indicates to the transmitter that 2-byte checksums are to be generated by the D, modem. A'0 - 1" transition starts checksum generation on the next six bytes loaded from the Tx Data Buttor into the Tx Data Register. Checksum generation continues for every 6 bytes loaded until this bit is cleared. The transmitter will send the generated checksum (2 bytes) after the last of each 6 bytes have been sent. i an underrun (no more data loaded) condition |~ ‘occurs before 6 bytes have been loaded checksum generation will abort, the transmission will cease after one ‘hang’ bit has been sent and Bit 4 in the Status Register (Tx Idle) will be set. No checksum will be transmitted. Clear — No checksum generation is carried out and the host may supply the checksum bytes. The output is then “as written”. Bit2 Rx Enable* Set - D, enables the receiver for operation. No data is produced (.e. No Rx Data Ready D, interrupts) until a ‘SYNC’ or 'SYNT" word is found in the raceived bit stream. Clear — The receiver is disabled and all interrupts caused by the receiver are inhibited. BIS Rx Message Set - D, is sampled after a checksum has been received and allows the host to control the D, Format way the receiver handles the following data bits. I'sef the receiver will assume that the next 6 bytes are data and will start error checking accordingly. Clear - The receiver will stop data transter to the host after the 2 checksum bytes until another "SYNC’ or ‘SYNT frame word is received. Bit4 Timer LSB These four bits control the timer as follows :- Dd, D, D, Dd, D, o 0 o o' Reset counter and disable timer interrupts 0 o o 1 Count and interrupt every- 8 bits 0 o 1 Oo * . * 16 bits o o 1 4 : : . 24 bits Bits Timer o 1 0 0 : : : 32 bits D, o 1 0 14 . : . 40 bits o 1 1 0 : : . 48 bits o 1 4 4 . : . 56 bits 1 0 0 0 : : . 64 bits 1 0 0 1 : : . 72 bits Bits Timer 4 0 4 0 . : . 80 bits D, 4 0 4 1 . : . 88 bits 1 1 0 0 . . . 96 bits 1 4 0 4 : : . 104 bits 4 1 4 0 . : . 112 bits 4 04 44 . . * 120 bits BRT Timer MSB if'a new timer value is written to these inputs within 1 byte poriod of the last timer interrupt D, then the next timer period will be correct without first having to reset the timer, otherwise the timer must be reset to zero and then set to the new time. * Note - Enabling Times The time taken to enable one section (receiver or transmitter) when both sections are initially disabled is 16 bit periods. If one section (receiver or transmitter) is already enabled this time is reduced to “one-half of a bit period. Tx Enable It using the internal Tx Preamble generation facility, e.g. with the internal timer setting the preamble length, the device may o¢casionally produce a Tx Data Ready interrupt immediately after a Tx Enable command. User software should handle this occurrence by either: (a) Detecting that the Timer interrupt Status Bit is not set and that itis not appropriate to load Tx data at this time. or, (b) Not using the Timer. i.8. immediately atter Tx enable, reading the Status Register and loading a byte of preamble. This resets any interrupt. The length of preamble transmitted is now controlled by the number of bytes loaded.

Status Register A=1 Aj=1 A,=1 Read Only When an interrupt is generated the IRQ Output goes Low with the Status Register bits indicating the sources of the interrupt. Bit Description Function ‘Set = logic '1' (High) Clear = logic '0' (Low) BO Rx Data Ready —_D, when set, causes an interrupt indicating that received data is ready to be read from the Rx Data o, Buffer. This data must be read within 8 bit periods. ‘Set — when a byte of data is loaded into the Rx Data Buffer, if a frame (SYNC/SYNT) word has been received. Bit and Interrupt Cleared — (i) by a read of the Status Register followed by a read of the Rx Data Buffer or (ii) by Rx Enable going Low. Bh1 Rx Checksum D, when set, indicates that the error checking on the previous 6 bytes agreed with the received D, True checksum. This function, which is valid when the Rx Data Ready bit (D,) is set for the second byte of the received checksum, does not cause an interrupt. vy, ‘Set - by a correct comparison between the received and generated checksums. Cleared- (i) by a read of the Status Register followed by a read of the Rx Data Butter, or (ii) by Rx Enable going Low. Bit2 Rx Carrier D, is a * Real Time ” indication from the modem receiver's carrier detect circuit and does not cause D, Detect an interrupt. When FFSK tones are present at the receiver input this bit goes High, for no FFSK input this bit goes Low. When the Rx Enable bit (D,- Control Register) is Low Rx Carrier Detect will go Low. BR3 Tx Data 'D, when set, causes an interrupt to indicate that a byte of data should be written to the Tx Data D, Ready Butter within 8 bit periods. ‘Set (i) when the contents of the Tx Data Buffer are transferred to the Tx Data Register, or (ii) when the Tx Enable is set — No interrupt is generated in this case. Bit Cleared — (i) by a read of the Status Register followed by a write to the Tx Data Butter, or (ii) by Tx Enable going Low. Interrupt Cleared— (i) by a read of the Status Register, ‘or (li) by Tx Enable going Low. BR4a Txidle D, causes an interrupt when set, to indicate that all loaded data and one ‘hang’ bit have been D, transmitted. ‘Set — one bit period after the last byte is transmitted. This last byte could be either “checksum” or * loaded data” depending upon the Tx Parity Enable state (Control Register D,). Bit Cleared- (i) by a write to the Tx Data Butter, or (ii) by Tx Enable going Low. Interrupt Cleared- (i) by a read of the Status Register, or (ii) by Tx Enable going Low. BitS Timer D,, when set, causes an interrupt to indicate that the set timer period has expired. (Control D, Interrupt Register D,— D,). Set — by the timer. Bit and Interrupt Cleared — by a read of the Status Register. BR6 Rx SYNC D,, when set, causes an interrupt to indicate that a 16-bit ‘SYNC’ word (1100010011010111) has Ls Detect * been detected in the received bit stream. ‘Set — on receipt of the 16th bit of a ‘SYNC’ word. Bit and Interrupt Cleared— (i) By a read of the Status Register, ‘or (li) by Rx Enable going Low. BiL7) Rx SYNT D,, when set, causes an interrupt to indicate that a 16-bit 'SYNT word (0011 101100101000 ) has D, Detect * been detected in the received bit stream. Set — on receipt of the 16th bit of a 'SYNT' word. Bit and Interrupt Cleared- _(i) By a read of the Status Register, ‘or (ji) by Rx Enable going Low. * Note — ‘SYNC’ and ‘SYNT' Detection is disabled whilst the checksum checker is running.

Rx Data Buffer A=1 A,=0 A,=1 Read Only These 8 bits are the last byte of data received with bit 7 being received first. Note the relative positions of the MSB and LSB presented in this bit stream, the position may be different to the convention used in other Processor peripherals. o, D, D, D, 9, o, D, D, LSB - - - - - - MSB Tx Data Buffer Aj=1 A,=0 A,=0 Write Only These 8 bits loaded to the Tx Data Buffer are the next byte of data that will be transmitted, with bit 7 being transmitted first. Note the relative positions of the MSB and LSB presented in this bit stream, the position may be different to the convention = *~» used in other Processor peripherals. it the the Tx Parity Enable bit (Control Register D, ) is set, a 2-byte checksum will be inserted and transmitted by the modem after every 6 transmitted “ message ” bytes. Dd, D, Dd, D, D, D, D, D, The Syndrome Word This 16-bit word (both Low and High bytes) may be used to correct errors. Bits S, to S,, are the 15 bits remaining in the polynomial divider of the checksum checker at the end of 6 bytes of * received message.” For a correct message all 15 bits (S, to S,,) will be zero. The 2 Syndrome bytes are valid when the Rx Data Ready bit (Status Register D,) is set for the second byte of the receivedchecksum and should be read, if required, before 8 byte periods. Syndrome Low Byte A,=0 A,=0 A,=1 Read Only _ Dd, D, D, Dd, Dd, D, LA Dd, s1 s2 $3 S4 s5 $6 s7 s8 Syndrome High Byte = a,=0 Ay=1 A,=1 Read Only Dd, D, D, D, D, Ly Ly 0, so S10 si $12 $13 Si4 S15 PARITY ERROR D, - This is a “Parity Error Bit” ~ Indicating an error between the received parity bit and the parity bit internally generated from the incoming message. Thus for a correctly received message all 16 bits of the Syndrome Word (S, to S,, and Parity Error) will be zero.

“= [ Component References _| Yes al | Component | Unit Value TRANSMIT OUTPUT Ves R, 1.0M lRecene weuT ° S R, 1.0M Ice — > 3 ial Ves c, 33p ‘ as ¢, 39 ce Yoo 5 a» > c, ot ae ‘ 10 fe STROBE. c, 1.08 call corre constant] © FX42QJ a c 1.0, XTAUCLOCK 7 * [o 1.0p. ‘SEE INSET he * ; = ® ” x, 4.032MHz oJ, 16 L_& Tolerances. Resistors + 10% Capacitors + 20% Dd 10 15 Je Z ay 14 jee Recommended Xtal Ds oe Componente, kd 8 xialClock | Pin No. Praca MICROPROCESSOR DATA INTERFACE LD4 ot Oat oat ot ost Oot of ol ote 8 Ves, Fig. 3 Recommended External Components it « Carrier Detect Time Constant The value of the Carrier Detect capacitor, C, , determines the carrier detect time constant. A long time constant (larger value C,), results in improved noise immunity but increased response time. C, may be varied to optimise noise immunity/ reponse time. 2x 107 Ideal Coherent FFSK FXx429 Characteristic Characteristic = 10% a BE we ae S 94 10° 10°, o 1 2 3 4 56 6 7 8 8 WH 2 13 4 15 16 Signal to Noise Ratio (dB) [Bit-Rate Bandwidth] (Linear Scale ) Fig. 4 Bit Error Rate vs Signal to Noise Ratio

& Km <C> STROBE i < wee be = SIRE SESS toe yes — Access Time yy — Address Hold Time tow — Data Hold Time (Write) ys — Address Setup Time 1, ~ Data Setup Time ow — Qutput Hold Time (Read) Fig. 5 Read and Write Timing Diagram te = Sober Operation - Rx ~ (a) Rx —where SYNC/SYNT is required after every message mewsef moeut ma ANNAN nAN IN eum Prttttttt tt tt sncienn n n ngeosw nh Stine rlriridl tll EO (0) - where additional data will follow the initial address data, indicated by the state of the Rx Message Format bit ee Cee ce sem tt ot ot dit tl tl tl th tlt t Sito! Et ete irr r tre — \\ nae Fora epaar pada Fig. 6 Simplified Rx Timing {a) whether the message is complete or (b), more data follows

Operation — Tx (a) Tx - one message with checksum supplied by the host i a i monn Reon DE Seti prpe hh bb det peso sas easren ttttttt ttt ot a THe (b) Tx - one message with checksum generated Internally i a osrer a en Oe | | SNE Prrtkt tht peso satus easren ft ttt tttt t par wee n (c) Tx - more than one message, with checksum generated internally Ghreur * A Foonret Sittin PErrhc kbd hb rrr are nso rus earn tttttttt tttttttt t pele PeTata Tepe === papep News Bo ourrur A: dies com fh: East a do oyiiidd HE, BEE | op tpt rt tama Fig. 7 Simplified Tx Timing mms

‘Setup aT byte varabio nals To 2070 (Rx Msg Length) ‘Set up an 8 byte butter ‘start address - (Rx Butter) ‘Set up a 1 byte variable - initialise to zero (rag Sent) ‘start address - (Tx Butter) Pat {or tanemission into = eputer(Tx Bute) Bio Tx Enable =" bth Te Party Enable = 0° ‘Write to Control Bie Renae ‘Wait 1 byte Bits ~ Rx Message Format = "0° (Specicaton requis 2 minimum of two bytes preamble) ‘Write [Tx Butter (@) | Tx Data Butler Return to Main Program Fig. 8 Power—Up Flow

Basic Software Interrupt Flow Status Register Yes Tx Dat - Ready 2 Write to TX Data Buffer with [Tx Buffer (Tx Msg Sent } Xo TTx Meg Seni] = [Te Mag Sent + 7) oe ‘Tx Parity = "1 y Rx Data \\, Yes Ready 2 ‘Read Rx Data Buffer and Store at Rx Butfer}(Rx Msg Len} Rx Msg Len = Rx Msg Len +1 Se Yes: ‘Save state of <E> ‘Save Syndrome - Hi trdtow Ye “<ES> tee Ss Foliow 2 No rogst Peo Yes = ne No Return From IRQ Fig. 9 Interrupt Flow

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. ‘Supply voltage -0.3 to 7.0V Input voltage at any pin (ref Vg = OV) -0.3to (Vp +0.3V) ‘Sink/source current (supply pins) +1 30mA (other pins) + 20mA Total device dissipation @ T,,,, 25°C 800mW Max. Derating 1omwrc Operating temperature range: FX429J -30°C to +85°C (ceramic) FX429LG/LS -30°C to +70°C (plastic) Storage temperature range: FX429J -55°C to +125°C (ceramic) FX429LG/LS ~40°C to +85°C (plastic) Operating Limits All characteristics are measured using the following parameters unless otherwise specified: ~ Bit Rate Bandwidth = 1200Hz. SSS Characteristics See Note Min. Typ. Max. Unit Static Values Supply Voltage 45 - 55 v Supply Current Ranges Ax and Tx Enabled - - 7.0 mA Rx Enabled, Tx Disabled - 4.0 6.0 mA Rx Disabled, Tx Enabled - - 7.0 mA Ax and Tx Disabled 10 - 15 25 mA Dynamic Values Modem Internal Detay - 15 - ms Interface Levels Output Logic 't’ Source Current 2 - - 120 HA Output Logic '0' Sink Current 3 - - 360 HA ‘Three State Output Leakage Current - - 40 HA D, - D, Data in/out 1 Logic 't' Level 35 - - v Logic ‘0’ Level - - 18 Vv A,, Ay A,, STROBE, IRQ 4 Logic 't' Level 40 - - v Logic ‘0’ Level - - 1.0 v ~ Analogue impedances — Rx Input 100 - - kQ ‘Tx Output (Enabled) - 10 - kQ ‘Tx Output (Disabled) - 5 - Ma ‘On-Chip Xtal Oscillator Ra 10 - - Ma Row 5 5.0 - 15 ko Oscillator Gain - 15 - oB Xtal frequency - 4.032 - MHz Timing - (Fig. 5) ‘Access Time = (thes) - - 135 ns Address Hold Time = (t,,) 0 - - As Address Set-up Time ~ (t,,) 0 - - ns Data Hold Time (Write) ~ (toa) 85 - - ns Data Set-up Time (Write) — (tos) 0 - - ns Output Hold Time (Read) ~ (tore) 15 - 105 ns Strobe Time = (ty) 140 - - ns

Characteristics Se Note ins Tye Meet Receiver Signal input Levels 6 8.0 20 +105 cr) Bit Error Rate 7 @ 1248 Signal/Noise Ratio - 70 - 10+ @ 2048 Signal/Noise Ratio - 1.0 - 10* ‘Synchronization @ 12dB Signal/Noise Ratio 8 Probability of Bit16 being correct - 99.5 - % Carrier Detect Response Time 8 - 13.0 - ms Transmitter Output Level - 8.25 - a8 Output Level Variation 1.0 - +1.0 6B Output Distortion - 3.0 50 % 3rd Harmonic Distortion - 20 30 % Logic '1' Frequency 9 - 1200 - Hz Logic ‘0’ Frequency 9 - 1800 - Hz Isochronous Distortion 41200Hz - 1800Hz - 25 40 us 1800Hz - 1200Hz - 20 40 Hs Notes 1. With each data line loaded as, C = S0pt and R = 10kQ. 2. Voy = 4.6V. 3. Voy # 0.4V 4, Sink/Source currents < 0.1mA. 5. Both Xtal and Xtal + 4 Outputs. 6. With 50dB Signal/Noise Ratio. 7. See Figure 3, Bit Error Rate. 230mV rms (-2.348) with no noise. 9, Dependent upon Xtal tolerance. r~ 10. Powersave is only active when both Rx and Tx functions are disabled. Checksum Generation and Checking Generation — The checksum generator takes the 48 bits from the 6 bytes loaded into the Tx Data Butfer and divides them ‘modulo-2, by the generating polynomial;- X14 XE XE XE KE XE Itthen takes the 15-bit remainder from the polynomial divider, inverts the last bit and appends an EVEN parity bit generated from the initial 48 bits and the 15 bit remainder (with the last bit inverted). This 16-bit word is used as the “Checksum.” Checking — The checksum chacker does two things: It takes the first 63 bits of a received message, inverts bit 63, and divides them modulo-2, by the generating polynomial;- XIE XIE XT KE XE ‘The 15 bits remaining in the polynomial divider are checked for all zero. Secondly, it generates an EVEN parity bit from the first 63 bits of a received message and compares this bit with the received bit (bit 64). fine 15 0 te polynomial divider are all zero, and the two parity bits are equal, then the Fix Checksum True bit (SR D,) bit is set.

Package Outlines Handling Precautions ‘The FX429 is available in the package styles outined ‘The FX429 is a CMOS LSI circuit which includes input below. Mechanical package diagrams and specifications —_protection. However precautions should be taken to are detailed in Section 10 of this document. prevent static discharges which may cause damage. Pin 1 identification marking is shown on the relevant iagram and pins on all package styles number anti-clookwise when viewed from the top. FX429J = 24-pin cerdip DIL (J4) FX429LG 24-pin quad plastic encapsulated bent and cropped (L1) NOT TO SCALE NOT TO SCALE Max. Body Length 32.03mm Max. Body Length 10.25mm Max. Body Width 14.81mm Max. Body Width 10.25mm FX429LS 24-lead plastic leaded chip carrier (L2) NOT TO SCALE iN

Ordering Information

FxX4295 24-pin cerdip DIL (J4) FX429LG = 24-pin quad plastic encapsulated bent and cropped (1) FX429LS —24-lead plastic leaded chip Max. Body Length 10.40mm carrier (L2) Max. Body Width —10.40mm CML does not assume any responsibility for the use of any circuitry described. No circuit patent foences are implied ‘and CML reserves the ight al anytime witout noice to change the said creuity