FX406

FX406 CMLMICRO | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

CML Semiconductor Products PRODUCT INFORMATION «¢eqm™ Universal Analogue Publication D/406/7 July 1994 Features/Applications @ 2nd Order Multiple Filter @ Programmable Filters @ PLi Clock Generator @ Voltage Controlled Filters “ Programmable @ Sinewave Oscillator @ F, set by RC or External Clock @ Tracking Filters/Oscillators ®@ Gain Adjustment on Inputs @ FSK and PSK Modems @ Single 5 Volt Supply CMOS @ Square-Sine, Pulse-Sine Converter Yo PHASE COMP %s———> TYPE O/P Vesas ———— f,0/P amor uuTer ea ha pe ft, cLock o7* oe PHASE mauve FX406 > BaNSPASS 07 FILTER 1 FILTER ee : PQ, Fig. 1 FX406 Unifil™ internal Block Diagram = °% =P Brief Description derived from a multiplying phase locked loop The FX406 Unifil™ is a CMOS LSI circuit whose reference or input frequency is the with a wide variety of signal processing same as the desired cut-off frequency of applications. The device consists of a the filters. The PLL comprises a voltage switched capacitor second order active filter controlled oscillator, one of two types of with a single input and outputs for bandpass, phase comparator, a fixed divider and an notch, lowpass and highpass frequency external RC loop filter. Facilities are provided responses, together with a clock generator to to programme the cut-off frequency of the provide the switched capacitor sampling filters by injecting an external signal into the clock frequency. The centre frequency of the PLL, or by using the on-chip clock oscillator bandpass and notch filters is the same as the circuit. The filters have gain adjustment on cut-off frequency f,of the lowpass and the input and the Q is programmable to eight highpass filters. The filter sampling clock is values between 0.54 and 8.0.

1 1 PCI O/P: Output of ‘EXCLUSIVE-OR’ type phase comparator. See Note on PLL operation. 2 2 PLL I/P: Input to limiter preceding phase comparators. 3 4 f,O/P: Divided down VCO square wave output. 4 5 PQ WP: These pins set the Q of the filters; they have internal resistors to 5 6 PavuP: set Q = 0.71 if left open circuit (logic state 10 1, = 1MQ) 6 7 Pa’ vp: Possible Q values are:

2 PQ, PQy PQ Q

1 1 1 0.54" 1 1 oO 0.58 (Bessel) 1 0 1 0.71 (Butterworth) 1 tC} 0 1.00 . 0 1 1 1.31 0 1 0 2.00 i 0 1 4.00 0 0 0 8.00 * (Cascaded with a 1.31 section for a 4th order Butterworth filter). 7 8 Clock O/P: Digital output of limiter from uncommitted amplifier, 8 10 Amp O/P: Analogue output of uncommitted amplifier. 9 aa Reference: Inverting input to uncommitted amplifier. 10 12 Clock /P: Non-inverting input to uncommitted amplifier. " 13 V.,: Negative supply. 12 14 V__: V_/2bias pin, externally decoupled. ous’ Yo0 13 15 Filter /P: Input to filter input buffer amplifier. 14 16 Gain: Output of filter input buffer amplifier. 15 7 Highpass O/P: Output of the highpass filter. The cut-off frequency is identical to the input frequency of the PLL when locked. 16 18 Lowpass O/P: Output of the lowpass filter. The cut-off frequency is the same as the highpass filter. 7 19 Bandpass O/P: Output of the bandpass filter. fo is identical to the input frequency to the PLL when locked. Gain in passband is dependent on Q. 18 20 Notch O/P: Output of the notch filter, fo, is the same as the bandpass filter. 19 2 VCO /P: Input of the VCO control voltage, usually connected to loop filter output. 20 22 ft _: This pin is connected to V__ via an external resistor R _(R_, see Figure7). The value sets the maximum frequefity of operation of the VCO"See Figures 9(a) and (b). 21 23 PCIi O/P: Output of the edge-triggered type of phase comparator. See Note on PLL operation. 22 24 V,,: Positive supply. 3,9 No Connection: Leave open circuit.

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3V to 7.0V Input voltage at any pin (ref Ves = OV) =0.3V to (Vo + 0.3V) Output sink/source current (total) 20mA Operating temperature range: FX406J 30°C to + 85°C FX406LG -30°C to + 70°C Storage temperature range: FX406J - 55°C to + 125°C FX406LG 40°C to + 85°C Maximum device dissipation: All versions 100mW Operating Limits Typical characteristics measured using the following parameters unless otherwise specified: Voo=5V, Tamb= 25°C, PLL input = 1kHz, _ filter Q = 0.707. Limits specified over the full operating temperature and working voltage range. “haracteristics See Note Min Typ Max Unit Static Characteristics Supply voltage 45 5.0 55 OV Supply current - 45 85 mA Input impedance (Filter & Clock Osc) 1.0 - - ma Output impedance (Filter Outputs) = - 10 ka Output impedance (Clock Output) - - 10k Input impedance (Po, PQ, PQ,) 260 - - ko Output impedance (7, output) — - 50 ka Input logic ‘1” 70% Voo - = v Input logic ‘0’ - - 30% Vo V Filter Characteristics Maximum cutoff frequency 4.0 5.0 = kHz Minimum cutoff frequency - 50 100 Hz Gain at f, (fg) (HP BP LP) - 20 log Q - dB Notch filter depth 1 - -30 - 48 Notch accuracy 1 = 40.5% fo - Hz Maximum signal handling 2 3.0 - - Vp-p No signal filter noise (BP) _ 6.0 - mVrms (LP HP N) - 3.0 - mVims VCO Characteristics -\\ VCO maximum frequency 3 40 5.0 - kHz VCO minimum frequency 3 - 50 100 Hz VCO input impedance 1.0 - - Ma Phase Comparator Characteristics Input impedance 100 500 - ka Input sensitivity 4 30 10 - mVrms Output impedance PCI 5 ~ - 15 ka PCr - - 15 ko Amplifier Characteristics (Clock Oscillator and Filter inputs) Open loop gain 40 - = 4B Input offset voltage = - 10 mv Maximum signal handling 2 3.0 - - Vp-p Notes: 1. Q = 8. 2. For SINAD = 30dB at output. 3. VCO frequency divided down at f, output. 4. At PLL input pin, ac coupled, 5. Output impedance when conducting, output is high impedance three-state when PLL is in lock.

Typical Filter Frequency Responses ‘20. fo = 100 Hz, Q = 8.0, Vz = 3V p-PK, Voo = 8V i \\ +10 m4 ‘ AN : ) “10 ° ~i2 Zr iN 8-18 =10 “2 | 2 | | 1.Q=80 | aeal | 1 -2 za = 49 = | 3. = 1.0 -B ] ii | -2. 7 “oT 0.2 os 1 2 5 10 mar) 02 0s 1 2 5 10 Mo tite Fig. 2. Bandpass Frequency Response for different Fig. 3. Notch Frequency Response Q Values +20 +2 0. NN ©. Van ~~ -10. =10 8 hoses \\ 8 J Lo-se ~ 2 20-40 \\ =2 J 2a = 49 a= 19 £0 = om] 4.0 = 0.707] - -m. -» or oz oY 510 or 02 o 1 2 5’ 10 fife tite Fig. 4 Lowpass Frequency Response for different Fig. 5 Highpass Frequency Response for different Q Values Q Values

PC4060 PCB For Design Evaluation To assist in customer's design evaluation of the FX406, a PCB is available to enable external components to be connected for easy evaluation of application circuits. ° ° A i K3 Se a r “4 4 as ot | al ak | on De dk <5 fi S i fa (2! NTF Sy Wa — “ ead conan oppo heels oa ° S pcan —-2 O nee poets ov wre Fig. 6(a) Track Side Fig. 6 (b) Component Side Fig. 6 PC4060 Printed Circuit Board Yoo Yoo. mM! 1 Vas Yoo vhs PO, 6 [te itn Ves. ' f zy ny Wa, & Ey Wa Be ne io t & 3 2» on ! ry. 19} 1 oc, J] es 1e| NOTCH [oe ok Se 7 408 gf te, nm vady Ral s| > 9 14) Ryy re oe Py Gemee Beh ryt Cy oer R, ¢, Ray Ru am Om wm oo ox L be, So d Py Voo Pw Yoo rewaneune #82 FS PSSavGF Fast 55 5 z Em 8 Fig. 6 (c) PC4060 Printed Circuit Board Schematic Diagram

External Component Connections The following examples of external component connections illustrate the basic modes of operation of the FX406. ‘Where component references are used, these are the same as the circuit references on the PC4060 Evaluation PCB. Yoo. ce i i, tow U iP $5 Sco lts 3 f> lett] : . aa bet fea] b3 | Ves rah ©, c> jo 3 FILTER O/P —a) fr 4 edad ° if va Ver fiLTER 11 O—A Fig. 7 Example 1 we Cy Re —Using PCI with lag loop filter —VCO range set using Rin (Ry7 ) and f,4, potential divider (R,, R.) —Filter input with simple gain adjustment —Clock input pre-filtered with 2nd order LPF. Yoo. Note: formula for frequency of 1 & Aetie eat(YR, CaLogylt+2 Bi) +2x10"

1 Colog, (1+ +2x

“ve stem Le a I o 4

42 Vee ay

Pie | ade Va 7 > _ at =a 7 vnf bl im “h—9 fa | 3 | Ve oti Ru a, 9 18 — © "4 id Fitter [> FILTER rue c.. 8 > =3 Vves ul vedo & ie Vis Fig. 8 Example 2 jc, —Using PCII with a lead-lag loop filter —VCO range set using variable R,,,,,(VR3) —Filter input with anti-aliasing clock filter Ves —Clock input using Astable oscillator with frequency adjustment

Note 1 — Setting VCO Frequency Range. Set faa,” of VCO by selecting R,., using graph in Fig. 9(a) & 9(b). If Phase comparator Tis being used, it is also possible to set f,,, of the VCO by using the network shown in Fig. 9(c). R,,, may be determined using the graph in Fig. 9(c). *Frequencies shown in graphs are actually fyco/ 128. 7 i _ 5 z RB 4 & ° | 5 | gS, |

1 H 3 Hi H

VCO INPUT (vee) Fig. Sta] VCO Conversion Gain Curves For Different Values of Rmax (R17) 2tr-y A SS A AS SS RS A SS Se | 3 a 19- |S SO SO p+ 4-f 4 a | FS a a | pt hare ee Hs ee ee eo oe roo N =SccSS=== @ a guL tk 3% Pet a e fio. a SS | a a i iy a pe el eo oo eo é PS | PEE SS SS 2 oo oe on eo ee |

1 SS SS A Oe

i? ve 20°24 28 392 «36 «40 44 48 82 ae He) Fig. 9{b) VCO fmax Versus Rex Curve 1000: i ! LOOP wo © veo, i teal

8 Por

or 02 03 04 05 08 07 08 09 10 $i nan Fig. 9c} Rmin Versus Ratio fmin/tmex

Note 2 — Loop Filter Design Note 3 — Phase Comparators In order to maintain a fixed phase relationship The following table shows the principal characteristics between the VCO and reference input (or clock) ‘of second order loops using phase comparator I ("EX- signals, a ‘second order loop’ must be established. OR’) with a ‘lag’ filter and phase comparator II (edge- This is achieved by placing a lowpass filter between triggered) using a ‘lead-lag’ filter the phase comparator output and the VCO control input This filter may be a ‘lag’ filter, (Fig.10a)or for improved PCL PCr stability a ‘lead-lag’ filter, (Fig10b). Input duty cycle 50% optimum don’t care a a Locks on harmonics Yes No of wanted signal cul Noise rejection Good Poor Vi cm Vout Vie] Vout Rey Ripple at 2 x f,, on Yes Low loop filter output Fig. 10a) ‘Lag’ Filter ‘Fig. 10(b) ‘Lead-Lag’ Filter} Lock range, 2f, Fpax—f min Frrax—fug The overall loop gain is given by Ky. Kz Kyeo- Kyiv Capture range, 2. 1 \\/ Ke KeoRay nt ‘max! Jo Tt a Where: MS : phase comparator gain in vols/radian. Frequency of VCO frnaxt in rin r= . ney ot frmax= Feri, Kyco = VCO conversion gain in radians/sec-volt, ‘°F "° signe! input 2 Kg = divider gain in radians/radian (I/128). Phase angle between 0° at Fin 0° f _ Selection of the frequency at which the loop gain is \\ eaend F veo! 128 in oo Brno unity (0dB) depends on the application, the unity gain * La frequency should be high enough to allow the loop to track expected variations of the reference frequency — Anti but low enough to provide a ‘flywheel’ action to Note 4 — Antraliasing the switched average noise and unwanted input transients. capacitor sampling clock inthe FX406 is fog = 64, This type of sampled filter produces alias or image ‘Some typical loop filter component values for the responses centred on half the sampling rate, i.e., 32f,, FX406 using phase comparator If are tabled below. fog [R= TBKQ Filters with passbands extending beyond 32f, will Unity’gain R R have spurious responses reflected into the passband at frequency (Hz) a corresponding distance below 32f,. 50 92k tu If the input frequency spectrum to the filter is likely to 100 39k ta contain components at these alias frequencies then an 250 200k ow additional RC filter is required to attenuate these 500 16k Oty inputs. This is easily accomplished by using the filter input amplifier, Fig. 11 shows a 2nd order 5kHz lowpe filter with passband gain suitable for values of f, When using phase comparator I, the loop filter above 250Hz. frequency response may be used to limit the capture range of the loop, that is the range of input Ry frequencies that the loop will lock onto. This property — Rie 47kQ. may be used to provide a degree of selectivity if Ay, Re | 100Ka required. The following table shows filter component cH} Ine | Ri. | 100k2 values for various capture ranges. It should be noted Ce c. 560,F that the loop filter used here is the simple ‘lag’ filter ¢ c 1800F (i.e. Ry = 0), this is to minimise ripple at 2 x fj, on " c. O.1yF the loop filter output which would cause frequency Vous modulation of the switched capacitor filter response. Fig. 11. Anti-Aliasing Filter ore *e [| | (Hay (FI Special Note 100 ‘470k | 340n Care must be taken when using the FX406 with f, 200 took | 390n below 200Hz as the aliasing frequencies lie within the 500 100k 68n specified minimum passband of the filter. 1000 100k 15 On the highpass fitter only, an additional lowpass 2000 100k | 3.90 response exists with its — 3dB point at 7f, and a roll-off of 20dB/decade.

Specific Application Notes Component Noo References F [over | i Vea] vy, Ry 24K ! 2 y Rig | 39k of ] Ris 6 é 1% 1 oh ete tel ete |e seenotes °7 > Tolerance & I, al MUP» LF» tress + 5% O13 Ves ad] 2 2 1. gine wave . 11¥ss 4 | = : Ry Mss. Ves, Note? Gy can be omitted for TTL or Fig. 12 Pulse to Sine Converter CMOS logic level input signals Component | Yoo. References “ [vom | vee | 'ss] Re 200k _ oa Mo Ro 100k 1 2 ! Ry 2k of % Re 0k 2. | Ry aK 6 FI 19. 0 Gs Rs 1% 4 thet] ag roa | oe |e Vos ye4 1.04 i 2 he 7 Cs 1.08 | Ten ; 2 a} ! Vs Tolerance | ‘eacseticy *L] ie 18, Ad resistors + 5% FREQUENCY b — * | ruten E>——9 Capacitors + 20% | > — gine wave ° 115s 4) ' ol nat ce oT on Vee Fig. 13 tkHz Sine Wave Oscillator

Specific Application Notes... continued Tolerance Component Gy Ali resistors + 5% v, AG ‘Capacitors +20% References sl --S. We -—----~----, Unit i 2 ; Volvo — — of ] Rr 180k | ‘ ‘ ns = b = 1%. ge Ree | 1% taf =] mo | [Ps Ry 1.8K ° 4 [fs wl aM 7 ree Cy. Cy 1.04 i a Ves Cy 47n N ‘ wo ° -——3 COSINE WAVE O/P 3 > paren Fe crn wae je # ves Wh tg hhh Vis Qe13t I TRIANGLE WAVE 0/ Fig. 14 Function Generator Moo Tolerance Component Gy Allresistors + 5% po! Capacitors 20% References Mss: 9 ’ Cy Rig R 100k ° + o Ry Tt > [r= a ae | tte ‘ S 204 vz Ry 2k tur |_| a mm | i a, ag] 4 FI [Jr Re | 6m “an FP) | me | Som " \\ ry | tak 3 ‘ss Cy, Cy 1 SIGNAL. Yr vw! . c sg INPOT g > oS c Ce | Ow Te 9 yve_ _ ds 1 aoyust p~ To#— —c0e — —! SSET S/N THRESHOLD CAN RC, SET DERESPONSE TIME ra - ——_| oe co KF EH po") > Lae Te a 2 19] Serer > RB \\ Sis ve Notes: 1. Adjust gain R, for largest fiter output without clipping. 2, Vary R, to give Yzat point 8. 3. Set R, for threshold. . , ; 4. Set C, for de response time. Fig. 15 Voice Operated Switch et se

Specific Application Notes... continued Moo, Component References & Velve lh ~ | A io ser fro tao: Of 7 Ry 24k “ d 19 c n |e th GbE EE Rie 18x in [Jen Ry tae | oh [Pe Be oF [re [) vay 100k as lb aa FD 4 GC, 1.04 6 Fa {rea _ Ie ue | Am Ve f (] Se ou ° 2 wh V, Voleranoe ©; urea 3 All resistors + 5% > [--—— peal Capacitors + 20% d 6 : aes hehe ---to«“* Ci a=1.0 Ves [ee ra: a Pod Pr om) DATA UP Fig. 16 150 Baud FSK Modulator 100bp.s1 Te SYNCH 0/? x2 Component References Tolerance Yoo All resistors +5% Re 200k Capacitors +20% i Ro 130k Vee me | Zam Ry 1.8K roa ate VR 50k 4 D Ser Jo gm CC | 1.0 & 2 S18) gpl ehhh ast © Cc} [ a | | r. peli =e DATAOTP * 7 eo FSK INPUT °. | Vss “y=600Hs I+ {30100 me) _ 4 a Vos | pas EST S= Ter CI % bs dd 3 & = a=40 in Vss Fig. 17 150 Baud FSK Demodulator %

Package Outlines Handling Precautions The FX406 is available in the package styles outlined ‘The FX406 is a CMOS LSI circuit which includes input below. Mechanical package diagrams and specifications —_ protection. However precautions should be taken to are detailed in Section 10 of this document. Prevent static discharges which may cause damage. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. FX406J —22-pin cerdip DIL (J3) FX406LG = 24-pin quad plastic encapsulated bent and cropped (L1) NOT TO SCALE NOT TO SCALE a | RR AS a \\ \\\\ | Z S Max. Body Length 27.38mm || Max. Body Length 10.25mm Max. Body Width 9.75mm, | Max. Body Width 10.25mm

Ordering Information

FX406J 22-pin cerdip DIL (J3) FX406LG = 24-pin plastic encapsulated bent and cropped (L1) (CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied {and CML reserves the right at any te without notice to change the sid reuty