FX365

FX365 CMLMICRO | Alldatasheet

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CML Semiconductor Products PRODUCT INFORMATION puP Compatible CTCSS Encoder/Decoder Publication D/365/5 October 1991 Features/Applications Provisional Issue @ CTCSS Encoder/Decoder @ ‘No Tone’ Facility @ Serial/Parallel P Interface @ HF Filters on Inputs @ 38 Programmable Tones @ On-Chip Analogue Switching © Separate Rx/Tx Audio Paths @ Low Power 5V CMOS @ HP Filter for Rejection of CTCSS Tone © Xtal Controlled Tones and Prefiltering of Tx Audio @ Meets EIA RS220(B)/MPT1306 @ Low Falsing with Noise Inputs @ Choice of DIL or Surface Mount @ Tx Phase Reversal Facility Package Styles xraecook —P>o- Er Fig. 1 FX365 Internal Block Diagram vo : > = To ann: AY yd See eu — a, ‘Sema Tt 1] Semone FX365 ERIN. CLOCKS or ee | Re | °, a ee ee weroneous

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| Lae Lowe] Yoo * ue —— ree “<] ——— | ecovecouanaronner él econ covenestonie r> Brief Description The FX365 is a CMOS LSI device intended for use The tone encoder has a phase reversal facility, the as aCTCSS Encoder/Decoder in radio tone decoder and speech path high pass filter have communications systems. Designed specifically separate inputs and both are protected against the for microprocessor controlled multichannel effects of incident RF voltages. The speech path equipment, the FX365 incorporates a number of filter has low passband ripple, low output noise and advanced features which improve performance a cut-off frequency of 300Hz regardless of the and facilitate system design. The tone frequency to programmed CTCSS tone. be encoded or decoded, the transmit enable Separate Rx and Tx audio paths are provided for command and the monitor receiver audio prefiltering of Tx audio and rejection of the CTCSS. command may all be entered via an 8-bit port anda tone in Rx mode. load/latch pulse. Alternatively, the programming The FX365 uses a 1MHzcrystal reference information may be entered via a serial data port oscillator, a single 5-volt supply; and the choice of anda data clock. The device has anew tone DIL or SMT packages makes it suitable for fixed or decoder design which reduces false decode portable equipment. outputs due to noise to insignificant levels.

FX365J | FX365LG | FX365LS 1 1 1 Vpp: Positive Supply. 2 2 2 Xtal/Clock 1/P: Input to on-chip inverter used with a 1MHz Xtal or external clock source. 3 3 3 Xtal: Output of on-chip inverter (clock output) 4 4 4 Load/Latch: Controls 8 on-chip latches ands used to latch Rx/Tx, PTL, Do-Ds. This pinis internally pulled to Vpp. A logic 1’ applied to this input puts the 8 latches in ‘transparent’ mode. A logic ‘0’ applied to this input puts the 8 latches in the ‘latched’ mode. In parallel mode data is loaded and latched by a logic 1—> O transition (see Fig. 4). In serial mode data is loaded and latched by a 0-+1—+0 strobe pulse on this pin (see Fig. 5). 5 5 5 D,/Serial Enable 1: Data input Ds (in parallel mode). A logic't’ applied to this input together with a logic '0' applied to D./SERIAL ENABLE 2 will put the device in ‘Serial mode’ (see Fig. 5). This pin internally pulled to Voo. 6 6 6 D,/Serial Enable 2: Data input D, (in parallel mode). Alogic ‘0’ applied to this input together with a logic ‘1’ on pin 5 will place the device in ‘serial mode’ (see Fig. 5). This pin internally pulled to Vo. 7 7 7 D,/Serial Data: Data input D, (in parallel mode). In serial mode this pin becomes the serial data input for Ds—Do, Rx/Tx, PTL (see Fig. 5). Dg is clocked first and PTL last. This pin internally pulled to Vop. 8 8 8 D,/Serial Clock: Data D. (in parallel mode). In serial mode this pin becomes the serial clock input. Data is clocked on the positive going edge (see Fig. 5). This pin is internally pulledto Vo. 9 9 9 D,: Data D, (in parallel mode). This pin internally pulled to Vop. 10 10 10 Dg: Data Do (in parallel mode). This pin internally pulled to Voo. 1" W "1 Ves: Negative supply. 12 12 12 Decode Comparator Ref (UP): This pins internally biased to Voo/3 OF 2Vpp/3 via 1MQ resistors depending on the logical state of the TONE DECODE O/P pin. TONE DEC 0/P=1 will bias this input to 2Vo0/3, a logic’0' willbias this input to Vpo/3. This input provides the decode comparator reference voltage, and switching of bias voltages provides hysteresis to reduce ‘chatter’ under marginal conditions. 13 13 13 Rx Tone Decoder (O/P): Gated output of the decode comparator. This output is used to gate the Rx Audio path. A logic ‘0’ on this pin indicates a successful decode and indicates that the ‘decode ‘comparator input' pinis more positive than the ‘decode comparator ref input (see Table 2).

FX365) | FX365LG | FX365LS 4 14 4 Decode Comparator Input: This is the inverting input of the decode comparator. This pinis to be connected to the Rx TONE DETECT pin viaan external integrator (see Figs. 2 & 3). 15 15 15 Rx Tone Detect (0/P): In Rx mode this pin will go to logic 1 during a successtul decode (see Table 2). This pinis normally connected to the Decode Comparator input via the external integrator circuitry, as shownin Figs. 2 & 3. 16 16 16 Tx Tone O/P: A low impedance emitter follower stage for sourcing the | CTCSS sinewave under the control of the Rx/Tx pin. This O/P when not transmitting atone may be biased to Voo —0.7V or O/C (see Table 2), 17 17 7 Rx/TX: This input (in parallel mode) selects Rx or Tx modes (see Fig. 2). In serial mode this function is serially loaded. This pinis internally pulled to Vop via a 1M(2 resistor. 18 18 18 PTL: Inparalle! Rx mode this pin operates asa ‘press tolisten’ function by enabling the Rx audio path thus overriding the tone squelch function. In parallel! Tx mode this pin reverses the phase of the. transmitted CTCSS tone (squelch tail elimination). In serial mode this function is serially loaded (see Fig. 3). The phase reversal function should be applied by timing circuit to ensure correct system operation 19 19 19 Rx Audio Out: Thisis the high pass filtered “Receive” audio output pin. This pin outputs audio when Rx TONE DECODE =0, or PTL=1 or NOTONE is programmed (see Table 2). In Tx mode this pinis biased toVop- 20 20 20 Tx Audio Out: This is the high pass filtered “Transmit” audio output pin. In Tx mode this pin outputs audio present at the ‘Tx AUDIO INPUT pin. In Rx mode this pinis biased to Voo. 21 21 a Bias: This pinis the output of an internally generated Voo bias level and would normally be externally decoupled toVesviaCs. 2 22 22 22 ‘Tx Audio VP: This is the Tx Audio input pin. In Tx mode audio may be prefiltered, using the Tx audio path, thus helping to avoid talkoff due to intermodulation of speech frequencies with the transmitted CTCSS tone. The Tx audio path may also be used to prefilter speech when using scramblers which introduce noise in the low frequency band. This pins internally biased to Von. 23 23 23 Rx Audio Input: This is the input to the audio high pass filter in Rx mode. This pins internally biased to Voo. 24 24 24 Tone Input: Thisis the input to the CTCSS tone detector and is internally biased to Vop.

External Component Connections Yoo NOTE2 cy c, + T 2a] 4} __ tone ue 2 23) fe /-—— Rx AUDIO UP NOTE? xo G l 22| 34} txaupiowr wo? on Co 4) BIAS LOADILATCH 4 AL Mss Vss py 5 20) TxAUDIOOP b « FX365J RRAUDIOOP Ds 7 18} PTL * [$+ : " wn DO, 9 16| fe TONE O/P Re TONE pa bd 4 uw. Pro FT DECODECOMP./P- Ves 2 13 Vss Fx TONE DECODE OP Fig. 2 Parallel Wired Application Unit Unit [comvonent | vaiue | Note] [comrenent] vate | note Ri 1M Cs Otm Ro 820k Cy 1.00 Ry 330k C, Ot c 68p Ce 1.0. Co 33p 0, ‘small signal Cs Otm X; {MHZ Ca Op NOTES: Tolerances: Resistors + 10%. Capacitors +20% 2. Cyis used for power supply decoupling. 1. Xtal circuitry shownis in accordance with CML. Depending on application further filtering may Application Note D/XT/1 April 1986. be required. Table 1 Component References and Values NOTE2 cy o : Fy) 4} —— toneve 23 * RxAUDIOUP Ca 3 22 |H/_- txauniove Ves — 4 21 Cay) BIAS LOADAATCH Ly. Voo ‘Ss — a Tehupooe

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Input Pin—Condition | Output Pin-Condition Result/Function i _ Decode RxTone Tone Tone TxTone TxAudio Tone Rx Audio | OD, AXTK PTL Comp Detect Decode Transmitter Phase Path Decoder Path Input Enabled Reversed Enabled Enabled _ Enabled Tone 0 0 x 0 7 Yes No Yes No No(bias)| 1a Tone 0 1 Xx 0 1 Yes Yes Yes No No (bias)) 1b Notone 0 x x 0 1 No(bias) x Yes No No(bias)} 2 Tone 1 0 0 0 1 No(o/c) x No Yes No(bias)| 3a Tore 1 1 0 Cy) 1 No(olc) x No Yes Yes | 3b | Tone 4 x 1 1 0 No(olc) x No Yes Yes | 4 Notone 1 x x x 0 No(olc) x No Yes _Yes_| 5 Notes: ta. Normal tone transmit condition. 1b. Tone transmit with phase reversed. 2. ‘NOTONE programmed in Tx mode, tone transmit O/P set to Voo/2-0.7V. Tx audio path enabled. 3a. Normal decode standby. 3b. Normal decode standby with PTL used to enable audio. 4, Normal decode of correct CTCSS tone’ condition, PTL has no effect. 5. ‘NOTONE ' programmed in Rx mode, tone transmit O/P (o/c), Rx audio path enabled. Table 2 Truth table defining combinations of input/output conditions. Nominal __FX365 Programme Inputs Freq.Hz Frequency Af,% Do Dy D, D, Ds Ds 67.0 67.05 +.07 1 1 1 1 1 1 19 71.90 0.0 1 1 1 1 1 0 74.4 74.35 -.07 0 1 1 1 1 1 770 76.96 =.05 1 1 1 1 t) t) 79.7 79.77 +.09 1 ° 1 1 1 1 825 82.59 +.10 0) 1 1 1 1 0) 85.4 85.38 =.02 0 CY) 1 1 1 1 88.5 88.61 +13 0 1 1 1 0 t) 91.5 91.58 +.09 1 1 0 1 1 1 94.8 94.76 =.04 1 CY) 1 1 1 ° 97.4 9729 -0.11 0 1 0 1 1 1 100.0 99.96 =.04 1 0 1 1 0 0) 103.5 103.43 -.07 ° 0 1 1 1 0 107.2 107.15 —.05 0 0 1 1 t) 0 110.9 110.77 =412 1 1 0 1 1 0 114.8 114.64 =14 1 1 0 1 0 0 1188 118.80 0.0 0 1 0 1 1 0 123.0 122.80 -A7 0 1 0 1 ° 0 1273 127.08 -17 1 0 0 1 1 0 131.8 131.67 =10 1 0 ° 1 t) 0 136.5 136.61 +.08 0 0 0 1 1 0 141.3 141.32 +02 0 0 0 1 0 0 146.2 146.37 +12 1 1 1 0 1 0 151.4 151.09 -.20 1 1 1 0 0 0 156.7 156.88 + 0) 1 1 0 1 0 1622 162.31 +.07 0 1 1 0 t) 0 1679 168.14 +14 1 0 1 0 1 0 1738 173.48 =19 1 0 1 ° 0 0 179.9 180.15 +14 0 0 1 0 1 0 186.2 186.29 +.05 0 0 1 0 0 0 192.8 192.86 +.03 1 1 0 0 1 0 203.5 203.65 +.07 1 1 0 0 0 0 210.7 210.17 -.25 0 1 0 0 1 0 218.1 218.58 +22 0 1 0 0 0 0 225.7 226.12 +18 1 0 0 ° 1 0 233.6 234.19 +.25 1 0 0 ° 0) 0 241.8 241.08 -.30 t) 0 0 0 1 0 250.3 250.28 ~01 0 0 0 0 0 0 Notone ——_Notone - C) 0 0 0 1 1 Serial Input Mode x x Clock Data 0 1 Table3 Tone programming Truth table

Parallel and Serial Mode Timing Diagrams i wennneccneennnneee | Des, au Pale PTL, x wenn enecenne eet + ~—t Por LOADMATGH moore prom rnrrrnseeccecennnnceccnccss (Note) (ote) H — — tsp : Note: For wired, non microprocessor, applications load/latch should be connected to Voo | timin=400ns tspmin=400ns Fig. 4 Parallel mode timing diagram Tenney, TTT | SERIAL H ENABLE H Teene a | pocnncnnnnnnnnnnnnnnnnennnnnnnnnnnnnnan nnn nnnnnnnnnnnnnnnnnanenennnnen nee — et a H H Hi 4 DATA H SY u nn one , _ SERIAL H Hi CLOCK { H i fo, H H tse} i sore U ocor mera pocen ncn cena senna trnnmmnnnnnnnennnal frome nnn nn rnnnc ene . P< H DON'T CARE ! -1M2. PULLUP H to, CARE a a Se a aa aaae! ‘she H DONTTCARE } -1Ma PULLUP 44 i i H H H H H i. ~ aae, H H H " Loap/ ’ H t i i LATCH H H i } ue tl= min 400nS A H — i+ t= min400nS H H if how ti= — min400ns LATCHED tc= min 400ns | 4 4h | tss= min 400ns LOAD DATA LATCHDATA tw= min400ns tl= min 400ns te= min 400ns Note 1: Serial bit 1 through bit 8= Ds, Dz, Ds, Dz, Ds, Do, Rx/Tx and PTL respectively. Load bit 1 first , bit 8 tast. Fig. 5 Serial mode timing diagram

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is notimplied. Supply voltage -0.3V to 7.0V Input voltage at any pin (ref Vss=0V) =0,3V to (Vop+0.3V) Output sink/source current (total) 20mA Operating temperature range: + FX365J -30°C to +85°C FX365LG/LS -30°C to +70°C Storage temperature range: FX365J 55°C to +125°C FX365LG/LS —40°C to +85°C Maximum device dissipation B00mw Derating 10mwrc Operating Limits All device characteristics are measured under the following conditions unless otherwise specified: Vop = 5.0V. Tye = 25°C. OdB ref: = 300mVrms. Composite Signal = OdB 1kHz Tone, -12dB Noise (band-limited 6kHz aussian white noise), -20dB f, CTCSS Tone. Characteristics See Note Min. Typ. Max. Unit Static Characteristics Supply Voltage 45 50 55 v Supply Current {(h - 35 - mA Tone input peda = $8 = ua ‘one Input Impedance - r = 12 Audio Input Impedance - 10 - MQ Audio Output Impedance - 1.0 - kQ Digital input Impedance 1 ~ 1.0 = Ma Input Logic “1” 1 35 = = Vv Input Logic “0” 1 = - 15 v Logic “1” Output 1' source = 0.1mA 2 40 - = v Logic "0" Output 1° sink = 0.1 mA 2 - - 1.0 v Dynamic Characteristics Decoder Decode input Signal Level 3 -20 - - 6B Decode Response Time 36 = - 250 ms De-Response Time 36 - - 250 ms Decode Selectivity 3 205 - 33.0 %, Encoder ‘one Output Level relative 77SmiVrms) 39 0 5 3B ‘one Frequency Accuracy ({, error) ; - +03 % Risetime to 90% \\nortnad Sutput) ° {> 100Hz 4 - 55.0 - ms f < 100Hz 4 - 70.0 - ms Tone OutpufLoad Current - - 5.0 mA Total Harmonic Distortion - 20 5.0 % Qutpu Level Variation Between Tones - O41 - 4B Audio Filter Total Harmonic Distortion 5 - 2.0 5.0 % Output Noise Level Input a.c. Short Cet, Audio Switch Enabled - ~49.0 ~45.0 oe Gut Of frequency = 300 = Hz Bandpass Ripple (300Hz ~3000Hz) 5 1.0 = +10 0B Stopband Attenuation <250Hz 5 36.0 40.0 - 0B Passband Gain (ref. 1kHz) - 0 - 8 Audio Switch Isolation 5 - 60.0 - B Serial/Parallel inputs Paralol Set-Up Timo (to) 7 400 - - ns Load/Latch Pulse Widti (t,) 7 400 - - ns Serial Clock Pulse Wiath (t,) 7 400 = = ns Serial Set-Up Time (t,,) 7 400 - - ns Serial Clock Frequency 7 - 10 =. MHz Notes — 1. Refers to Rx/Tx, PTL, Decode Comparator Input, D,, D,, D,, Dy, Dy, Dy, 2. Alllogic outputs. 3. Composite Signal Test Condition. 4. Any programme tone and RL = 6002. CL = 15pF. Includes response to a phase reversal instruction. 5. tkHz reference = OdB. 6. {,.> 100Hz, (for 100Hz >f,>67Hz: t= (100/f, Hz) x 250ms). 7. See Figures 4 and 5.

Packaging Outlines Handling Precautions The FX365J, the cerdip package, is illustrated The FX365J/LG/LS is a CMOS LSI circuit in figure 6. The ‘LG’ version is shown in which includes input protection. However, figure 7, and the ‘LS’ version in figure 8. precautions should be taken to prevent static To allow complete identification, the FX365 LG discharges which may cause damage. and ‘LS' packages have an indent spot 7 adjacent to pin 1 and a chamfered corner Fig.7_ FX36SLG Package between pins 3 and 4. Pins number eee a he anti-clockwise when viewed from the top | {indent side). = al Sy tf vo oe mer Bo i Fig.6 FX365J Cerdip DIL Package 5 TESTy aL neni ager] om ene

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Ordering Information as cred FX365J 24-pin cerdip DIL a FX365LG —24-pin quad plastic encapsulated, bent and GO — cropped §\\ J Boe — “gi FX365LS _24-lead plastic leaded chip ae Tig" carrier ‘Atdimensions in mm. Angles in degrees, a 1040 97 F085 ous 8 os 10 G05 1080 ° 1.35.45" * oss i ta? 3 a7 225 e 230 kaa ar ‘CML does not assume any responsibilty lor he use any crcutry descrbed. Nocieut patenticences are mpled and ‘GML reserves the rightat any time without noice to change the saldcncuitry