FX013

FX013 CMLMICRO | Alldatasheet

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Technical content

CML Semiconductor Products PRODUCT INFORMATION FX013 HSC Tone Decoder for ‘Pagers Obsolete Product Features - For Information Only - @ 'N'-Tone HSC Decoding @ Radiopaging, PMR Selcall and @ ElAand CCIR Tonesets Remote Signalling Applications @ 4-Bit Parallel (HEX) Data Output © Selectable 560kHz or 4.48MHz Xtal/Clock Operation @ Processor interface - © Auxiliary 23.33kKHz Clock Output © Automatic Power-Up Reset Facility © Low-Power (2.5V @ 5001A,,, ) @ 24-Pin/Lead Package Versions Requirement TAR er an __] OATA CHANGE ve aeNoRY Soke _s | wm | FXO13 [ron [ROTH ae Fe | OLD — XTAUCLOCK, coms __iag cock zaaad OF Fig.1 Functional Block Diagram Brief Description The FX013is a very low-voltage continuous The FX013 has on-chip automatic Power-Up Reset “N’-Tone EIA and CCIR HSC tone decoder which is circuitry, which with selected time-constant ideal for tone-paging applications. components ensures the correct start-up settings for From an analogue signal input the FX013 will Most supply conditions, making this device ideal for produce a representative 4-bit (HEX) paraliel output installation within radiopaging units. word for either toneset. Hold, Data Change and Operating at 2.5 volts with a minimum current Interrupt features combined with the 4-bit data output requirement of 500uA, the FX013 is available in two enable Processor interface and control. Altematively, toneset versions to decode either EIA (A) or CCIR (C) the FX013 may be used in a simple passive system tones. . - - using the Data Change and Data Outputs. To cater for variations in design requirements the This can be used with a cu: . fied FX013 is produced in both 24-pin cerdip DiL and Processor or with a pre-programmed address Plastic quad packages. decoderidisplay driver.

3 Signal In: HSC input tones are a.c. coupled to this pin; de bias of the internal high gain limiter is set up by an internal 3MQ bias resistor connected between this pin and the Signal Bias pin. Neither pin should be loaded with any other circuitry. 5 Signal Blas: See Signal In. 7 23.33kHz Clock Out: A 23.333kHz buffered squarewave logic output directly derived from the oscillator frequency (nominally 560.0kHz). This pin may be used for auxiliary functions, e.g. external timing of received tone periods and for other '03 series devices. 8 Xtal: Output from on-chip inverter. 9 Xtal/Clock: Input to on-chip inverter. May be used in conjunction with the Xtal O/P and a 560kHz ceramic resonator/trimming capacitor, or a 4.48MHz Xtal Circuit. May also be used with a buffered input from an externally derived 560kHz or 4.48MHz clock. 10 560kHz Buffered O/P: A buffered 560kHz signal is output from this pin. "1 Clock Frequency Select: Normally at logic “1” if a S60kHz resonator is being used. If held at logic “0,” a divide by 8 function is switched in after the oscillator circuit to divide down the 4.48MHz frequency to 560kHz. This pin has an internal 1MQ pullup resistor. 12 Vee? Negative Supply (GND).

13 Hold UP: If taken to V,, and a tone is input, the resulting Data Change output latches to logic

“7” and the Data lines output the code for the detected tone regardless of subsequent changes to the input tone, until Hold is retumed to V,,,.. This facilitates interrup/handshake routines for hProcessors when used in conjunction with the Data Change O/P. This pin has an internal 1MQ pullup resistor.

4 Power-Up Reset (P U RS): To reset internal circuitry on power-up, a logic “1” is required at

this pin for a duration of at least 1.0ms after clock is applied. For slow-rising supplies the time constant recommended by the components in Figure 2 should be increased accordingly. 15 IRQ: Interrupt Request. This output, is latched to logic “O” when a tone is detected and the CS pin is at V,,, i.e. chip disabled. This pin is reset to logic “1,” enabling its for use in wire-ORing with similar outputs from other peripherals. This pin has internal 1kQ pulldown and 1002 pullup resistors on-chip. 16 CS: Chip Select. When this pin is at V,., the chip is disabled and the data outputs DO - D3 and Data Change output go open circuit. When at V,, the chip is enabled and the IRQ output is reset to logic “1.” 17 Data Change: A 1.0 ms pulse is generated at this pin upon detection of a valid tone and new data is presented to the DO - D3 outputs. The signal from this pin can be latched at a logic “1” after detection of a tone (see Hold input). This output is tri-state.

19 D3 Data Outputs: A 4-bit word, that represents the HEX value of the decoded tone

20 2 frequency, is output from these pins after a successful decode. 22 01 These outputs are tri-state. See Table 1. 23 Do 24 Voo! Positive Supply 1,2, 4,6, | | Not connected. Leave open-circuit. 18, 21

Application Information

' | Ce | es : Hi i I vi ' | ' 1 24 k= y CG i IGNAL IN 2 23 po * +t ee | SIGNAI ih —Amecose | rsa 22 ° yee recent 4 21 c, SIGNAL 5 20 pe zosccntz op |& FXOIs 19 03 7 18 TAL 8 17 |——> Data CHANGE IL XTAL/CLOCK 9 16 fod cane tek 10 15 Ra (LOCK SELECT "1 14 PURS Veo 12 13 HOLD R, | Ves Fig. 2 Recommended Extemal Components Component Value R, 1MQ c, 47.0pF R, 1MQ C, 5- 65pF c, 0.01pF Cc, 47.0pF c, 0.001 nF c, 1.0nF x, S60kHZ Tolerance: R=+10% C=+20% Input Tone Frequencies (Hz) Binary Coded Output Quadradecimal Data F013 A FXOI3.C D3 b2 D1 DO Character (BIA) (cciR) 600 1981 0 0 0 0 ° 71 1124 0 0 o 1 1 882 1197 0 o 1 0 2 1023 1275 o o 1 4 3 1164 1368 o 1 0 0 4 1305 1446 o 1 0 1 5 1446 1540 o 41 1 = 0 6 1587 1640 o 4 414 7 1728 1747 1 0 0 0 8 1869 1860 1 0 0 1 9 2151 2400 1 0 1 0 A 2433 930 1 0 1 4 B 2010 2247 1 1 0 0 c 2292 991 en D 459 2110 1 41 10 E Notone Norone 1 4 404 F Table 1 Decode Frequency Tonesets

‘CLOCK os trese these c PuRs 7 —— > “ (otras) OF Toe DATA CHANGE /\\ /\\ J \\ J \\ <otrus > €toc Fig.3 Normal Timing Operation [not to scale] Timing Specification tun «2.0 = om iclnesr toe - 330 - ms or : te 05 - 10 ms > toc i ST tase 20.0 - 33.0 ms ome OXON KK ty 930 - 530 ms “thon farm 20m. ‘orm 7 - 120 us a a too 500 - > ps io, hea - = 250 ons Fig.4 HOLD Operation [not to scale] taao 205 - 340 ms tes > > 250s ton > + 100 ons. INPUT Valid Tone Notes: 1. 'E’is the start-up (power-up reset) trina condition. md 2. The state of D0/1/2/3 will NK represent the input frequency 7 present during and after Power- Ss ms, Up Reset (F [Notone] in the ne eee Figure 3 example). at, lon, Fig.5 CS and IRQ Operartion [not to scale]

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3 to 7.0V Input voltage at any pin (ref V,,= OV) -0.3 to (V,, + 0.3V) Sink/source current (supply pins) +/- 30mA (other pins) +1 20mA Total device dissipation @ Ty, 25°C 800mW Max. Derating 10mW/eC Operating Temperature (T.,,): FX013J/LG ~40°C to +85°C Storage temperature range (T,,): FXO13J/LG -55°C to +125°C Supply Voltage (Vj,) 25 55 Vat 25°C All device characteristics are measured under the following conditions unless otherwise specified: Vo =5:0V Top = ~40 to +85 °C. Xtal/Clock or ‘Clock In’ Frequency = 560kHz. Characteristics See Note Min. Typ. Max. Unit SaticVauesSSSOSCSC~<“<—SSS——CSSSTTCCCOSCSS —_ ‘Supply Voltage (V,.=0V) 25 : 55 v ‘Supply Current : 500 : HA Logic *1” Output (Source = 1 mA) 1 45 : : Vv Logic “0” Output (Sink = 1 mA) 1 - - 05 v Logic “1” Input Level 2 35 - - v Logic “0” Input Level 2 - : 15 v Oscillator Output Level Input Impedances Signal In : 1.0 - Mo Clock Select - 1.0 - MQ Hold VP - 1.0 - MQ Chip Select - 10.0 : Mo. Output Impedances Do - D3 : 1.0 : kQ Data Change - 1.0 : ka Oscillator Outputs : 10.0 - ka Dynamic Values Signal Input Range 3 35.0 : Voj/2 -mVms | Decode Bandwidth when P>0.995 QA 4 420.0 - : Hz ac 4 #10 - - % Not-Decode Bandwidth when P<0.03 QA 5 : : £60.0 Hz ac 5 - : +3.0 % Noise Response Rate (hours per F - F : F single character response with no input tone). QA 6 - 0.15 : Irour ac 6 : 40.0 : fnour Decode Response Time: Norone to Tone (F - F) 7 20.0 25.0 33.0 ms Tone to Notone, Tf (F - F) 7 33.0 : 53.0 ms Minimum inter-tone gap for “F” 8 15.0 : 28.0 ms Notes: 1. Pins 7, 8, 17 and 19, 20, 22 and 23. 2. Pins 13,14 and 16. 3. An ac coupled sine/squarewave. 5. All conditions of input SNR and amplitude with maximum Tp specified for the toneset. 6. Gaussian input noise, bandwith 6.0kHz, maximum input level corresponds to 1-digit code falsing rate. F = random single character. 7. Delay from change of input (tone applied/temoved) to change at Q0-Q8 outputs. 8. Included in',,. Minimum tone gap requirement for “Noone” recognition. Outputs = F after delay.

Package Outlines Handling Precautions The FX013U, the cerdip package is shown in The FX013 is a CMOS LSI circuit which includes Figure 6 and the 'LG' quad plastic version in Figure 7. _input protection. However precautions should be taken Pin 1 identification marking is shown on the to prevent static discharges which may cause damage. relevant diagram and pins on both package styles number anti-clockwise when viewed from the top (marked side). Fig.6 FX013J 24-pin cerdip Package Fig.7 FX013LG quad plastic Package r—: Be. Te tO al BO Eo Ree Bt Lo — + TORE colle Si iTiinee CTH nome Aten gn ent afer ar] ce DIMENSION MAX wn Lor a care! $ exnee Srmeny oat ie eae) 99 NOTE Adin nm “f . oii 2 & DIMENSION MAX. man ww H es 2 : ue Ge Ne : 2 ‘* é Be oie a «es = $ mo one oxtrm i = ot Fo Ee) rve a el a er po Flores, 4 we se y BP rnen® be “

Ordering Information

‘The FXO013 is available in two tonesets and two package styles: 'A’ = EIA Tones ‘C’=CCIR Tones Please order the correct toneset in the correct package. FX013J'A'/'C' 24-pin cerdip DIL FXO13LG'A'/'C' 24-pin plastic encapsulated bent and cropped (CML does not assume any responsibilty forthe use of any crcultry described. No circu patent icences are impiied and CML reserves the right at any tie without notice to change the sad creutry,