FX003

FX003 CMLMICRO | Alldatasheet

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—_ FX003 _Selective Call Publication D/003/4 February 1990 15-Tone Selcall Decoder CCIR, ZVEI, EEA, EIA Tone Sets Group Call and Data Capability » Processor Compatible Excellent Noise Performance High Dynamic Range

4 Bit Data Output Low Power CMOS

Few External Components On-Chip Oscillator Uses Low-Cost Resonator FOLB vp POWER UP SIGNAL are Fx003QZ FX0030E DATA fi TI oe FX0030A [sina see|——-« FX0030ZS cocks ee osc. vP (aE GENERATOR Lock 0/P 2.388 kHe Osc. o/P Fig. 1 Internal Block Diagram handshake routines with microprocessors and The FX003 is a CMOS OTC (Quadradecimal other data processing logic. Tone Coding) tone decoder which may be A ‘Power Up Reset’ (PURS) routine ensures used to decode Selcall tones in accordance all internal circuitry is correctly reset when with CCIR, ZVEI, EEA and EIA international power is first applied to the device. Following tone standards. ‘PURS’ the FX003 generates HEX ‘E’ (NO The FX003 detects an input frequency falling DATA CHANGE) which in turn is followed by within any of the fifteen tone channels a normal decode sequence. programmed on-chip and outputs the The on-chip inverter may be used with a hexadecimal tone number in 4-bit binary resonator to provide the 560 kHz master code. When a tone is detected, its 4-bit code clock for the device, or an external clock may is latched at the data outputs and a Data be used. A divided down buffered 23.33 kHz Change is generated. Failure to qualify any clock output is also provided for use with tone for a continuous period of 33 ms causes _ other ‘03 devices and trimming of the the output to be set to ‘Notone’ (16th logic 560 kHz resonator. state) and a Data Change strobe to be The FX003 is available in a number of pin generated. compatible versions, each version A DATA CHANGE output signals each change — programmed in accordance with the in the output code and can be used with the frequencies and bandwidths of a specified HOLD/ACKNOWLEDGE input to establish QTC toneset.

(See Figure 2) DLL. Chip Carrier | FX003*| FX102K FX202*K | *QC, QZ, QE, QA, OZS (see Note A) ; 1° 2 _ | 23.333 kHz Clock O/P: A 23.333 kHz buffered squarewave logic output | directly derived from the oscillator frequency (nominally 560.0 kHz). May | be used for auxiliary functions e.g. 560 kHz resonator trimming,external | timing of received tone periods and for other ’03 family products. 2 4 - | Xtal: Output from on-chip inverter. 3 6 - | Xtal/Clock: Input to on-chip inverter may be used in conjunction with Xtal \\ O/P and 560 kHz resonator or as a buffered input for an external clock | (nominally 560.0 kHz). 4 10 5 | VSS: Negative supply. i | 5 - 8 | Hold I/P: Active when at VSS. If hold is taken to VSS when the input tone | | changes it latches the next data change pulse at logic 1 until the Hold is | returned to VDD. This facilitates Interrupt/Handshake routines for micro- | processors when used in conjunction with the Data Change O/P. Tie to | VDD if not used. 6 - 9 | Power Up Reset: A logic 1 level of at least 1 ms duration is required at | this pin to reset internal circuitry on power-up. For slow-rising power | | supplies increase the time constant of the components shown accordingly. i 7&%16! 135 123 | Internally Connected/Open Circuit: Should be left open circuit. | 789 #6710 | 11:12 11:13 | | 14 15 14 15 i | 16 18 18 20 i | 20 21 23 24 | 22 23 26 28 | 25 27 | 8 = 16 i Data Change: A pulse is generated at this pin shortly after detection of a | | tone and new data being presented at the Q, — Q, outputs (see Figure 5 | | Timing Diagram). | 9 - 22 ‘ Q, | Data Outputs: A 4-bit word which | 10 | Q, | is output after a successful decode | ah) | Q, | and represents the Hex code for the | 12 Q,| decoded tone frequency. | | ~° | 13 19 25 | VDD: Positive Supply. | i 14 24 - | Signal Input: Audio selcall tones are a.c. coupled to this pin via a | | capacitor. D.C. bias of the internal high gain limiter is set up by connecting | this pin via a resistor to the bias pin. | 15 26 - | Signal Bias: These pins should not be loaded with any other circuitry. | i] 1 - - 3 | 93.333 kHz Osc 1/P FX102K/FX202*K: Interchip connections. | - 13 - | 93.333 kHz Osc O/P. | These pins should not be loaded with any external | - - 27 | Logic Signal |/P. circuitry. - 17 - i Logic Signal O/P FX003*D.I.L: internally connected. Note A: FX102K and FX202*K are sold as a pair, and represent the same circuit function as the FX003* D.I.L. device.

EXTERNAL COMPONENT CONNECTIONS (23.333 kHz) CLOCK 0/P 1 16] @ XTAL 2 15+-—{___}-4 SIGNAL BIAS See Fig. 4 | eens XTAL/CLOCK 3 14 exe [SIGNAL 1/P in vss FOB UP 4 FX003 13 voD 'M | 5 12 Q, vi PUR oo Ty 6 uy a, OUTPUTS 10n el7 10 Q, | (Hexadecimal Code) DATA CHANGE STROBE 0/P § 8 Q, Fig. 2 Dual-In-Line * QC, QZ, QE, QA, ZS @ No connection. Do not tie. DB In recommended value for C, Z, E and ZS versions. 2.2n recommended value for the A version. INTERCONNECTION OF .FX102K AND FX202*K I Fx003* i AND EXTERNAL COMPONENTS 1 (Fx102K) ' sou Sg Q, | INTERNAL INVERTER | INPUT, Qs | para i | 22M ip Q, | srw’s | 1 >o | Astin CTH, [Os ee or) zal | ER Ea [FB HP ara crane i een ere, ie 2 102K a 202K 3 zasaa ke Shp ery, ad TAL 560 ke re : | Fr XTAL/ Lock 1 nin) See Fig. 4 ‘on 5-50 Fig. 3 Chip Carrier Fig. 4. 560 kHz Resonator Circuit Character Tone Table Tone Frequencies (f) in Hz 00304 0030C 0030E 00302 0030ZS Output Code atc (EIA) (CCIR) (EEA) (ZVEN) (ZVELS) Q, Q, a, Q, Format Character 600 1981 1981 2400 2400 0 t) te) 0 0 741 1124 1124 1060 1060 i?) t) i) 1 1 882 1197 1197 1160 1160 0 () 1 0 2 1023 1275 1275 1270 1270 0 0 1 1 3 1164 1358 1358 1400 1400 0 1 0 0 4 1305 1446 1446 1530 1530 0 1 0 1 5 1446 1540 1540 1670 1670 0 1 1 (e) 6 1587 1640 1640 1830 1830 0 1 1 1 7 1728 1747 1747 2000 2000 1 0 0 0 8 1869 1860 1860 2200 2200 1 0 0 1 9 2151 2400 1055 2800 886 1 0 1 0 A 2433 930 930 810 810 1 0 1 1 B 2010 2247 2247 970 740 1 1 0 0 c 2292 991 991 886 680 1 1 0 1 D 459 2110 2110 2600 970 1 1 1 0 E NOTONE NOTONE NOTONE NOTONE NOTONE 1 1 1 1 F

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage ~0.3V to 7.0V Input voltage at any pin (ref VSS = OV) —0.3V to (VDD + 0.3V) Output sink/source current (total) 20mA Operating temperature range: FX003* } _ ano 0, FX102K/FX202K* 30°C to + 85°C Storage temperature: Fx003* _ ERO, 0, exrozk/rxzo2" 5B°C to 125°C Maximum device dissipation 100mWw *QC, QZ, QE, OA, AZS Operating Limits VDD = 5V, Ta = 25°C, @ = 560kHz, Af d = 0. All characteristics measured using the standard test circuit with the following test parameters, and is valid for all tones unless otherwise stated: — oo SSSSSSSSSSSSSSSSSSses Characteristic See Note Min Typ Max Unit ss Static Characteristics Supply voltage (VSS = OV) 3.3 5.0 5.5 v Supply current 500 yA Logic ‘1’ output | source = 0.1 mA 1 45 Vv Logic ‘0’ output | sink = 0.1 mA 1 0.5 Vv Logic ‘1’ input Level 2 3.5 Vv Logic ‘O’ input level 2 1.5 Vv Dynamic Characteristics Signal input range 3 0.1 VDD Vpk-pk Decode Bandwidth (P> 0.995) 4 QA 4a 20 +Hz ac 4b 1 +% QE 4c 1 +% Q2/0ZS 4d 2 +% Not-decode bandwidth (P< 0.03) QA 5 60 +Hz ac 5 3 +% QE 5 3 +% az/azs 5 45 +% Noise response rate (hours per F> F> F single character response with no input tone). QA 6 0.15 Hour ac 6 40.0 Hour QE 6 40.0 Hour Qz/aZzSs 6 1.0 Hour Decode response time: _ Notone to tone (F> F) 7 20 25 Tp ms Tone to notone, T, (F> F) 7 33 53 ms Min. intertone gap for ‘F’ 8 15 28 ms SSS Notes 5. All conditions of input SNR and amplitude with . maximum Tp specified for toneset. 1. Relates to output pins 1, 8, 9-12. 6. Gaussian input noise, bandwidth 6kHz, maximum 2 Relates to input pins 5 and 6. input level corresponds to 1-digit code falsing rate. 3. A led, sine/: F = random single character. 4. With minimum tone period (Tp) specified change at Q,- Q, outputs (see fig. 5). for toneset. P = decode probability: & Included in T,. Minimum tone gap requirement for (a), (c} SNR3 dB ‘notone’ recognition. Outputs = F after delay. (b), (d) SNR OdB (see fig. 5).

. |. PUR H i j fi ‘t,t a III KIX : : X [III : 7 Q, Trrt aN Nin TR jr nee, CORD, GEE i} rt ot | H ried | 1 ‘ DATA - As DATA1 DATA2 DATAN F 2 LRAT. ' : Tae 1 tt | DATA CHANGE Et 4 ‘ . t ‘ Troe I ee NOT DRAWN TO SCALE Fig. 5 FX003* Timing Diagram (See References) * QC, QZ, QE, QA, AZS Typical Performance References: T, Logic 1, >2ms T, > 33 ms & < 50 ms T, 33 ms (DATA E) T, 20 ms minimum (Tp MAXIMUM) T, 0.5 ms — 1.0 ms (DATA CHANGE) T. 1.0 ms (DATA CHANGE PULSE DURATION) T, > 50 us T, < 120 us + Q, — Q, will represent the input frequency present during and after PUR (shown as ‘F’ (Notone) in this example). tt After application of HOLD the next Data Change pulse will stay high until HOLD is removed according to timing shown.

The ceramic dual-in-line package of the FX003 The FX003 is a CMOS LSI circuit which is shown in Figure 6 and the chip carrier version _includes input protection. However, shown in Figure 7. For the D.I.L. package, the precautions should be taken to prevent static pins number counter-clockwise (top view) from 1 discharges which can cause damage. with reference to a notch as a guidance. For the chip carrier package, pins number counter- clockwise (viewed from above) from the long pad (pad 1). inches mm, Inches mm, sie ee eT Co77 19.86 Coa) toa Don 279 Dow tt

2001 O25 2008 1

F 0% 7ee a Foo 18 G 0.70 17.78 oo G 0.05 1.3, Homo ‘2% f 4902 Om t=: - _ tL fh . L pos a re . CUI « £ a : 4 — - 5 mt Qe Tet) sai Cua * QC, OZ, QE, QA, aZS * VERSIONS Qc :CCIR FX003* —16-pin Ceramic D.LL. Oe cea FX102K 28-pad Ceramic Chip Carrier OA : EIA FX202*K 2% id Ci ic Chip Carrier : 8-pad Cerami Hp arr QZS : Suppressed ZVEI Note: FX102K & FX202*K are available in pairs only. CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.