FP31QF WJCI | Alldatasheet

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Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM Product Features

  • 50 – 4000 MHz
  • 18 dB Gain @ 900 MHz
  • +34 dBm P1dB
  • +46 dBm Output IP3
  • High Drain Efficiency
  • Pb-free 6mm 28-pin QFN package
  • MTTF > 100 years

Applications

  • Mobile Infrastructure
  • CATV / DBS
  • W-LAN / ISM
  • RFID
  • Defense / Homeland Security
  • Fixed Wireless Product Description The FP31QF is a high performance 2-Watt HFET (Heterostructure FET) in a low-cost lead-free 28-pin 6x6 mm QFN (Quad Flatpack, No-Lead) surface-mount package. This device works optimally at a drain bias of +9 V and 450 mA to achieve +46 dBm output IP3 performance and an output power of +34 dBm at 1-dB compression. The device conforms to WJ Communications’ long history of producing high reliability and quality components. The FP31QF has an associated MTTF of a minimum of 100 years at a mounting temperature of 85°C. All devices are 100% RF & DC tested. The product is targeted for use as driver amplifiers for wireless infrastructure where high performance and high efficiency are required. Functional Diagram Function Pin No. Gate / RF Input 3 Drain / RF Output 19 Ground All other pins & backside copper Specifications DC Parameter Units Min Typ Max Saturated Drain Current, Idss mA 1170 Transconductance, Gm mS 590 Pinch Off Voltage, Vp (1) V -2.0 RF Parameter (2) Units Min Typ Max Operational Bandwidth MHz 50 4000 Test Frequency MHz 800 Small Signal Gain dB 18 Maximum Stable Gain dB 24 Output P1dB dBm +34 Output IP3 (3) dBm +46 Noise Figure dB 3.5 1. Pinch-off voltage is measured when Ids = 4.8 mA. 2. Test conditions unless otherwise noted: T = 25ºC, V DS = 9 V, IDQ = 450 mA, in a tuned application circuit with ZL = ZLOPT, ZS = ZSOPT (optimized for output power). 3. 3OIP measured with two tones at an output power of +18 dBm/tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the 3OIP using a 2:1 rule. Absolute Maximum Rating Parameter Rating Operating Case Temperature -40 to +85 °C Storage Temperature -55 to +125 °C DC Power 7.5 W RF Input Power (continuous) 6 dB above Input P1dB Drain to Gate Voltage, Vdg +14 V Junction Temperature +220° C Operation of this device above any of these parameters may cause permanent damage. Typical Performance (4) Parameter Units Typical Frequency MHz 915 1960 2140 2450 Gain dB 18 13.5 13 12 S11 dB -20 -20 -18 -18 S22 dB -12 -11 -24 -15 Output P1dB dBm +34 +33.8 +33.2 +33.5 Output IP3 (3) dBm +46 +46.8 +46.6 +46.8 Noise Figure dB 3.5 4.5 4.6 4.6 IS-95 Channel Power @ -45 dBc ACPR dBm +27.8 +27.3 W-CDMA Ch. Power @ -45 dBc ACLR dBm +25 Drain Voltage (5) V +9 Drain Current (5) mA 450 4. Typical parameters represent perform ance in an application circuit. 5. Empirical measurements showed optimal power performance at a drain voltage = 9 volts at 450 mA. Because the FP31QF is a discrete device, users can choose their own bias configuration. Performance may vary from the data shown depending on the biasing conditions. To achieve a minimum 1 million hours MTTF rating, the biasing condition should maintain a junction temperature below 160° C over all operating temperatures. This can be approximated by (drain voltage) x (drain current) x 17.5° C/W + (maximum operating temperature).

Ordering Information

Part No. Description FP31QF 2-Watt HFET (Leaded QFN Pkg) FP31QF-F 2-Watt HFET (lead-free/RoHS-compliant QFN Pkg) FP31QF-PCB900 870 – 960 MHz Application Circuit FP31QF-PCB1900 1930 – 1990 MHz Application Circuit FP31QF-PCB2140 2110 – 2170 MHz Application Circuit 28 27 26 25 24 23 22 8 9 10 11 12 13 14 GND GND DRAIN / RF OUT GND GND GND GND GND GND GATE / RF IN GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM Typical Device Data S-Parameters (VDS = +9 V, IDS = 450 mA, T = 25°C, calibrated to device leads) 0 0.5 1 1.5 2 2.5 3 Frequency (GHz) S21, Maximum Stable Gain vs. Frequency S21, MSG (dB) DB(|S[2,1]|) DB(MSG) 1.0 1.0-1.0 10.0 10.0 -10.0 5.0 5.0 -5.0 2.0 2.0 -2.0 3.0 3.0 -3.0 4.0 4.0 -4.0 0.2 0.2 -0.2 0.4 0.4 -0.4 0.6 0.6 -0.6 0.8 0.8 -0.8 S11 Swp Max 6GHz Swp Min 0.01GHz 1.0 1.0-1.0 10.0 10.0 -10.0 5.0 5.0 -5.0 2.0 2.0 -2.0 3.0 3.0 -3.0 4.0 4.0 -4.0 0.2 0.2 -0.2 0.4 0.4 -0.4 0.6 0.6 -0.6 0.8 0.8 -0.8 S22 Swp Max 6GHz Swp Min 0.01GHz Note: Measurements were made on the packaged device in a test fixture with 50 ohm input and output lines. The S-parameters shown are the de-embedded data down to the device leads and represents typical performance of the device. Freq (MHz) S11 (mag) S11 (ang) S21 (mag) S21 (ang) S12 (mag) S12 (ang) S22 (mag) S22 (ang) Device S-parameters are available for download off of the website at: http://www.wj.com Load-Pull Data at 1.96 and 2.14 GHz (Vds = 8 V, Ids = 500 mA, 25°C, ZS = 50 Ω, calibrated to device pins) Freq (GHz) ZS (Ω) ZL (Ω) Gain (dB) P1dB (dBm) OIP3 (dBm) PAE (%) 1.96 5 + j0 8 - j2 18.5 +34 +48 49 2.14 5 - j2 8 - j3 18.0 +34 +48 50 1.0 1.0-1.0 10.0 10.0 -10.0 5.0 5.0 -5.0 2.0 2.0 -2.0 3.0 3.0 -3.0 4.0 4.0 -4.0 0.2 0.2 -0.2 0.4 0.4 -0. 0.6 0.6 -0.6 0.8 0.8 -0.8 P1dB Swp Max 1.96GHz Swp Min 1e-009GHz

1.96 GHz

1.0 1.0-1.0 10.0 10.0 -10.0 5.0 5.0 -5.0 2.0 2.0 -2.0 3.0 3.0 -3.0 4.0 4.0 -4.0 0.2 0.2 -0.2 0.4 -0. 0.6 0.6 -0.6 0.8 0.8 -0.8 Output IP3 Swp Max 1.96GHz Swp Min 1e-009GHz P1dB max (1.96 GHz) = +34 dBm at Z L = 8 - j2 Ω OIP3 max (1.96 GHz) = +48 dBm at Z L = 8 - j2 Ω 1 2

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM The application circuit is matched for output power. Typical RF Performance Drain Bias = +9 V, Ids = 450 mA, 25°C Frequency MHz 870 915 960 S21 – Gain dB 18.3 18 17.7 S11 – Input Return Loss dB -15 -20 -16 S22 – Output Return Loss dB -9.3 -12 -16 Output P1dB dBm +33.9 +34 +33.7 Output IP3 (+18 dBm / tone, 1 MHz spacing) dBm +46 Noise Figure dB 3.4 3.5 3.5 IS-95 Channel Power @ -45 dBc ACPR dBm +27.8 Circuit Board Material: .014” FR-4 (εr = 4.6), 4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper The main microstrip line has a line impedance of 50 Ω. Bill of Materials Ref. Desig. Value Part style Size C1, C4, C8, C10 100 pF Chip capacitor 0603 C2, C3 4.7 pF Chip capacitor 0603 C6, C11 0.018 µF Chip capacitor 0805 C7 1000 pF Chip capacitor 0603 C12 0.1 µF Chip capacitor 1206 L1, L2 27 nH Wirewound chip inductor 0805 L3 3.3 nH Multilayer chip inductor 0603 R1 10 Ω Chip resistor 0603 R2 51 Ω Chip resistor 0603 Q1 FP31QF WJ 2W HFET QFN 6x6 C5 Do Not Place

  • The C2 and C3 placements are at silk screen markers, “H” and “9.5”, respectively.
  • The via hole spacing along the main microstrip line is .040”.
  • The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
  • The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge. RES ID=

10 Ohm

ID= 100 pF IND ID= 27 nH CAP ID= 100 pF C10 CAP ID= 1.8e4 pF C11 CAP ID= 1e5 pF C12 CAP ID= 100 pF CA P ID= 1.8e4 pF CA P ID= 100 pF CAP ID= 1000 pF CAP ID= 4.7 pF IND ID= 27 nH RES ID=

51 Ohm

ID= DNP pF IND ID= 3.3 nH TL INP F0 = Loss= Eeff= Z0 = ID=

0 MHz

  1. 46 520 mil

50 Ohm

ID= 4.7 pF TL INP F0 = Loss= Eeff= Z0 = ID=

  1. 46 500 mil

NET= ID= "FP31QF" POR T

1 POR T

-Vgg Vds=9V @ 450 mA C2 C3

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM S11 vs. Frequency -30 -25 -20 -15 -10 860 880 900 920 940 960 Frequency (MHz) S11 (dB) -40c +25c +85c S21 vs. Frequency 860 880 900 920 940 960 Frequency (MHz) S21 (dB) -40c +25c +85c S22 vs. Frequency -30 -25 -20 -15 -10 860 880 900 920 940 960 Frequency (MHz) S22 (dB) -40c +25c +85c P1dB vs. Frequency 860 880 900 920 940 960 Frequency (MHz) P1dB (dBm) -40c +25c +85c Noise Figure vs. Frequency 860 880 900 920 940 960 Frequency (MHz) NF (dB) -40c +25c +85c ACPR vs. Channel Power IS-95, 9 Ch. Forward, ±885 kHz offset, 30 kHz Meas BW -70 -60 -50 -40 22 23 24 25 26 27 28 29 Output Channel Power (dBm) ACPR (dBc) -40 C +25 C +85 C freq = 915 MHz OIP3 vs. Temperature -40 -15 10 35 60 85 Temperature (°C) OIP3 (dBm) freq = 915, 916 MHz +18 dBm / tone IMD products vs. Output Power fundamental frequency = 915 MHz, 916 MHz; Temp = +25° C -100 -80 -60 -40 -20 4 8 12 16 20 24 28 Output Power (dBm) IMD products (dBm) IMD_Low IMD_High OIP3 vs. Output Power fundamental frequency = 915 MHz, 916 MHz; Temp = +25° C 4 8 12 16 20 24 28 Output Power (dBm) OIP3 (dBm) Output Power / Gain vs. Input Power frequency = 915 MHz, Temp = -40° C -4 0 4 8 12 16 20 Input Power (dBm) Gain (dB) Output Power (dBm) Output Power Gain Output Power / Gain vs. Input Power frequency = 915 MHz, Temp = +25° C -4 0 4 8 12 16 20 Input Power (dBm ) Gain (dB) Output Power (dBm) Output Power Gain Output Power / Gain vs. Input Power frequency = 915 MHz, Temp = +85° C -4 0 4 8 12 16 20 Input Power (dBm) Gain (dB) Output Power (dBm) Output Power Gain

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM The application circuit is matched for output power. Typical RF Performance Drain Bias = +9 V, Ids = 450 mA, 25°C Frequency MHz 1930 1960 1990 S21 – Gain dB 14 13.8 13.8 S11 – Input Return Loss dB -17 -21 -27 S22 – Output Return Loss dB -11 -11 -13 Output P1dB dBm +33.5 +33.8 +33.8 Output IP3 (+18 dBm / tone, 1 MHz spacing) dBm +46.8 Noise Figure dB 4.3 4.5 4.4 IS-95 Channel Power @ -45 dBc ACPR dBm +27.3 Circuit Board Material: .014” FR-4 (εr = 4.6), 4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper The main microstrip line has a line impedance of 50 Ω. Bill of Materials Ref. Desig. Value Part style Size C1, C4, C8, C10 22 pF Chip capacitor 0603 C2 2.2 pF Chip capacitor 0603 C3 2.0 pF Chip capacitor 0603 C6, C11 0.018 µF Chip capacitor 0805 C7 1000 pF Chip capacitor 0603 C12 0.1 µF Chip capacitor 1206 L1, L2 12 nH Wirewound chip inductor 0805 L3 4.7 nH Multilayer chip inductor 0603 R1 5.1 Ω Chip resistor 0603 R2 51 Ω Chip resistor 0603 Q1 FP31QF WJ 2W HFET QFN 6x6 C5 Do Not Place

  • The C2 and C3 placements are at silk screen markers, “B” and “3”, respectively.
  • The via hole spacing along the main microstrip line is .040”.
  • The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
  • The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge. RES ID=

5 Ohm

ID= 22 pF IND ID= 12 nH CAP ID= 22 pF C10 CAP ID= 1.8e4 pF C11 CAP ID= 1e5 pF C12 CAP ID= 22 pF CA P ID= 1.8e4 pF CA P ID= 22 pF CAP ID= 1000 pF CAP ID= 2 pF IND ID= 12 nH RES ID= ID= DNP pF IN D ID= 4.7 nH TL INP F0 = Loss= Eeff= Z0 = ID=

  1. 46 200 mil

ID= 2.2 pF TLINP F0 = Loss = Eeff = Z0 = ID= 3.46 190 mil NET= ID= "FP31QF" POR T -Vgg Vds=9V @ 450 mA C2 C3

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM S11 vs. Frequency -30 -25 -20 -15 -10 1930 1950 1970 1990 Frequency (MHz) S11 (dB) -40C +25C +85C S21 vs. Frequency 1930 1950 1970 1990 Frequency (MHz) S21 (dB) -40C +25C +85C S22 vs. Frequency -30 -25 -20 -15 -10 1930 1950 1970 1990 Frequency (MHz) S22 (dB) -40C +25C +85C P1dB vs. Frequency 1930 1950 1970 1990 Frequency (MHz) P1dB (dBm) -40c +25c +85c Noise Figure vs. Frequency 1930 1950 1970 1990 Frequency (MHz) NF (dB) -40c +25c +85c ACPR vs. Channel Power IS-95, 9 Ch. Forward, ±885 kHz offset, 30 kHz Meas BW -75 -65 -55 -45 -35 22 23 24 25 26 27 28 29 Output Channel Power (dBm) ACPR (dBc) -40 C +25 C +85 C freq = 1960 MHz OIP3 vs. Temperature -40 -15 10 35 60 85 Temperature (°C) OIP3 (dBm) freq = 1960, 1961 MHz +18 dBm / tone IMD products vs. Output Power fundamental frequency = 1960, 1961 MHz; Temp = +25° C -100 -80 -60 -40 -20 4 8 12 16 20 24 28 Output Power (dBm) IMD products (dBm) IMD_Low IMD_High OIP3 vs. Output Power fundamental frequency = 1960, 1961 MHz; Temp = +25° C 4 8 12 16 20 24 28 Output Power (dBm) OIP3 (dBm) Output Power / Gain vs. Input Power frequency = 1960 MHz, Temp = -40° C 2 6 10 14 18 22 26 Input Power (dBm) Gain (dB) Output Power (dBm) Output Power Gain Output Power / Gain vs. Input Power frequency = 1960 MHz, Temp = +25° C 2 6 10 14 18 22 26 Input Power (dBm) Gain (dB) Output Power (dBm) Output Power Gain Output Power / Gain vs. Input Power frequency = 1960 MHz, Temp = +85° C 2 6 10 14 18 22 26 Input Power (dBm) Gain (dB) Output Power (dBm) Output Power Gain

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM The application circuit is matched for output power. Typical RF Performance Drain Bias = +9 V, Ids = 450 mA, 25°C Frequency MHz 2110 2140 2170 S21 – Gain dB 13.2 13.3 13.1 S11 – Input Return Loss dB -17 -19 -16 S22 – Output Return Loss dB -14 -24 -18 Output P1dB dBm +33.6 +33.2 +33.3 Output IP3 (+18 dBm / tone, 1 MHz spacing) dBm +46.6 Noise Figure dB 4.7 4.6 4.9 IS-95 Channel Power @ -45 dBc ACPR dBm +25 Circuit Board Material: .014” FR-4 (εr = 4.6), 4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper The main microstrip line has a line impedance of 50 Ω. Bill of Materials Ref. Desig. Value Part style Size C1, C4, C8, C10 22 pF Chip capacitor 0603 C2, C3 2 pF Chip capacitor 0603 C6, C11 0.018 µF Chip capacitor 0805 C7 1000 pF Chip capacitor 0603 C12 0.1 µF Chip capacitor 1206 L1, L2 12 nH Wirewound chip inductor 0805 L3 4.7 nH Multilayer chip inductor 0603 R1 5.1 Ω Chip resistor 0603 R2 51 Ω Chip resistor 0603 Q1 FP31QF WJ 2W HFET QFN 6x6 C5 Do Not Place

  • The C2 and C3 placements are at silk screen markers, “A” and “2.5”, respectively.
  • The via hole spacing along the main microstrip line is .040”.
  • The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
  • The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge. RES ID=

ID= 22 pF IND ID= 12 nH CAP ID= 22 pF C10 CAP ID= 1.8e4 pF C11 CAP ID= 1e5 pF C12 CAP ID= 22 pF CA P ID= 1.8e4 pF CA P ID= 22 pF CAP ID= 1000 pF CAP ID= 2 pF IND ID= 12 nH RES ID= ID= DNP pF IN D ID= 4.7 nH TL INP F0 = Loss= Eeff= Z0 = ID=

  1. 46 180 mil

ID= 2 pF TLINP F0 = Loss = Eeff = Z0 = ID= 3.46 150 mil NET= ID= "FP31QF" POR T -Vgg Vds=9V @ 450 mA C2 C3

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM S11 vs. Frequency -30 -25 -20 -15 -10 2110 2130 2150 2170 Frequency (MHz) S11 (dB) -40c +25c +85c S21 vs. Frequency 2110 2130 2150 2170 Frequency (MHz) S21 (dB) -40c +25c +85c S22 vs. Frequency -30 -25 -20 -15 -10 2110 2130 2150 2170 Frequency (MHz) S22 (dB) -40c +25c +85c P1dB vs. Frequency 2110 2130 2150 2170 Frequency (MHz) P1dB (dBm) -40C +25C +85C Noise Figure vs. Frequency 2110 2130 2150 2170 Frequency (MHz) NF (dB) -40C +25C +85C ACPR vs. Channel Power 3GPP W-CDMA, Test Model 1 + 64 DPCH, ±5 MHz offset -60 -55 -50 -45 -40 -35 22 23 24 25 26 27 Output Channel Power (dBm) ACPR (dBc) -40 C +25 C +85 C freq = 2140 MHz OIP3 vs. Temperature -40 -15 10 35 60 85 Temperature (°C) OIP3 (dBm) freq = 2140, 2141 MHz +18 dBm / tone IMD products vs. Output Power fundamental frequency = 2140, 2141 MHz; Temp = +25° C -100 -80 -60 -40 3 6 9 1 21 51 82 1 Output Power (dBm) IMD products (dBm) IMD_Low IMD_High OIP3 vs. Output Power fundamental frequency = 2140, 2141 MHz; Temp = +25° C 3 6 9 1 21 51 82 1 Output Power (dBm) OIP3 (dBm) Output Power / Gain vs. Input Power frequency = 2140 MHz, Temp = -40° C 2 6 10 14 18 22 26 Input Power (dBm) Gain (dB) Output Power (dBm) Output Power Gain Output Power / Gain vs. Input Power frequency = 2140 MHz, Temp = +25° C 2 6 10 14 18 22 26 Input Power (dBm) Gain (dB) Output Power (dBm) Output Power Gain Output Power / Gain vs. Input Power frequency = 2140 MHz, Temp = +85° C 2 6 10 14 18 22 26 Input Power (dBm) Gain (dB) Output Power (dBm) Output Power Gain

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM Reference Design: 2400 – 2500 MHz The application circuit is matched for output power. Typical RF Performance Drain Bias = +9 V, Ids = 450 mA, 25°C Frequency MHz 2400 2500 S21 – Gain dB 12.1 12.0 S11 – Input Return Loss dB -13 -16 S22 – Output Return Loss dB -13 -17 Output P1dB dBm +33.5 Output IP3 (+18 dBm / tone, 1 MHz spacing) dBm +46.8 Noise Figure dB 4.6 The 2.4 – 2.5 GHz Reference Circuit is shown for design purposes only. An evaluation board is not readily available for this application. The reader can obtain any FP31QF evaluation board and m odify it with the circuit shown to achieve the performance shown in this reference design. Frequency (GHz) Measured S-Parameters -25 -20 -15 -10 (dB) Circuit Board Material: .014” FR-4 (εr = 4.6), 4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper The main microstrip line has a line impedance of 50 Ω. Bill of Materials Ref. Desig. Value Part style Size C1, C4, C8, C10 22 pF Chip capacitor 0603 C2, C3 1.5 pF Chip capacitor 0603 C6, C11 0.018 µF Chip capacitor 0805 C7 1000 pF Chip capacitor 0603 C12 0.1 µF Chip capacitor 1206 L1, L2 12 nH Wirewound chip inductor 0805 L3 3.3 nH Multilayer chip inductor 0603 R1 5.1 Ω Chip resistor 0603 R2 50 Ω Chip resistor 0603 Q1 FP31QF WJ 2W HFET QFN 6x6 C5 Do Not Place

  • The C2 and C3 placements are at silk screen markers, “A” and “2”, respectively.
  • The via hole spacing along the main microstrip line is .040”.
  • The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
  • The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge. CAP ID= 22 pF IND ID= 12 nH CAP ID= 22 pF C10 CAP ID= 1.8e4 pF C11 CAP ID= 1e5 pF C12 CAP ID= 22 pF CA P ID= 1.8e4 pF CA P ID= 22 pF CAP ID= 1000 pF CAP ID= 1.5 pF IND ID= 12 nH RES ID=

ID= DNP pF IN D ID= 3.3 nH TL INP F0 = Loss= Eeff= Z0 = ID= 3.46 180 mil ID=

5.1 Ohm

ID= 1.5 pF TLINP F0 = Loss = Eeff = Z0 = ID=

  1. 46 150 mil

NET= ID= "FP31QF" POR T -Vgg Vds=9V @ 450 mA C2 C3

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM Reference Design: 3500 MHz The application circuit is matched for output power. Typical RF Performance Drain Bias = +9 V, Ids = 450 mA, 25°C Frequency MHz 3500 S21 – Gain dB 11.9 S11 – Input Return Loss dB -16 S22 – Output Return Loss dB -8.8 Output P1dB dBm +33.5 Output IP3 (+18 dBm / tone, 1 MHz spacing) dBm +45 The 3.5 GHz Reference Circuit is shown for design purposes only. An evaluation board is not readily available for this application. The reader can obtain any FP31QF evaluation board and m odify it with the circuit shown to achieve the performance shown in this reference design. Frequency (GHz) Measured S-Parameters -25 -20 -15 -10 (dB) Circuit Board Material: .014” FR-4 (εr = 4.6), 4 layers (other layers added for rigidity), .062” total thickness, 1 oz copper The main microstrip line has a line impedance of 50 Ω. Bill of Materials Ref. Desig. Value Part style Size C1, C4, C8, C10 22 pF Chip capacitor 0603 C2 0.9 pF Chip capacitor 0603 C3 1.0 pF Chip capacitor 0603 C6, C11 0.018 µF Chip capacitor 0805 C7 1000 pF Chip capacitor 0603 C12 0.1 µF Chip capacitor 1206 L1, L2 6.8 nH Wirewound chip inductor 0805 L3 3.3 nH Multilayer chip inductor 0603 R1 2.2 Ω Chip resistor 0603 R2 50 Ω Chip resistor 0603 Q1 FP31QF WJ 2W HFET QFN 6x6 C5 Do Not Place

  • Both the C2 and C3 placements are between the first and second via locations along the main microstrip line leading from the FP31QF device. Further descriptions are shown in the diagram on the left.
  • The via hole spacing along the main microstrip line is .040”.
  • The distance from the edge of the FP31QF to the closer edge of L3 is .305”.
  • The transmission line lengths shown in the schematic are from the FP31QF device edge to the component edge. CAP ID= 22 pF IND ID= 6.8 nH CAP ID= 22 pF C10 CAP ID= 1.8e4 pF C11 CAP ID= 1e5 pF C12 CAP ID= 22 pF CA P ID= 1.8e4 pF CA P ID= 22 pF CAP ID= 1000 pF CAP ID= 1 pF IND ID= 6.8 nH RES ID=

ID= DNP pF IN D ID= 3.3 nH TL INP F0 = Loss= Eeff= Z0 = ID=

  1. 46 65 mil

ID= 0.9 pF TL INP F0 = Loss= Eeff= Z0 = ID= 3.46 30 mil ID=

2.2 Ohm

NET= ID= "FP31QF" POR T -Vgg Vds=9V @ 450 mA

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM Application Note: Constant-Current Active-Biasing Special attention should be taken to properly bias the FP31QF. Power supply sequencing is required to prevent the device from operating at 100% Idss for a prolonged period of time and possibly causing damage to the device. It is recommended that for the safest operation, the negative supply be “first on and last off.” With a negative gate voltage present, the drain voltage can then be applied to the device. The gate voltage can then be adjusted to have the device be used at the proper quiescent bias condition. An optional active-bias current mirror is recommended for use with the application circuits shown this datasheet. Generally in a laboratory environment, the gate voltage is adjusted until the drain draws the recommended operating current. The gate voltage required can vary slightly from device to device because of device pinchoff variation, while also varying slightly over temperature. The active-bias circuit, shown on the right, uses dual PNP transistors to provide a constant drain current into the FP31QF, while also eliminating the effects of pinchoff variation. This configuration is best suited for applications where the intended output power level of the amplifier is backed off at least 6 dB away from its compression point. With the implementation of the circuit, lower P1dB values may be measured for a Class-AB amplifier, where the device will attempt to source more drain current while the circuit tries to provide a constant drain current. The circu it should be connected directly in line with where the voltage supplies would be normally connected with the amplifier circuit, as sh own the diagram. Any required matching circuitry remains the same, although it is not shown in the diagram. This recommended activ e-bias constant-current circuit adds 7 components to the parts count for implementation, but should cost only an extra $0.144 to realize ($0.10 for U1, $0.0029 for R1, R3, R4, R5, $0.024 for R2, and $0.0085 for C1). Temperature compensation is ach ieved by tracking the voltage variation with the temperature of the emitter-to-base junction of the two PNP transistors. As a 1st order approximation, this is achieved by using matched transistors with approximately the same Ibe current. Thus the transistor emitter voltage adjusts the HFET gate voltage so that the device draws a constant current, regardless of the temperature. A Rohm dual transistor - UMT1N - is recommended for cost, minimal board space re quirements, and to minimize the variation between the two transistors. Minimizing the variability between the base-to-emitter junctions allow more accuracy in setting the current draw. More details can be found in a separate application note “Active-bias Constant-current Source Recommended for HFETs” found on the WJ website. Parameter FP31QF Pos Supply, Vdd +9 V Neg Supply, Vgg -5 V Vds +8.75. V Ids 450 mA R1 62 Ω R2* 0.56 Ω R3 2 kΩ R4 1 kΩ R5 1 kΩ *R2 should be of size 1206 to dissipate 0.113 Watts. This should be of 1% tolerance. Two 1.1 Ω resistors in parallel of size 0805 can also be used. 5 2 R1 R2 1 kΩ -Vgg +Vdd Rohm UMT1N RF IN RF OUT DUTM.N. M.N. .01 µF

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM FP31QF Mechanical Information This package may contain lead-bearing materials. The plating material on the pins is SnPb. Outline Drawing Mounting Configuration / Land Pattern Thermal Specifications Parameter Rating Operating Case Temperature -40 to +85 °C Thermal Resistance, Rth (1) 17.5 ° C/W Junction Temperature, Tjc (2) 156 ° C 1. The thermal resistance is referenced from the hottest part of the junction to the ground copper on the backside. 2. This corresponds to the typical drain biasing condition of +9V, 450 mA at an 85 °C case temperature. A minimum MTTF of 1 million hours is achieved for junction temperatures below 160 °C. Product Marking The component will be lasermarked with a “FP31QF” product label with an alphanumeric lot code on the top surface of the package. Tape and reel specificati ons for this part will be located on the website in the “Application Notes” section. ESD / MSL Information ESD Rating: Class 1C Value: Passes 1000V to <2000V Test: Human Body Model (HBM) Standard: JEDEC Standard JESD22-A114 ESD Rating: Class IV Value: Passes 1000V Test: Charged Device Model (CDM) Standard: JEDEC Standard JESD22-C101 MSL Rating: Level 1 at +250 °C convection reflow Standard: JEDEC Standard J-STD-020 Functional Pin Layout Pin FUNCTION

3 Gate / RF Input

19 Drain / RF Output

The backside paddle is the Source and should be grounded for thermal and electrical purposes. All other pins should be grounded on the PCB. MTTF vs. GND Tab Temperature 100 60 70 80 90 100 110 120 Tab Temperature (°C)

Specifications and information are subject to change without notice WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com November 2004 FP31QF 2-Watt HFET Product Information The Communications Edge TM FP31QF-F Mechanical Information This package is lead-free/RoHS-compliant. It is compatible with both lead-free (maximum 260°C reflow temperature) and leaded (maximum 245°C reflow temperature) soldering processes. The plating material on the pins is annealed matte tin over copper. Outline Drawing Mounting Configuration / Land Pattern Thermal Specifications Parameter Rating Operating Case Temperature -40 to +85 °C Thermal Resistance, Rth (1) 17.5 ° C/W Junction Temperature, Tjc (2) 156 ° C 1. The thermal resistance is referenced from the hottest part of the junction to the ground copper on the backside. 2. This corresponds to the typical drain biasing condition of +9V, 450 mA at an 85 °C case temperature. A minimum MTTF of 1 million hours is achieved for junction temperatures below 160 °C. Product Marking The component will be lasermarked with a “FP31QFF” product label with an alphanumeric lot code on the top surface of the package. Tape and reel specificati ons for this part will be located on the website in the “Application Notes” section. ESD / MSL Information ESD Rating: Class 1C Value: Passes 1000V to <2000V Test: Human Body Model (HBM) Standard: JEDEC Standard JESD22-A114 ESD Rating: Class IV Value: Passes 1000V Test: Charged Device Model (CDM) Standard: JEDEC Standard JESD22-C101 MSL Rating: Level 2 at +260 °C convection reflow Standard: JEDEC Standard J-STD-020 Functional Pin Layout Pin FUNCTION The backside paddle is the Source and should be grounded for thermal and electrical purposes. All other pins should be grounded on the PCB. MTTF vs. GND Tab Temperature 100 60 70 80 90 100 110 120 Tab Temperature (°C)