FMP3217BAX FIDELIX | Alldatasheet

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Technical content

Revision 0.3 Feb. 2007 Document Title 2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM

Revision History

Jun.01st ,2006Revised P/N according to the new P/N system0.2 Feb. 2nd , 2007Revised ISB1 to 120uA0.3 PreliminaryNov.10th ,2005Added G(Pb-Free) and H(Pb-Free & Halogen Free) descriptions Added Operating Temperature descriptions0.1 PreliminarySep.16th, 2005Initial Draft0.0 RemarkDraft dateHistoryRevision No.

Revision 0.3 Feb. 2007 2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM PIN DESCRIPTION 1 2 3 4 5 6 A B C D E F G H /LB /OE A0 A1 A2 I/O9 /UB A3 A4 /CS I/O10 I/O11 A5 A6 I/O2 VSS I/O12 A17 A7 I/O4 VCCQ I/O13 DNU A16 I/O5 I/O15 I/O14 A14 A15 I/O6 I/O16 A19 A12 A13 WE A18 A8 A9 A10 A11 /ZZ I/O1 I/O3 VCC VSS I/O7 I/O8 A20 48-FBGA : Top View(Ball Down) Core PowerVCCLow Power Modes/ZZ Do Not Use DNUData Inputs/OutputsI/O1~I/O16 Lower Byte(I/O 1~8)/LBAddress InputsA0~A20 Upper Byte(I/O9~16)/UBWrite Enable Input/WE GroundVSSOutput Enable Input/OE I/O PowerVCCQChip Select Input/CS FunctionNameFunctionName FUNCTIONAL BLOCK DIAGRAM Precharge circuit.Clk gen. VCC VSS Memory arrayRow Addresses I/O Circuit Column select Data cont Data cont Column Addresses Data cont Control Logic /CS /OE /WE /UB /LB /ZZ I/O9~I/O16 I/O1~I/O8 Row select

FEATURES

  • Process Technology : Full CMOS
  • Organization : 2M x 16
  • Power Supply Voltage : 2.7~3.3V
  • Low Power & Page Modes FMP3217BA1 : support the PASR/DPD function FMP3217BA2 : support the Direct DPD function FMP3217BA4 : support the PASR/DPD/PAGE function FMP3217BA5 : support the Direct DPD/PAGE function
  • Operating Temperature Ranges: Special (-10’C to +60’C) Commercial (0’C to +70’C) Extended (-25’C to +85’C) Industrial (-40’C to +85’C)
  • Three state output and TTL Compatible
  • Package Type : 48-FBGA-6.00x8.00 mm2 FMP3217BAx-FxxX : Normal FMP3217BAx-GxxX : Pb-Free FMP3217BAx-HxxX : Pb-Free & Halogen Free
  • Separated I/O power(VCCQ) & Core Power(VCC)
  • Page read/write operation by 16 words (FMP3217BA4, FMP3217BA5)
  • DPD mode by using MRS only (FMP3217BA1, FMP3217BA4)
  • Direct DPD mode when /ZZ goes low (FMP3217BA2, FMP3217BA5) PRODUCT FAMILY ISB1 (CMOS Standby Current) ICC2 ICC1 Max.Typ. 20mA Max.Typ. Max.Typ.Min. 120uA3.0 Typ.Max. 80uA15mA 12mA3mA1.5mA60ns 70ns3.32.7FMP3217BAx-H60E FMP3217BAx-H70E Operating Voltage (V) f = fmaxf = 1MHz Power Dissipation SpeedProduct Family 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER 3. Operating Temperature Range: S (-10’C~60’C),C(0’C~70’C),E(-25’C~85’C),I (-40’C~85’C)

Revision 0.3 Feb. 2007 PRODUCT LIST 48-FBGA, 60ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V) 48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V) FMP3217BAx-H60E FMP3217BAx-H70E FunctionPart Name ABSOLUTE MAXIMUM RATINGS1) ’C-65 to 150TSTGStorage temperature W1.0PDPower Dissipation V-0.2 to 3.6VccVoltage on Vcc supply relative to Vss V-0.2 to Vcc+0.3VVIN, VOUTVoltage on any pin relative to Vss UnitRatingsSymbolItem 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional ope ration should be restricted to recommended operating condition. Exposure to absolute maximum rati ng conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS -0.22) 0.8VCCQ 2.7 2.7 Min FMP3217BA 0.2VCCQ VCC+0.21) 3.3 3.3 Max -0.22) 0.8VCCQ 2.25 2.7 Min 0.2VCCQ VCC+0.21) 2.75 3.3 Max 1.95 V3.32.7VCCSupply voltage 0.2VCCQ VCC+0.21) Max V-0.22)VILInput low voltage V0.8VCCQVIHInput high voltage V0VSSGround V1.65VCCQI/O operating voltage (VCCQ ≤ VCC) Unit Min SymbolItem Note : 1. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 2. Undershoot : -1.0V in case of pulse width≤20ns. 3. Overshoot and undershoot are sampled, not 100% tested. FUNCTIONAL DESCRIPTION Direct DPD2)DeselectedHigh-ZHigh-ZX1)X1)X1)X1)LX1) ActiveWord WriteDinDinL L ActiveUpper Byte WriteDinHigh-ZLH ActiveLower Byte WriteHigh-ZDinHL LX1) ActiveWord ReadDoutDoutLL ActiveUpper Byte ReadDoutHigh-ZLH ActiveLower Byte ReadHigh-ZDoutHL HL HL ActiveOutput DisabledHigh-ZHigh-ZLX1)HHH ActiveOutput DisabledHigh-ZHigh-ZX1)LHHH L StandbyDeselectedHigh-ZHigh-ZHHX1)X1)HX1) Low Power Modes3)DeselectedHigh-ZHigh-ZX1)X1)X1)X1)LH StandbyDeselectedHigh-ZHigh-ZX1)X1)X1)X1)HH PowerModeI/O9-16I/O1-8/UB/LB/WE/OE/ZZ/CS 1. X means don’t care.(Must be low or high state) 2. In case of FMP3217BA2 & FMP3217BA5 product 3. In case of FMP3217BA1 & FMP3217BA4 product 1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER 2. Operating Temperature Range: S (-10’C~60’C),C(0’C~70’C),E(-25’C~85’C),I (-40’C~85’C)

Revision 0.3 Feb. 2007 DC AND OPERATING CHARACTERISTICS 1. Capacitance is sampled, not 100% tested. CAPACITANCE1) (f=1MHz , TA=25’C) Max Min pFVIO=0VCIOInput/Output capacitance pFVIN=0VCINInput capacitance UnitTest ConditionSymbolItem uA10--/ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD)ISB0 Low Power Modes uA90--/ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selectionISB0a uA100--/ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selectionISB0b uA120--/CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCCISB1Standby Current(CMOS) uA1--1/CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCCILOOutput leakage current uA1--1VIN=VSS to VCCILIInput leakage current mA3--Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH, VIN≤0.2V or VIN≥VCC-0.2VICC1 Average operating current V0.2VCCQIOL=0.5mAVOLOutput low voltage mA20--Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH, VIN=VIL or VIHICC2 V0.8VCCQIOH=-0.5mAVOHOutput high voltage 120 0.3 Max Typ Min uA/ZZ≤0.2V, Other inputs=0~VCC, All refresh area selectionISB0c mA/CS=VIH, /ZZ=VIH, Other inputs=VIH or VILISBStandby Current(TTL) UnitTest ConditionsSymbolItem -10℃ to +60℃SpecialFMP3217BAx-XxxS 0℃ to +70℃CommercialFMP3217BAx-XxxC -25℃ to +85℃ExtendedFMP3217BAx-XxxE 1.65V to Vcc2.7V to 3.3V -40℃ to +85℃IndustrialFMP3217BAx-XxxI VDDQVDDAmbient TemperatureRangeDevice Operating Range

Revision 0.3 Feb. 2007 AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level : 0.2 to VCC-0.2V Input rising and falling time : 5ns Input and output reference voltage : 0.5*VCCQ Output load(see right) : CL=30pF+1TTL AC CHARACTERISTICS(VCC=2.7V~3.3V) 30pf 1TTL ns20k-20k-tMRCMaximum Cycle Time Page ns-10-10tCP ns25-20-tPAAPage Mode Address Access Time ns-25-20tPCPage Mode Cycle Time /CS High Pulse Width ns-5-5tOWEnd Write to Output Low-Z ns-0-0tDHData Hold from Write Time ns-20-20tDWData to Write Time Overlap ns5050tWHZWrite to Output High-Z ns-0-0tWRWrite Recovery Time ns-50-50tWPWrite Pulse Width ns-60-50tBW/UB, /LB Valid to End of Write ns-60-50tAWAddress Valid to End of Write ns-0-0tASAddress Set-up Time ns-60-50tCWChip Select to End of Write ns20k7020k60tWCWrite Cycle Time Write ns-5-5tOHOutput Hold from Address Change ns5050tOHZOutput Disable to High- Z Output ns5050tBHZ/UB, /LB Disable to High- Z Output ns5050tHZChip Disable to High- Z Output ns-5-5tOLZOutput Enable to Low-Z Output 70ns ns-10-10tBLZ/UB, /LB Enable to Low-Z Output ns-10-10tLZChip Select to Low-Z Output ns70-60-tBA/UB, /LB Access Time ns25-25-tOEOutput Enable to Valid Output ns70-60-tCOChip Select to Output ns70-60-tAAAddress Access Time ns20k7020k60tRCRead Cycle Time Read MaxMinMaxMin 60ns Units Speed Bins SymbolParameter List 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.

Revision 0.3 Feb. 2007 Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 200us with /CS=V IH Standby Mode State machines Standby Mode Characteristics 090 (ISB0a)¼v a l i d 0100 (ISB0b)½v a l i d 20010 (ISB0)Invalid Low Power Modes 0120 (ISB0c)valid 0120 (ISB1)ValidStandby Mode Memory Cell Data Wait Time(us)Standby Current(uA) Initial State Standby Mode Active Mode Low Power Modes 1 (32M/16M/8M bits) Power On /CS=VIL /ZZ=VIH /CS=VIH (or/and /UB=/LB=VIH) /ZZ=VIH /CS=VIH /CS=VIH, /ZZ=VIL /CS=VIL, /ZZ=VIH /UB or/and /LB=VIL Low Power Modes 2 (Data Invalid) Wait 200us /CS=VIH, /ZZ=VIL /CS=VIH, /ZZ=VIL /CS=VIH /ZZ=VIL /CS=VIL /ZZ=VIH /CS=VIH, /ZZ=VIH

Revision 0.3 Feb. 2007 READ CYCLE (2) (/ZZ=/WE=VIH) 1. tHZ and tOHZ are defined as the ti me at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. Address tAA tCO tBA tOE tOH tOLZ tBLZ tLZ Data ValidHigh-Z tHZ tBHZ tOHZ /CS /UB, /LB /OE Data Out tRC READ CYCLE (1) (Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL) Address Data Out tRC Previous Data Valid Data Valid tAA tOH 1. tHZ and tOHZ are defined as the ti me at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 4. In case page address skew is over 3ns, tPAA will be out of spec. PAGE READ CYCLE (/ZZ=/WE=VIH, 16 words access) A0~A3 tAA tCO tBA tOE High-Z tHZ tBHZ tOHZ /CS /UB, /LB /OE Data Out tRC A4~A20 tOH tPC tPC tPC tPC tPC tPC tPC tPAA tPAA tPAA tPAA tPAA tPAA tPAA tLZ tBLZ tOLZ Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid tMRC

Revision 0.3 Feb. 2007 WRITE CYCLE (2) (/CS controlled, /ZZ=/WE=VIH) Address /CS /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2)tAS(3) tAW WRITE CYCLE (3) (/UB, /LB controlled, /ZZ=VIH) 1. A write occurs during the overlap (tWP) of lo w /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneou sly asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. Address /CS /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2) tAW tAS(3) WRITE CYCLE (1) (/WE controlled, /ZZ=VIH) Address /CS /UB, /LB /WE Data Out tWC tCW(2) tWR(4) tAW tBW tWP(1) tAS(3) High-Z High-Z Data Undefined Data Valid tDW tDH tOWtWHZ Data in

Revision 0.3 Feb. 2007 1. A write occurs during the overlap (tWP) of lo w /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneou sly asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 6. In case page address is over 3ns, write to the invalid address can occur. PAGE WRITE CYCLE (Address controlled, /ZZ=VIH) A4~A20 /CS /UB, /LB /WE Data Out tAS(3) High-Z Data Undefined Data Valid tDW tOW tWHZ Data in A0~A3 tWC tPC tPC tPC tPC tPC tPC tPC High-Z tDH Data Valid tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid tMRC

Revision 0.3 Feb. 2007 LOW POWER MODES 1. Mode Register Set A0A1A2A3A4A20 ~ A5 Array Refresh AreaHalf SelectionArray On/Off on /ZZ ZZ Enable/Disable0 /ZZ Enable/Disable DPD Disable (Default)1 Deep Power Down Enable0 TypeA4 Array On/Off on /ZZ Reduced Memory Size Mode1 Partial Array Refresh Mode (Default)0 TypeA3 Note: If the register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that /ZZ is driven low and there is no MRS update. When /ZZ is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, Deep Power Down Disabled). Note: The RMS(Reduced Memory Size) mode is enabled after /ZZ goes high and remains enabled after /ZZ goes high. To change to a different mode, the mode register will have to be rewritten. Half Selection (Top / Bottom) Top1 Bottom (Default)0 TypeA2 Array Refresh Area RFU10 ½A r r a y01 ¼A r r a y1 Full Array (Default)0 TypeA0 2. MRS Update Address /CS /UB, /LB /WE tWC tWR(4) tBW tWP(1) tCW(2)tAS(3) tAW /ZZ tZZWE Register Write Start Register Write Complete Register Update Complete The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a don’t care When /ZZ is low during the register updates.

Revision 0.3 Feb. 2007 16Mb1Mbx16100000h-1FFFFFh1/2101 8Mb512Kbx16180000h-1FFFFFh1/4111 32Mb2Mbx16000000h-1FFFFFhFull00X 16Mb1Mbx16000000h-0FFFFFh1/2100 8Mb512Kbx16000000h-07FFFFh1/4110 DensitySizeAddressRefresh SectionA1,A0A2 Partial Array Refresh Mode (A3=0, A4=1) Reduced Memory Size Mode (A3=1, A4=1) 3. Deep Power Down Mode Entry/Exit 4. Address Information tZZmin tR /CS /UB, /LB /WE tWC tWR(4 tBW tWP(1) tCW(2 tAS(3) tAW /ZZ tZZWE Register Write(DPD) Deep Power down start Deep Power down exit Next Cycle 16Mb1Mbx16100000h-1FFFFFh 1/2101 8Mb512Kbx16180000h-1FFFFFh1/4111 16Mb1Mbx16000000h-0FFFFFh 1/2100 8Mb512Kbx16000000h-07FFFFh 1/4110 DensitySizeAddressRefresh SectionA1,A0A2 us-10Low Power Mode TimetZZmin us-200Operation Recovery TimetR(Deep Power Down Mode only) us10ZZ low to Write Enable LowtZZWE UnitsMaxMinDescriptionParameter

Revision 0.3 Feb. 2007 PACKAGE DIMENSION 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View B C #A1 Bottom View Side View Detail A Unit : millimeters 0.08--Y 0.300.250.20E2 -0.85-E1 1.201.10-E 0.400.350.30D -5.25-C1 8.108.007.90C -3.75-B1 6.106.005.90B -0.75-A MaxTypMin- D C E 0.30 0.85/Typ. 0.25/Typ. Y NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) B C B/2 B1 0.05 0.05 A1 INDEX MARK 6 5 4 3 2 1 A B C D C1/2 E F G H A