FMP3216DAX

FMP3216DAX FIDELIX | Alldatasheet

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Technical content

2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM

Revision History

No. History Draft date Remark 0.0 Initial Draft A pr. 10, 2010 Preliminar yp, y 0.1 Removed Page Write Operation Jul. 14, 2010 Revision 0.1 Jul. 2010

2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM

FEATURES

• Process Technology : Full CMOS
• Organization : 2M x 16
• Power Supply Voltage 2.7V ~ 3.3V
• Three state output and TTL Compatible
• Separated I/O power(VCCQ) & Core power(VCC)
• Operating Temperature Ranges: Special (-10’C to +60’C) Commercial (0’C to +70’C) Et dd ( 25’C t 85’C)
• Package Type : 48-FBGA-6.00x8.00 mm2 FMP3216DAx-HxxX : Pb-Free & Halogen Free
• Low Power & Page Modes FMP3216DA1 : support the PASR/DPD function FMP3216DA2 : support the Direct DPD function FMP3216DA4 : support the PASR/DPD/PAGE function FMP3216DA5 : support the Direct DPD/PAGE function
• Page read operation by 16 words (FMP3216DA4, FMP3216DA5)
• DPD mode by using MRS only PRODUCT FAMILY Product Family Operating Voltage (V) Speed Power Dissipation ICC1 ICC2 ISB1 (CMOS Standby Current) Min. Typ. Max. f = 1MHz f = fmax Extended (-25’C to +85’C) Industrial (-40’C to +85’C) DPD mode by using MRS only (FMP3216DA1, FMP3216DA4)
• Direct DPD mode when /ZZ goes low (FMP3216DA2, FMP3216DA5) PIN DESCRIPTION 1 2 3 4 5 6 FUNCTIONAL BLOCK DIAGRAM Min. Typ. Max. FMP3216DAx-H60E FMP3216DAx-H70E 2.7 3.0 3.3 60ns 70ns 1.5mA 3mA 15mA 12mA 20mA 90uA 120uA 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. H=FBGA(Pb-Free & Halogen Free), W=WAFER 3. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) A B C D /LB /OE A0 A1 A2 I/O9 /UB A3 A4 /CS I/O10 I/O11 A5 A6 I/O2 VSS I/O12 A17 A7 I/O4 /ZZ I/O1 I/O3 VCC Precharge circuit.Clk gen. VCC VSS Memory arrayRow Addresses Row select E F G H VCCQ I/O13 DNU A16 I/O5 I/O15 I/O14 A14 A15 I/O6 I/O16 A19 A12 A13 WE A18 A8 A9 A10 A11 VSS I/O7 I/O8 A20

48 FBGA : Top View(Ball Down)

I/O9~I/O16 I/O1~I/O8 48-FBGA : Top View(Ball Down) Name Function Name Function /ZZ Low Power Modes VCC Core Power /CS Chip Select Input VCCQ I/O Power /OE Output Enable Input VSS Ground /WE Write Enable Input /UB Upper Byte(I/O9~16) A0 A20 Add I t /LB L B t (I/O 1 8) Column Addresses Control Logic /CS /OE /WE /UB /LB Revision 0.1 Jul. 2010 A0~A20 Address Inputs /LB Lower Byte(I/O 1~8) I/O1~I/O16 Data Inputs/Ou tputs DNU Do Not Use /LB /ZZ

Part Name FunctionPart Name Function FMP3216DAx-H60E FMP3216DAx-H70E 60ns, VCC=3.0V, VCCQ=3.0V 70ns, VCC=3.0V, VCCQ=3.0V FUNCTIONAL DESCRIPTION /CS /ZZ /OE /WE /LB /UB I/O1 8 I/O9 16 Mode Po er 1. H=FBGA(Pb-Free & Halogen Free), W=WAFER 2. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) /CS /ZZ /OE /WE /LB /UB I/O1-8 I/O9-16 Mode Power HH X 1) X1) X1) X1) High-Z High-Z Deselected Standby X1) LX 1) X1) X1) X1) High-Z High-Z Deselected Direct DPD 2) HL X 1) X1) X1) X1) High-Z High-Z Deselected Low Power Modes 3) LHHH X 1) X1) High-Z High-Z Output Disabled Active LH H H High-Z High-Z Output Disabled Active L H Dout High-Z Lower Byte Read Active LH H L High-Z Dout Upper Byte Read Active L L Dout Dout Word Read Active X1) L H H High-Z High-Z Write-abort 4) Active L H Din High-Z Lower Byte Write Active H L High-Z Din Upper Byte Write Active L L Din Din Word Write Active 1. X means don’t care.(Must be low or high state) 2. In case of FMP3216DA2 & FMP3216DA5 product ABSOLUTE MAXIMUM RATINGS1) p 3. In case of FMP3216DA1 & FMP3216DA4 product 4. Write data can’t be written to the memory cell.Item Symbol Ratings Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 to VCC+0.3V V Voltage on VCC supply relative to VSS VCC -0.2 to 3.6 V Power Dissipation PD 1.0 W 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be rest ricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS Power Dissipation PD 1.0 W Storage temperature TSTG -65 to 150 ’C Item Symbol FMP3216DAx Unit Note : Item Symbol Unit Min Typ Max Supply voltage VCC 2.7 3.0 3.3 V I/O operating voltage (VCCQ ≤ VCC) VCCQ 2.7 3.0 3.3 V Ground VSS 000 V Input high voltage VIH 0.8VCCQ VCCQ VCC+0.2 1) V Input low voltage VIL -0.22) 0 0.2VCCQ V Revision 0.1 Jul. 2010 1. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 2. Undershoot : -1.0V in case of pulse width≤20ns. 3. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE1) (f=1MHz , TA=25’C) It Sb l Tt Cd i t i Mi M Ui t DC AND OPERATING CHARACTERISTICS 1. Capacitance is sampled, not 100% tested. Item Symbol Test Condition Min Max Unit Input capacitance C IN VIN=0V - 8 pF Input/Output capacitance C IO VIO=0V - 8 pF Item Symbol Test Conditions Min Max Unit Input leakage current ILI VIN=VSS to VCC -1 1 uAInput leakage current ILI VIN VSS to VCC 1 1 uA Output leakage current I LO /CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC -1 1 uA Average operating current ICC1 Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH, VIN≤0.2V or VIN≥VCC-0.2V -3 m A ICC2 Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH, VIN=VIL or VIH -2 0 m A Output low voltage V OL IOL=0.5mA 0.2VCCQ V Output high voltage V OH IOH=-0.5mA 0.8VCCQ V St db C t(TTL) ISB /CS V IH /ZZ V IH Oth i t V IH VIL 03 AStandby Current(TTL) ISB /CS=VIH, /ZZ=VIH, Other inputs=VIH or VIL - 0.3 mA Standby Current(CMOS) I SB1 /CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCC - 120 uA Low Power Modes ISB0 /ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD) - 10 uA ISB0a /ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selection - 90 uA ISB0b /ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selection - 100 uA ISB0c /ZZ≤0.2V, Other inputs=0~VCC, All refresh area selection - 120 uA Operating Range Device Range Ambient Temperature VCC VCCQ FMP3216DAx-XxxS Special -10℃ to +60℃ 2.7V to 3.3V 2.7V to VCC FMP3216DAx-XxxC Commercial 0℃ to +70℃ FMP3216DAx-XxxE Extended -25℃ to +85℃ FMP3216DAx-XxxI Industrial -40℃ to +85℃ Operating Range AC Input/Output Reference Waveform NOTE: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns.

2 Inp t timing begins at VCCQ/2

Test Points VCCQ/23VCCQ/2 2 VCCQ VSS Input1 Output 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. AC Output Load Circuit DUT 50& Test Point VCCQ/2 Revision 0.1 Jul. 2010 30pF

AC CHARACTERISTICS(VCC=2.7V~3.3V)AC CHARACTERISTICS(VCC 2.7V 3.3V) Parameter List Symbol Speed Bins Units60ns 70ns Min Max Min Max Read Cycle Time tRC 60 20k 70 20k ns Address Access Time tAA - 60 - 70 ns Chip Select to Output tCO - 60 - 70 ns Read Output Enable to Valid Output tOE - 25 - 25 ns /UB, /LB Access Time tBA - 25 - 25 ns Chip Select to Low-Z Output tLZ 10 - 10 - ns /UB, /LB Enable to Low-Z Output tBLZ 10 - 10 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns C h i p D i s a b l e t o H i g h - Z O u t p u t t H Z 0505 n s /UB, /LB Disable to Hi gh- Z Outpu t t B H Z 0505 n sg p O u t p u t D i s a b l e t o H i g h - Z O u t p u t t O H Z 0505 n s Output Hold from Address Change tOH 5 - 5 - ns Write Cycle Time tWC 60 20k 70 20k ns Chip Select to End of Write tCW 50 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 50 - 60 - ns /UB /LB V lid t E d f W it tBW 50 60 Write /UB, /LB Valid to End of Write tBW 50 - 60 -n s Write Pulse Width tWP 50 - 50 - ns Write Recovery Time tWR 0 - 0 - ns W r i t e t o O u t p u t H i g h - Z t W H Z 0505 n s Data to Write Time Overlap tDW 15 - 15 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns Page Page Mode Cycle Time tPC 20 - 25 - ns Page Mode Address Access Time tPAA - 20 - 25 ns Maximum Cycle Time tMRC - 20k - 20k ns /CS High Pulse Width tCP 10 - 10 - ns 1. /CS High Pulse Width is defined by /CS. Revision 0.1 Jul. 2010

1. Apply Power 2. Maintain stable power for a minimum of 150us with /CS=/ZZ=V IH Standby Mode State machines Initial State Power On /CS=/ZZ=VIH Wait 150us /CS=VIH, /ZZ=VIH Initial State Active Mode /CS=VIL, /ZZ=VIH Wait 150us /CS=VIH, /ZZ=VIL Standby Mode Low Power Modes 1 (32M/16M/4M bits) /CS=VIL /ZZ=VIH /CS=VIH /ZZ=VIH /CS=VIH, /ZZ=VIL Low Power Modes 2 (Data Invalid) /CS=VIH /ZZ=VIL /CS=VIL /ZZ=VIH Standby Mode Characteristics /CS=VIH, /ZZ=VIL Mode Memory Cell Data Standby Current(uA) Wait Time(us) Standby Valid 120 (ISB1) 0 Low Power Modes Invalid 10 (ISB0) 150 ¼ valid 90 (ISB0a) 0 ½ valid 100 (ISB0b) 0 valid 120 (ISB0c) 0 Revision 0.1 Jul. 2010

READ CYCLE (1) (Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL) READ CYCLE (2) (/ZZ=/WE=VIH) Address Data Out tRC Previous Data Valid Data Valid tAA tOH Address tAA tCO tBA tOH tHZ tBHZ /CS /UB, /LB tRC 1. tHZ and tOHZ are defined as the time at which the outputs a chieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.

3 D t d i ith l ti i h t th tRC(tWC) f ti i d 20

/OE Data Out 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. PAGE READ CYCLE (/ZZ=/WE=VIH, 16 words access) A0~A3 tRC tPC tPC tPC tPC tPC tPC tPC tMRC tAA tCO tBA tHZ tBHZ /CS /UB, /LB A4~A20 tOH 1. tHZ and tOHZ are defined as the time at which the outputs a chieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. tOE High-Z tBHZ tOHZ /OE Data Out tPAA tPAA tPAA tPAA tPAA tPAA tPAA tLZ tBLZ tOLZ Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Revision 0.1 Jul. 2010 to de ce te co ect o 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 4. In case page address skew is over 3ns, tPAA will be out of spec.

WRITE CYCLE (1) (/WE controlled, /ZZ=VIH) tWC Address /CS /UB, /LB /WE tWC tCW(2) tWR(4) tAW tBW tWP(1) WRITE CYCLE (2) (/CS controlled, /ZZ=/WE=VIH) tWC Data Out tAS(3) High-Z High-Z Data Undefined Data Valid tDW tDH tOWtWHZ Data in Address /CS /UB, /LB /WE tWC tWR(4) tBW tWP(1) tDW tDH tCW(2)tAS(3) tAW Data Out High-Z High-Z Data Valid tDW tDH Data in WRITE CYCLE (3) (/UB, /LB controlled, /ZZ=VIH) Address tWC Address /CS /UB, /LB /WE tWR(4) tBW tWP(1) tDW tDH tCW(2) tAW tAS(3) 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the be ginning of write. Data Out High-Z High-Z Data ValidData in Revision 0.1 Jul. 2010 gg 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.

1. Mode Register Set A20 ~ A5 A4 A3 A2 A1 A0 0 ZZ Enable/Disable Array On/Off on /ZZ Half Selection Array Refresh Area /ZZ Enable/Disable A4 Type

0 Deep Power Down Enable

1 DPD Disable (Default)

0 Partial Array Refresh Mode (Default)

1 Reduced Memory Size Mode

N t If th i t i itt t bl th D Nt T h R M S ( Rd d M S i ) d i b ld f tNote: If the register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that /ZZ is driven low and there is no MRS update. When /ZZ is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, Deep Power Down Disabled). Note: The RMS(Reduced Memory Size) mode is enabled after /ZZ goes high and remains enabled after /ZZ goes high. To change to a different mode, the mode register will have to be rewritten. Half Selection (Top / Bottom) A2 Type Array Refresh Area A1 A0 Type

0 Bottom (Default)

1 Top

0 0 Full Array (Default)

01 R F U

10 ½ A r r a y 11 ¼ A r r a y 2. MRS Update Address /CS /UB, /LB tWC tWR(4) tBW tWP(1) tCW(2)tAS(3) tAW /WE tWP(1) /ZZ tZZWE Register Write Start Register Write Complete Register Update Complete Revision 0.1 Jul. 2010 The register update take place on the rising eDAe of /ZZ. Once the register is updated, the next time /ZZ goes low, without any updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a don’t care When /ZZ is low during the register updates.

3D P D Md Et / Ei t3. Deep Power Down Mode Entry/Exit /CS /UB, /LB tWC tWR(4) tBW tCW(2) tAS(3) tAW tZZmin tR /WE tWP(1) /ZZ tZZWE Register Write(DPD) Deep Power down start Deep Power down exit Next Cycle Parameter Description Min Max Units tZZWE ZZ low to Write Enable Low 0 1 us tR(Deep Power Down Mode only) Operation Recovery Time 150 - us tZZmin Low Power Mode Time 10 - us Write(DPD) down start down exit Partial Array Refresh Mode (A3=0, A4=1) 4. Address Information A2 A1,A0 Refresh Section Address Size Density 0 11 1/4 000000h-7FFFFh 512Kbx16 8Mb 0 10 1/2 000000h-FFFFFh 1Mbx16 16Mb X 00 Fl l 000000h 1FFFFFh 2Mb 16 32Mb Reduced Memory Size Mode (A3=1, A4=1) X 00 Full 000000h-1FFFFFh 2Mbx16 32Mb 1 11 1/4 180000h-1FFFFFh 512Kbx16 8Mb 1 10 1/2 100000h-1FFFFFh 1Mbx16 16Mb A2 A1,A0 Refresh Section Address Size Density 0 11 1/4 000000h-7FFFFh 512Kbx16 8Mb 0 10 1/2 000000h-FFFFFh 1Mbx16 16Mb 1 11 1/4 180000h-1FFFFFh 512Kbx16 8Mb 1 10 1/2 100000h-1FFFFFh 1Mbx16 16Mb Revision 0.1 Jul. 2010

48 BALL FINE PITCH BGA(0 75mm ball pitch)

Unit : millimeters 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View B Bottom View B B1 0.05 0.05 A1 INDEX MARK 6 5 4 3 2 1 A C #A1 C A B C D E F B/2 G H Side View Detail A D C E 0.30 Typ. 0.25/Typ. Y A -M i n T y p M a x A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 52 5 C 0.85/ NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical 5 Y is coplanarity : 0 08(Max)C1 - 5.25 - D 0.30 0.35 0.40 E - 1.10 1.20 E1 - 0.85 - E2 0.20 0.25 0.30 Y- - 0 . 0 8 5. Y is coplanarity : 0.08(Max) Revision 0.1 Jul. 2010