CMS6416LAF

CMS6416LAX-15EX FIDELIX | Alldatasheet

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Technical content

Rev1.3, Nov. 2005 CMS6416LAx-15Ex 64M(4Mx16) Low Power SDRAM Revision 1.3 November, 2005

Rev1.3, Nov. 2005 CMS6416LAx-15Ex Document Title 64M(4Mx16) Low Power SDRAM

Revision History

Feb, 2005Change IDD3p/Idd6 specification1.2 FinalNov. 1st, 2005Add H(Pb-Free & Halogen Free) descriptions1.3 Jan.10th, 2005Change Setup/Hold time1.1 PreliminaryDec.6th, 2004Change IDD specifications0.4 PreliminaryOct.20th, 2004Extend Vddmax limit for 2.5V product0.3 PreliminaryJan.5th, 2005 Add Pb & Halogen free package item Change from manual TCSR to auto TCSR Change IDD2N specifications 1.0 PreliminaryOct.6th, 2004Add commercial & extended temperature options Add package dimension0.2 PreliminaryAug.13th, 2004Correct typo. Add Write Burst Mode description0.1 PreliminaryJun.25th, 2004Initial Draft0.0 RemarkDraft dateHistoryRevision No.

Rev1.3, Nov. 2005 CMS6416LAx-15Ex

Features

• Functionality - Standard SDRAM Functionality - Programmable burst lengths : 1, 2, 4, 8, or full page - JEDEC Compatibility - Low Power Features - Low voltage power supply : 1.8V - Auto TCSR(Temperature Compensated Self Refresh) - Partial Array Self Refresh power-saving mode - Deep Power Down Mode - Driver Strength Control - Operating Temperature Ranges: - Special (-10℃ to +60℃) - Commercial (0℃ to +70℃) - Extended (-25℃ to +85℃) - Industrial (-40℃ to +85℃) - LVCMOS Compatible IO Interface - 54ball FBGA with 0.8mm ball pitch - CMS6416LAF : Normal - CMS6416LAG : Pb-Free - CMS6416LAH : Pb-Free & Halogen Free Functional Description The CMS6416LAx-xxxx family is high-performance CMOS Dynamic RAMs (DRAM) organized as 4M x 16. These devices feature advanced circuit design to provide ultra-low active current and extremely low standby current.This is ideal for providing More Battery Life in portable applications such as wireless handsets. The device is compatible with the JEDEC standard LP-SDRAM specifications. Selection Guide 20ns20ns8ns83MHz 20ns20ns7ns100MHz 1.65-VDD1.65-1.95VCMS6416LAx-15Ex tRCD CL=2 Access Time(tAC) CL=3VDDQVDD tRPFrequency Voltage Device Column Decoder Column Decoder Column Decoder Bank 0 Row Addr Latch/ Decoder Bank 3 Bank 2 Bank 1 Bank 0 Row Addr Latch/ Decoder Bank 0 Memory Array 4Kx4K Sense Amp Row Add Mux Write Drivers DQM Mask READ DATA LATCH Data Output Reg Column Address Latch Bank Control Logic Refresh Counter Addr Reg Data Output Reg LDQM - UDQM DQ0 - DQ15 Column Decoder Enhanced Mode Reg Mode Reg Control Logic CKE CLK /CS /WE /CAS /RAS A0-A11 BA0-BA1 Logic Block Diagram - CMS6432LBH : Pb-Free & Halogen Free

Rev1.3, Nov. 2005 CMS6416LAx-15Ex Pin Configuration for X16 VSS DQ15 V SSQ VDDQ DQ0 VDD DQ13 V DDQ VSSQ DQ2 DQ1DQ14 DQ11 V SSQ VDDQ DQ4 DQ3DQ12 DQ9 V DDQ VSSQ DQ6 DQ5DQ10 NC V SS VDD LDQM DQ7DQ8 CLK CKE /CAS /RAS /WEUDQM A11 A9 BA0 BA1 /CSNC A7 A6 A0 A1 A10A8 A5 A4 A3 A2 VDDVSS 54 ball FBGA(8mm x 8mm) 1 2 3 4 5 6 7 8 9 A B C D E F G H J

Rev1.3, Nov. 2005 CMS6416LAx-15Ex Pin Description Data Input/Output : Data busI/ODQ No Connect-NC DQ Power: Provide isolated power to DQs for improved noise immunity.SupplyVDDQ DQ Ground: Provide isolated ground to DQs for improved noise immunity.SupplyVSSQ Power Supply: Voltage dependent on option.SupplyVDD Ground.SupplyVSS Address Inputs: A0–A11 are sampled during the ACTIVE command (row-address A0–A11) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (A10 LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. InputA0-A11 Input/Output Mask: L(U)DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM corresponds to DQ0 – DQ7 and UDQM corresponds to DQ8–DQ15. InputLDQM, UDQM Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. InputBA0, BA1 Input Input Input Input Type /CAS, /RAS, /WE /CS CKE CLK Symbol Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. Command Inputs : /CAS, /RAS, and /WE (along with /CS) define the command being entered. Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle), ACTIVE POWER-DOWN(row active in any bank) or CLOCK SUSPEND operation(burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until af ter exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

Description

Rev1.3, Nov. 2005 CMS6416LAx-15Ex FUNCTIONAL DESCRIPTION The Fidelix 64Mb SDRAM is a quad-bank DRAM that operates at 1.8V and includes a synchronous inter- face (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a pro- grammed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE comm and. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0- A11 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.The SDRAM must be ini- tialized prior to normal operation. The following sections pro- vide detailed information regarding device initialization, register definition, command descriptions and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to V DD and V DDQ(simultaneously) and the clock is stable (meets the clock specifications in the AC characteristics), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. The COMMAND INHIBIT or NOP should be applied at least once during the 100µs delay. After the 100µs delay, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Refer to Figure 1.

Register and Extended Mode Register are discussed below. requirements will result in unspecified operation. that can be accessed for a given READ or WRITE command. Figure 1. Initialize and Load Mode Register

1. The two AUTO REFRESH commands at T4 and T9 may be applied before either LOAD MODE REGISTER (LMR) command.
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank
3. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order; However, all must occur prior to an Active command.

set to four; and by A3-A7 when the burst length is set to eight. bursts wrap within the page if the boundary is reached. Table 1. Mode Register Definition.

1. For full-page accesses: y = 256
2. For a burst length of two, A1-A7 select the block-of-two burst; A0 selects the starting column within the block.
3. For a burst length of four, A2-A7 select the block-of-four burst; A0-A1 select the starting column within the block.
4. For a burst length of eight, A3-A7 select the block-of-eight burst; A0-A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0-A7 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
7. For a burst length of one, A0-A7 select the unique column to be accessed,and mode register bit M3 is ignored.

Table 2. Burst Length Definition. will be valid by T2, as shown in Figure 2. incompatibility with future versions may result. single-location (non-burst) accesses.

Figure 2. CAS Latency

either of these requirements results in unspecified operation. refresh cycle automatically. will be lost when the two bank option with M7=0 is used. bank option with M7=0 is used down . Table 4. Extended Mode Register Definition

Table 5. Extended Mode Register Table[11.12.].

1. EM13 and EM12 (BA1 and BA0) must be “1, 0” to select the Extended Mode Register(vs. the base Mode Register).
2. RFU: Reserved for Future Use

1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A10 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the aut o precharge feature; BA0, BA1 determine which

bank is being read from or written to.

1. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
2. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
3. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
4. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). LDQM controls DQ0-7 and UDQM controls DQ8-15.

Table 6. provides a reference of all the commands available the SDRAM, regardless of whether the CLK signal is enabled. Operations already in progress are not affected. The mode register is loaded via inputs A0-A11, BA0, BA1. definition for the Mode Register and Extended Mode Register. or wait states. Operations already in progress are not affected. different row in the same bank. registered LOW, the DQs will provide valid data. be executed to that byte/column location. RP) after the PRECHARGE command is issued. any READ or WRITE commands being issued to that bank. performed upon completion of the READ or WRITE burst. AUTO PRECHARGE does not apply in the full page mode burst. disabled for each individual READ or WRITE command.

Rev1.3, Nov. 2005 CMS6416LAx-15Ex AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum t RP has been met after the PRECHARGE command. The addressing is generated by the internal refresh controller. The address bits thus are a “Don’t Care” during an AUTO REFRESH command. The Fidelix 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (t REF), regardless of width option. Providing a distributed AUTO REFRESH command every 15.625µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (t RFC), once every 64ms. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM(without external clocking), even if the rest of the system is powered down. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is reg- istered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to t RAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (meet the clock specifications in the AC characteristics) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for t XSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize he row refresh counter. DEEP POWER DOWN Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the device. Data will not be retained once the device enters DPD Mode. Full initialization is required when the device exits from DPD Mode. The DC value of DPD Mode can’t be zero due to transistor’s leakage current; a reverse PN diode leakage current which is called ‘Junction leakage current’ and a punch-through leakage current. [Figure29.30]

1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40°C = TA = +85°C for IT parts) is ensured.
2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operati on is ensured. (VDD and VDDQ must be
3. All states and sequences not shown are illegal or reserved.
4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
5. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.
6. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover point. If the input transition time is longer than tT (MAX), then the timing is referenced

at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.

1. IDD specifications are tested after the device is properly initialized.
2. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
3. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition.
4. Address transitions average one transition every two clocks.
5. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid V IH or VIL levels.
6. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD 6 limit is actually a nominal value and does not result in a fail value

Rev1.3, Nov. 2005 CMS6416LAx-15Ex AC Characteristics ns12tCLKS2 ns7tHZ(3)CL=3 ns8tHZ(2)CL=2 ns20tRRDActive Banka to Active Bankb Command ns20tRPPrecharge Command Period ns80tRFCAuto Refresh Period ms64tREFRefresh Period(4096 rows) ns20tRCDActive to Read/Write Delay ns80tRCActive to Active Command Period ns12000048tRASActive to Precharge Command ns-tHZ(1)CL=1 Data High Impedance Time[25.] ns1.0tCMH/CS, /RAS, /CAS, /WE, /DQM Hold Time to Clock ns2.0tCMS/CS, /RAS, /CAS, /WE, /DQM Setup Time to Clock ns1.0tCDHData In Hold Time to Clock ns2.0tCDSData In Setup Time to Clock ns2.5tOHOutput Hold Time from Clock ns-tAC(1)CL=1 ns8tAC(2)CL=2 ns7tAC(3)CL=3 Clock Access Time tCK1tBDLLast data-in to burst STOP command[38.] tCK2tDPLData-in to PRECHARGE command[41.] nstWR+tRPtDALData-in to ACTIVE command[40.] tCK0tDWDWRITE command to input data delay[38.] tCK2tDQZDQM to data high-impedance during READs[38.] tCK0tDQMDQM to data mask during WRITEs[38.] tCK0tDQDDQM to input data delay[38.] tCK1tPEDCKE to clock enable or power-down exit setup mode[39.] tCK1tCKEDCKE to clock disable or power-down entry mode[39.] tCK1tCCDREAD/WRITE command to READ/WRITE command[38.] ns80tXSRExit Self Refresh to Active Command[37.] ns20tWRWrite Recovery Time[36.] tCK2tWRWrite Recovery Time[35.] ns1.20.5tTTransition Time[34.] ns1.0tCKHCKE Hold Time to Clock ns2.0tCKSCKE Setup Time to Clock ns1.0tCAHAddress Hold Time to Clock ns2.0tCASAddress Setup Time to Clock ns3tCLClock Low Time ns3tCHClock High Time ns10tCLKS3 Clock Period[33.] MaxMinParameter Units -15 Symbol AC Characteristics

Rev1.3, Nov. 2005 CMS6416LAx-15Ex AC Characteristics tCK1tROH(1)CL=1 tCK2tROH(2)CL=2 tCK3tROH(3)CL=3 Data-out to high-impedance from PRECHARGE command[38.] tCK2tMRDLOAD MODE REGISTER command to ACTIVE or REFRESH command[42.] tCK2tRDLLast data-in to PRECHARGE command[41.] tCK1tCDLLast data-in to new READ/WRITE command[38.] MaxMinParameter Units -15 Symbol AC Characteristics Note : 33. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 34. AC characteristics assume tT = 1ns. 35. Auto precharge mode only. 36. Precharge mode only. 37. CLK must be toggled a minimum of two times during this period. 38. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 39. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 40. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 41. Timing actually specified by tWR. 42. JEDEC and PC100 specify three clocks.

Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3

Figure 5. Random Read Accesses for CAS Latency =1,2,3

Figure 6. Read to Write

element is valid, where x equals the CAS latency minus one. element n + 3 is the last desired data element of a longer burst. Figure 9. Read to Precharge

Figure 10. Terminating a Read Burst

Figure 11. Read & Write Cycle at Same Bank @Burst Length=4, tDPL =2CLK (100Mhz)

1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle.[CAS Latency -1] number of valid output data is available after Row precha rge. Last valid output will be Hi-Z(t SHZ) after
3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC
4. Out put will be Hi-Z after the end of burst. (1,2,3,8 & Full page bit burst)

Figure 12. Read & Write Cycle at Same Bank @Burst Length=4, tDPL=2CLK (133Mhz)

Figure 13. Page Read Cycle at Same Bank @ Burst Length=4

1. Row precharge will interrupt writing. Last data input, tDPL before Row precharge, will be written.

element will be registered coincident with the WRITE command. two or the last desired of a longer burst. performed to a different bank. Figure 14. Write Command

Rev1.3, Nov. 2005 CMS6416LAx-15Ex command. This is shown in Figure 20. , where data n is the last desired data element of a longer burst. PRECHARGE The PRECHARGE command (see Figure 21. ) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t RP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge(meeting t CKS). See Figure 22. .

Figure 21. Precharge Command

according to the programmed burst length and sequence. Figure 22. Power Down

Figure 23. Clock Suspend During Write Burst

Auto Precharge occurs are defined below. to bank m will interrupt a Read on bank n, CAS latency later.

1. Interrupted by a Write(with or without auto precharge): A

Write to bank m will interrupt a Read on bank n when registered.

1. Interrupted by a Read(with or without auto precharge): A
2. Interrupted by a Write ( with or without auto Precharge): A

Write to bank m will interrupt a Write on bank n when registered. Figure 24. Clock Suspend During Read Burst - Burst of 4 (CAS latency =2)

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current State is the state of the SDRAM immediatly prior to the clock edge n.
3. Commandn is the command registered at clock edge n , and Actionn is a result of Commandn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power down at clock edge n will put the device in all the banks idle state in time for clock edge n+1(provided the t
6. Exiting self refresh at clock edge n will put the device in all the banks idle state once tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges

occuring during the tXSR period. A minimum of two NOP commands must be provided during the tXSR period.

1. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1.
2. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 9. ) and after tXSR has been met (if the previous state was self refresh).
3. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that

state. Exceptions are covered in the notes below.

1. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data

bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

1. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank

Table 11. . Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating:

1. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these

state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state.

1. All states and sequences not shown are illegal or reserved.
2. Not bank-specific; requires that all banks are idle.
3. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
4. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
5. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs wi th auto precharge disabled.
6. Does not affect the state of the bank and acts as a NOP to that bank.

1. This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m

(assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.

1. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data

bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. bank will be in the idle state.

1. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
2. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
3. All states and sequences not shown are illegal or reserved.
4. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge d isabled.
5. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m’s burst.
6. Burst in bank n continues as initiated.
7. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later.
8. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered.

DQM should be used twwo clock prior to the WRITE command to prevent bus contention.

1. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered,

with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

1. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered.

The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

1. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later.

The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 25.) .

1. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be

used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 26. ).

1. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out

be data-in registered one clock prior to the READ to bank m(Figure 27. ).

1. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered.

clock prior to the WRITE to bank m (Figure 28. ).

Rev1.3, Nov. 2005 CMS6416LAx-15Ex PACKAGE DIMENSION 54 BALL FINE PITCH BGA (8 x 8 x 1.0 mm) Top View Bottom View Side View Unit : millimeters E D #A1 A1 INDEX MARK 9 8 7 6 5 4 3 2 1 E/2 D/2 e 0.400.350.30z 0.500.450.40b -0.80-e -6.40-D1 -8.00-D -6.40-E1 -8.00-E 1.20--A MaxTypMin- b E A z e A B C D E F G H J 1 2 3 4 5 6 7 8 9 A B C D E F G H J