FM93C56N

FM93CS56 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

I Wide VCC 2.7V - 5.5V I Programmable write protection I Sequential register read I Typical active current of 200µA 10µA standby current typical 1µA standby current typical (L) 0.1µA standby current typical (LZ) I No Erase instruction required before Write instruction I Self timed write cycle I Device status during programming cycles I 40 year data retention I Endurance: 1,000,000 data changes I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP INSTRUCTION DECODER CONTROL LOGIC AND CLOCK GENERATORS COMPARATOR AND WRITE ENABLE HIGH VOLTAGE GENERATOR AND PROGRAM TIMER INSTRUCTION REGISTER ADDRESS REGISTER PROTECT REGISTER EEPROM ARRAY READ/WRITE AMPS DATA IN/OUT REGISTER

16 BITS

2 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read Connection Diagram Dual-In-Line Package (N) 8–Pin SO (M8) and 8–Pin TSSOP (MT8) Top View Package Number N08E, M08A and MTC08 Pin Names CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground PE Program Enable PRE Protect Register Enable VCC Power Supply

Ordering Information

FM 93 CS XX LZ E XXX Letter Description Package N 8-pin DIP M8 8-pin SO MT8 8-pin TSSOP Temp. Range None 0 to 70 °C V -40 to +125 °C E -40 to +85 °C Voltage Operating Range Blank 4.5V to 5.5V L 2.7V to 5.5V LZ 2.7V to 5.5V and <1µA Standby Current Density 56 2048 bits C CMOS CS Data protect and sequential read Interface 93 MICROWIRE Fairchild Memory Prefix VCC PE GND CS SK DI DO PRE

3 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read Absolute Maximum Ratings (Note 1) Ambient Storage Temperature -65 °C to +150°C All Input or Output Voltages +6.5V to -0.3V with Respect to Ground Lead Temperature (Soldering, 10 sec.) +300 °C ESD rating 2000V Operating Conditions Ambient Operating Temperature FM93CS56 0 °C to +70°C FM93CS56E -40 °C to +85°C FM93CS56V -40 °C to +125°C Power Supply (VCC) 4.5V to 5.5V DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified Symbol Parameter Conditions Min Max Units ICCA Operating Current CS = V IH, SK=1.0 MHz 1 mA ICCS Standby Current CS = V IL 50 µA IIL Input Leakage V IN = 0V to VCC ±-1 µA IOL Output Leakage (Note 2) VIL Input Low Voltage -0.1 0.8 V VIH Input High Voltage 2 V CC +1 VOL1 Output Low Voltage I OL = 2.1 mA 0.4 V VOH1 Output High Voltage I OH = -400 µA 2.4 VOL2 Output Low Voltage I OL = 10 µA 0.2 V VOH2 Output High Voltage I OH = -10 µAV CC - 0.2 fSK SK Clock Frequency (Note 3) 1 MHz tSKH SK High Time 0 °C to +70°C 250 ns -40°C to +125°C 300 tSKL SK Low Time 250 ns tCS Minimum CS Low Time (Note 4) 250 ns tCSS CS Setup Time 50 ns tPRES PRE Setup Time 50 ns tDH DO Hold Time 70 ns tPES PE Setup Time 50 ns tDIS DI Setup Time 100 ns tCSH CS Hold Time 0 ns tPEH PE Hold Time 250 ns tPREH PRE Hold Time 50 ns tDIH DI Hold Time 20 ns tPD Output Delay 500 ns tSV CS to Status Valid 500 ns tDF CS to DO in Hi-Z CS = V IL 100 ns tWP Write Cycle Time 10 ms

4 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read Absolute Maximum Ratings (Note 1) Ambient Storage Temperature -65 °C to +150°C All Input or Output Voltages +6.5V to -0.3V with Respect to Ground Lead Temperature (Soldering, 10 sec.) +300 °C ESD rating 2000V Operating Conditions Ambient Operating Temperature FM93CS56L/LZ 0 °C to +70°C FM93CS56LE/LZE -40 °C to +85°C FM93CS56LV/LZV -40 °C to +125°C Power Supply (VCC) 2.7V to 5.5V DC and AC Electrical Characteristics VCC = 2.7V to 4.5V unless otherwise specified. Refer to page 3 for VCC = 4.5V to 5.5V. Symbol Parameter Conditions Min Max Units ICCA Operating Current CS = V IH, SK=256 KHz 1 mA ICCS Standby Current CS = V IL L 10 µA LZ (2.7V to 4.5V) 1 µA IIL Input Leakage V IN = 0V to VCC ±1 µA IOL Output Leakage (Note 2) VIL Input Low Voltage -0.1 0.15V CC V VIH Input High Voltage 0.8V CC VCC +1 VOL Output Low Voltage I OL = 10µA 0.1V CC V VOH Output High Voltage I OH = -10µA 0.9V CC fSK SK Clock Frequency (Note 3) 0 250 KHz tSKH SK High Time 1 µs tSKL SK Low Time 1 µs tCS Minimum CS Low Time (Note 4) 1 µs tCSS CS Setup Time 0.2 µs tPRES PRE Setup Time 50 ns tDH DO Hold Time 70 ns tPES PE Setup Time 50 ns tDIS DI Setup Time 0.4 µs tCSH CS Hold Time 0 ns tPEH PE Hold Time 250 ns tPREH PRE Hold Time 50 ns tDIH DI Hold Time 0.4 µs tPD Output Delay 2 µs tSV CS to Status Valid 1 µs tDF CS to DO in Hi-Z CS = V IL 0.4 µs tWP Write Cycle Time 15 ms Capacitance TA = 25°C, f = 1 MHz or 256 KHz (Note 5) Symbol Test Typ Max Units COUT Output Capacitance 5 pF CIN Input Capacitance 5 pF Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: Typical leakage values are in the 20nA range. Note 3: The shortest allowable SK clock period = 1/f SK (as shown under the fSK parameter). Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet. Within this SK period, both t SKH and tSKL limits must be observed. Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation. Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode diagram on the following page.) Note 5: This parameter is periodically sampled and not 100% tested. AC Test Conditions VCC Range V IL/VIH VIL/VIH VOL/VOH IOL/IOH Input Levels Timing Level Timing Level (Extended Voltage Levels) (TTL Levels) Output Load: 1 TTL Gate (CL = 100 pF)

SK, DI and DO pins are ignored while CS is held low. of this clock input. This pin is gated by CS signal. rising edge of the SCK. This pin is gated by CS signal. active only when the device is selected. device before clocking a “1”. This is a 2-bit field and should immediately follow the start bit. field) select a particular instruction to be executed. This is a 8-bit field and should immediately follow the Opcode bits. instruction (along with Opcode bits, PRE and PE signals). bits. Only the WRITE and WRALL instructions require this field. during writes as well as reads). TABLE 1. Instruction set

6 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read Functional Description A typical Microwire cycle starts by first selecting the device (bringing the CS signal high). Once the device is selected, a valid Start bit (“1”) should be issued to properly recognize the cycle. Following this, the 2-bit opcode of appropriate instruction should be issued. After the opcode bits, the 8-bit address information should be issued. For certain instructions, some (or all) of these 8 bits are don’t care values (can be “0” or “1”), but they should still be issued. Following the address information, depending on the instruction (WRITE and WRALL), 16-Bit data is issued. Other- wise, depending on the instruction (READ and PRREAD), the device starts to drive the output data on the DO line. Other instructions perform certain control functions and do not deal with data bits. The Microwire cycle ends when the CS signal is brought low. However during certain instructions, falling edge of the CS signal initiates an internal cycle (Programming), and the device remains busy till the completion of the internal cycle. Each of the 10 instructions is explained in detail in the following sections. Memory Instructions Following five instructions, READ, WEN, WRITE, WRALL and WDS are specific to operations intended for memory array. The PRE pin should be held low during these instructions. 1) Read and Sequential Read (READ) READ instruction allows data to be read from a selected location in the memory array. Input information (Start bit, Opcode and Address) for this instruction should be issued as listed under Table1. Upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer from the selected memory location into a 16-bit serial-out shift register. This 16-bit data is then shifted out on the DO pin. D15 bit (MSB) is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit (logical 0) precedes this 16-bit data output string. Output data changes are initiated on the rising edge of the SK clock. After reading the 16-bit data, the CS signal can be brought low to end the Read cycle. The PRE pin should be held low during this cycle. Refer Read cycle diagram. This device also offers “sequential memory read ” operation to allow reading of data from the additional memory locations instead of just one location. It is started in the same manner as normal read but the cycle is continued to read further data (instead of terminat- ing after reading the first 16-bit data). After providing 16-bit data, the device automatically increments the address pointer to the next location and continues to provide the data from that location. Any number of locations can be read out in this manner, however, after reading out from the last location, the address pointer points back to the first location. If the cycle is continued further, data will be read from this first location onward. In this mode of read, the dummy-bit is present only when the very first data is read (like normal read cycle) and is not present on subsequent data reads. The PRE pin should be held low during this cycle. Refer Sequen- tial Read cycle diagram. 2) Write Enable (WEN) When VCC is applied to the part, it “powers up” in the Write Disable (WDS) state. Therefore, all programming operations (for both memory array and Protect Register) must be preceded by a Write Enable (WEN) instruction. Once a Write Enable instruction is executed, programming remains enabled until a Write Disable (WDS) instruction is executed or V CC is completely removed from the part. Input information (Start bit, Opcode and Address) for this WEN instruction should be issued as listed under Table1. The device becomes write-enabled at the end of this cycle when the CS signal is brought low. The PRE pin should be held low during this cycle. Execution of a READ instruction is independent of WEN instruction. Refer Write Enable cycle diagram. 3) Write (WRITE) WRITE instruction allows write operation to a specified location in the memory with a specified data. This instruction is valid only when the following are true: I Device is write-enabled (Refer WEN instruction) I Address of the write location is not write-protected I PE pin is held high during this cycle I PRE pin should be held low during this cycle Input information (Start bit, Opcode, Address and Data) for this WRITE instruction should be issued as listed under Table1. After inputting the last bit of data (D0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes t WP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. The status of the internal programming cycle can be polled at any time by bringing the CS signal high again, after t CS interval. When CS signal is high, the DO pin indicates the READY/BUSY status of the chip. DO = logical 0 indicates that the programming is still in progress. DO = logical 1 indicates that the programming is finished and the device is ready for another instruction. It is not required to provide the SK clock during this status polling. While the device is busy, it is recommended that no new instruction be issued. Refer Write cycle diagram. It is also recommended to follow this instruction (after the device becomes READY) with a Write Disable (WDS) instruction to safeguard data against corruption due to spurious noise, inadvert- ent writes etc. 4) Write All (WRALL) Write all (WRALL) instruction is similar to the Write instruction except that WRALL instruction will simultaneously program all memory locations with the data pattern specified in the instruction. This instruction is valid only when the following are true: I Protect Register has been cleared (Refer PRCLEAR instruction) I Device is write-enabled (Refer WEN instruction) I PE pin is held high during this cycle I PRE pin should be held low during this cycle Input information (Start bit, Opcode, Address and Data) for this WRALL instruction should be issued as listed under Table1. After inputting the last bit of data (D0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes t WP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Write All cycle diagram.

7 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read 5) Write Disable (WDS) Write Disable (WDS) instruction disables all programming opera- tions and is recommended to follow all programming operations. Executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvertent writes etc. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table1. The device becomes write-disabled at the end of this cycle when the CS signal is brought low. Execution of a READ instruction is independent of WDS instruction. Refer Write Disable cycle diagram. Protect Register Instructions Following five instructions, PRREAD, PREN, PRCLEAR, PRWRITE and PRDS are specific to operations intended for Protect Register. The PRE pin should be held high during these instructions. 1) Protect Register Read (PRREAD) This instruction reads the content of the internal Protect Register. Content of this register is 8-bit wide and is the starting address of the “write-protected” section of the memory array. All memory locations greater than or equal to this address are write-protected. Input information (Start bit, Opcode and Address) for this PRREAD instruction should be issued as listed under Table 1. Upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer (address information) from the Protect Register. This 8-bit data is then shifted out on the DO pin with the MSB first and the LSB last. Like the READ instruction a dummy-bit (logical 0) precedes this 8-bit data output string. Output data changes are initiated on the rising edge of the SK clock. After reading the 8-bit data, the CS signal can be brought low to end the PRREAD cycle. The PRE pin should be held high during this cycle. Refer Protect Register Read cycle diagram. Though the content of this register is 8-bit wide, only the last 7 bits (LSB) are valid for FM93CS56 device. 2) Protect Register Enable (PREN) This instruction is required to enable PRCLEAR, PRWRITE and PRDS instructions and should be executed prior to executing PRCLEAR, PRWRITE and PRDS instructions. However, this PREN instruction is enabled (valid) only the following are true I Device is write-enabled (Refer WEN instruction) I PE pin is held high during this cycle I PRE pin is held high during this cycle Input information (Start bit, Opcode and Address) for this PREN instruction should be issued as listed under Table1. The Protect Register becomes enabled for PRCLEAR, PRWRITE and PRDS instructions at the end of this cycle when the CS signal is brought low. Note that this PREN instruction must immediately precede a PRCLEAR, PRWRITE or PRDS instruction. In other words, no other instruction should be executed between a PREN instruction and a PRCLEAR, PRWRITE or PRDS instruction. Refer Protect Register Enable cycle diagram. 3) Protect Register Clear (PRCLEAR) This instruction clears the content of the Protect register and therefore enables write operations (WRITE or WRALL) to all memory locations. Executing this instruction will program the content of the Protect Register with a pattern of all 1s. However, in this case, WRITE operation to the last memory address (0x01111111) is still enabled. PRCLEAR instruction is enabled (valid) only when the following are true: I PREN instruction was executed immediately prior to PRCLEAR instruction I PE pin is held high during this cycle I PRE pin is held high during this cycle Input information (Start bit, Opcode and Address) for this PRCLEAR instruction should be issued as listed under Table1. After inputting the last bit of address (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed clear cycle. It takes t WP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal clear cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Protect Register Clear cycle diagram. 4) Protect Register Write (PRWRITE) This instruction is used to write the starting address of the memory section to be write-protected into the Protect register. After the execution of PRWRITE instruction, all memory locations greater than or equal to this address are write-protected. PRWRITE instruction is enabled (valid) only the following are true: I PRCLEAR instruction was executed first (to clear the Protect Register) I PREN instruction was executed immediately prior to PRWRITE instruction I PE pin is held high during this cycle I PRE pin is held high during this cycle Input information (Start bit, Opcode and Address) for this PRWRITE instruction should be issued as listed under Table1. After inputting the last bit of address (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes t WP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Protect Register Write cycle diagram. 5) Protect Register Disable (PRDS) Unlike all other instructions, this instruction is a one-time-only instruction which when executed permanently write-protects the Protect Register and renders it unalterable in the future. This instruction is useful to safeguard vital data (typically read only data) in the memory against any possible corruption. PRDS instruction is enabled (valid) only the following are true: I PREN instruction was executed immediately prior to PRDS instruction I PE pin is held high during this cycle I PRE pin is held high during this cycle Input information (Start bit, Opcode and Address) for this PRDS

8 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read instruction should be issued as listed under Table1. After inputting the last bit of address (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes t WP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. The Protect Register is permanently write-protected at the end of this cycle. Refer Protect Register Disable cycle diagram. Clearing of Ready/Busy status When programming is in progress, the Data-Out pin will display the programming status as either BUSY (low) or READY (high) when CS is brought high (DO output will be tri-stated when CS is low). To restate, during programming, the CS pin may be brought high and low any number of times to view the programming status without affecting the programming operation. Once programming is completed (Output in READY state), the output is ‘cleared’ (returned to normal tri-state condition) by clocking in a Start Bit. After the Start Bit is clocked in, the output will return to a tri-stated condition. When clocked in, this Start Bit can be the first bit in a command string, or CS can be brought low again to reset all internal circuits. Refer Clearing Ready Status diagram. Related Document PROM.

9 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read tCSS SYNCHRONOUS DATA TIMING CS SK PRE PE DI DO (Data Read) DO (Status Read) Valid Status tPRES tPES tDIS tDIH tPD tDH tSV tSKH tSKL tCSH tPREH tPEH tDF tDF tPD Valid Input Valid Input Valid Output Valid Output CS SK DI DO High - Z Dummy Bit 1 1 0 A7 A6 A1 A0 PRE

0 D15 D1 D0

/;/;/;/; /;/;/;/; tCS /;/;/; /;/;/; NORMAL READ CYCLE (READ) Address Bits(8) Start Bit Opcode Bits(2) 93CS56: Address bits pattern -> x-A6-A5-A4-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); ( A6-A0 -> User defined ) PE Timing Diagrams CS SK DI DO High - Z Dummy Bit Data(n) 1 1 0 A7 A0 PRE

0 D15 D0

/;/;/;/; /;/;/;/; tCS /;/;/; /;/;/; SEQUENTIAL READ CYCLE (PRE = 0; PE = X) Data(n+1) Data(n+2) Address Bits(8) Start Bit Opcode Bits(2) 93CS56: Address bits pattern ->x-A6-A5-A4-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); ( A6-A0 -> User defined )

10 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read Timing Diagrams (Continued) Address Bits(8) CS PE SK DI DO High - Z WRITE DISABLE CYCLE (WDS) Start Bit 93CS56: Address bits pattern -> 0-0-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1) Opcode Bits(2) 1 0 0 A7 A6 A1 A0 PRE tCS Address Bits(8) Data Bits(16) CS PE SK DI DO High - Z tCS WRITE CYCLE (WRITE) Start Bit 93CS56: Address bits pattern -> x-A6-A5-A4-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); ( A6-A0 -> User defined ) Data bits pattern -> User defined Opcode Bits(2) 1 0 1 A7 A6 A1 A0 D15 D14 D1 D0 PRE Busy Ready tWP Address Bits(8) CS PE SK DI DO High - Z WRITE ENABLE CYCLE (WEN) Start Bit 93CS56: Address bits pattern -> 1-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1) Opcode Bits(2) 1 0 0 A7 A6 A1 A0 PRE tCS

11 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read Timing Diagrams (Continued) CS SK DI DO High - Z Dummy Bit 1 1 0 A7 A6 A1 A0 PRE PE

0 D7 D1 D0

/;/;/;/; /;/;/;/; tCS /;/;/; /;/;/; PROTECT REGISTER READ CYCLE (PRREAD) Address Bits(8) Start Bit Opcode Bits(2) 93CS56: Address bits pattern -> x-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1) Address Bits(8) CS PE SK DI DO High - Z PROTECT REGISTER ENABLE CYCLE (PREN) Start Bit 93CS56: Address bits pattern -> 1-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1) Opcode Bits(2) 1 0 0 A7 A6 A1 A0 PRE tCS /;/;/;/;/;/;/;/;/; /;/;/;/;/;/;/;/;/; Address Bits(8) Data Bits(16) CS PE SK DI DO High - Z tCS WRITE ALL CYCLE (WRALL) Start Bit 93CS56: Address bits pattern -> 0-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1) Data bits pattern -> User defined Opcode Bits(2) 1 0 0 A7 A6 A1 A0 D15 D14 D1 D0 PRE Busy Ready tWP

12 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read Timing Diagrams (Continued) Address Bits(8) CS PE SK DI DO High - Z tCS PROTECT REGISTER WRITE CYCLE (PRWRITE) Start Bit 93CS56: Address bits pattern -> x-A6-A5-A4-A3-A2-A1-A0; (x -> Don't Care, can be 0 or 1); ( A6-A0 -> User defined ) Opcode Bits(2) 1 0 1 A7 A6 A1 A0 PRE Busy Ready tWP /;/;/;/;/;/;/;/;/; /;/;/;/;/;/;/;/;/; Address Bits(8) CS PE SK DI DO High - Z tCS PROTECT REGISTER DISABLE CYCLE (PRDS) Start Bit 93CS56: Address bits pattern -> 0-0-0-0-0-0-0-0 Opcode Bits(2) 1 0 0 A7 A6 A1 A0 PRE Busy Ready tWP /;/;/;/;/;/;/;/;/; /;/;/;/;/;/;/;/;/; Address Bits(8) CS PE SK DI DO High - Z tCS PROTECT REGISTER CLEAR CYCLE (PRCLEAR) Start Bit 93CS56: Address bits pattern -> 1-1-1-1-1-1-1-1 Opcode Bits(2) 1 1 1 A7 A6 A1 A0 PRE Busy Ready tWP /;/;/;/;/;/;/;/;/; /;/;/;/;/;/;/;/;/;

13 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read Timing Diagrams (Continued) CS PE SK DI DO High - Z High - Z CLEARING READY STATUS Start Bit Note: This Start bit can also be part of a next instruction. Hence the cycle can be continued(instead of getting terminated, as shown) as if a new instruction is being issued. PRE Busy Ready

14 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8) Package Number M08A Physical Dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) Lead #1 IDENT Seating Plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) Typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) Typ 0.016 - 0.050 (0.406 - 1.270) Typ. All Leads 8¡ Max, Typ. All leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads 0.004 (0.102) All lead tips 0.010 - 0.020

15 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read 8-Pin Molded TSSOP, JEDEC (MT8) Physical Dimensions inches (millimeters) unless otherwise noted 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 0.169 - 0.177 (4.30 - 4.50) (7.72) Typ(4.16) Typ (1.78) Typ (0.42) Typ (0.65) Typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) Typ. 0.0433 (1.1) Max 0.0075 - 0.0118 (0.19 - 0.30) Pin #1 IDENT 0.0035 - 0.0079 0¡-8¡ 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25)Seating plane Gage plane See detail A Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 Land pattern recommendation DETAIL A Typ. Scale: 40X

16 www.fairchildsemi.com FM93CS56 Rev. C.1 FM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROMwith Data Protect and Sequential Read Physical Dimensions inches (millimeters) unless otherwise noted Molded Dual-In-Line Package (N) Package Number N08E 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337)DIA 1234 8765 0.250 - 0.005 (6.35 ± 0.127) 870.032 ± 0.005 (0.813 ± 0.127) Pin #1 Option 2 RAD 0.145 - 0.200 (3.683 - 5.080) 0.130 ± 0.005 (3.302 ± 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) Min0.018 ± 0.003 (0.457 ± 0.076) 90° ± 4° Typ 0.100 ± 0.010 (2.540 ± 0.254) 0.040 (1.016) 0.039 (0.991) Typ. 20° ± 1° 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) Pin #1 IDENT Option 1

0.280 MIN

0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762)MAX 0.125 (3.175) DIA NOM 0.009 - 0.015 (0.229 - 0.381) 0.045 ± 0.015 (1.143 ± 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95° ± 5° 0.090 (2.286) (7.112) IDENT Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Americas Europe Hong Kong Japan Ltd. Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg. Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan Franç ais Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840 Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841