FM25H20-G

FM25H20 RAMTRON | Alldatasheet

Document overview

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• PDF pages: 15

Technical content

Features

2M bit Ferroelectric Nonvolatile RAM

• Organized as 256K x 8 bits
• High Endurance 100 Trillion (1014) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI
• Up to 40 MHz Frequency
• Direct Hardware Replacement for Serial Flash
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Write Protection Scheme
• Hardware Protection
• Software Protection Low Power Consumption
• Low Voltage Operation 2.7V – 3.6V
• Sleep Mode Current 3 µA (typ.) Industry Standard Configurations
• Industrial Temperature -40°C to +85°C
• 8-pin “Green”/RoHS TDFN Package
• 8- pin “Green”/RoHS EIAJ SOIC Package

Description

The FM25H20 is a 2-megabit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories. Unlike Serial Flash, the FM25H20 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after it has been transferred to the device. The next bus cycle may commence without the need for data polling. The product offers virtually unlimited write endurance, orders of magnitude more endurance than Serial Flash. Also, F-RAM exhibits lower power consumption than Serial Flash. These capabilities make the FM25H20 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of Serial Flash can cause data loss. The FM25H20 provides substantial benefits to users of Serial Flash as a hardware drop-in replacement. The FM25H20 uses the high-speed SPI bus, which enhances the high-speed write capability of F-RAM technology. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration S Q W VSS VDD HOLD C D Pinout is equivalent to other SPI F-RAM devices. Pin Name Function /S Chip Select /W Write Protect /HOLD Hold C Serial Clock D Serial Data Input Q Serial Data Output VDD Supply Voltage (2.7 to 3.6V) VSS Ground

Ordering Information

FM25H20-DG 8-pin “Green”/RoHS TDFN FM25H20-DGTR 8-pin “Green”/RoHS TDFN, Tape & Reel FM25H20-G 8-pin “Green”/RoHS EIAJ SOIC FM25H20-GTR 8-pin “Green”/RoHS EIAJ SOIC, Tape & Reel Q VSS VDD /HOLD C D Top View

Figure 1. Block Diagram ignores any transition on C or /S. All transitions on /HOLD must occur while C is low. Register. A complete explanation of write protection is provided on pages 6 and 7. logic level to meet IDD specifications.

• D may be connected to Q for a single pin data interface.

the falling edge of the serial clock.

• Q may be connected to D for a single pin data interface.

Rev. 2.2 Sept. 2010 Page 3 of 15 Overview The FM25H20 is a serial F-RAM memory. The memory array is logically organized as 262,144 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the F-RAM is similar to Serial Flash. The major differences between the FM25H20 and a Serial Flash with the same pinout are the F-RAM’s superior write performance, very high endurance, and lower power consumption. Memory Architecture When accessing the FM25H20, the user addresses 256K locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a three- byte address. The complete address of 18-bits specifies each byte address uniquely. Most functions of the FM25H20 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike Serial Flash, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25H20 due to its fast write cycle and high endurance as compared to Serial Flash. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than Serial Flash since it is completed quickly. By contrast, Serial Flash requiring milliseconds to write is vulnerable to noise during much of the cycle. Serial Peripheral Interface – SPI Bus The FM25H20 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 40MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25H20 operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25H20 devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25H20 device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the Hold pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25H20 will begin monitoring the clock and data lines. The relationship between the falling edge of /S, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25H20 supports only modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25H20 on the rising edge of C and data is expected on the first rising edge after /S goes active. If the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /S is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Certain op-codes are commands with no subsequent data transfer. The /S must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.

WREN and WRDI commands, respectively. BP1 and BP0 are memory block write protection bits. protected as shown in the following table. Table 3. Block Memory Write Protection protect inadvertent changes to the block protect bits. protected only when WPEN=1 and the /W pin is low. Table 4. Write Protection

0 X X Protected Protected Protected

of sequential writes may be performed. op-code. The next op-code is the WRITE instruction. bits in the most significant address byte are ignored. write operation is shown in Figure 9. address of the first data byte of the read operation.

operates with a read and restore mechanism. endurance is very high even at 40MHz clock rate. Table 5. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop

14 Cycles

Rev. 2.2 Sept. 2010 Page 10 of 15 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +4.5V VIN Voltage on any pin with respect to V SS -1.0V to +4.5V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 260° C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. D) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 2kV 1kV 200V Package Moisture Sensitivity Level MSL-1 (TDFN) MSL-1 (EIAJ) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40°C to + 85°C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 2.7 3.3 3.6 V IDD Power Supply Current @ C = 1 MHz @ C = 40 MHz 1.0 10.0 mA mA ISB Standby Current @ TA = 25°C @ TA = 85°C 150 270 µA µA IZZ Sleep Mode Current @ TA = 25°C @ TA = 85°C µA µA ILI Input Leakage Current - ±1 µA 4 ILO Output Leakage Current - ±1 µA 4 VIL Input Low Voltage -0.4 0.3 V DD V VIH Input High Voltage 0.7 V DD V DD + 0.5 V VOL Output Low Voltage @ IOL = 1.6 mA 0.4 V VOH Output High Voltage @ IOH = -100 µA VDD – 0.2 V Notes 1. C toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V. 2. /S=VDD. All inputs VSS or VDD. 3. In Sleep mode and /S=VDD. All inputs VSS or VDD. 4. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD.

Rev. 2.2 Sept. 2010 Page 11 of 15 AC Parameters (TA = -40°C to + 85°C, VDD = 2.7V to 3.6V, CL = 30pF) Symbol Parameter Min Max Units Notes fCK C Clock Frequency 0 40 MHz tCH Clock High Time 11 ns 1 tCL Clock Low Time 11 ns 1 tSU Chip Select Setup 10 ns tSH Chip Select Hold 10 ns tOD Output Disable Time 12 ns 2 tODV Output Data Valid Time 9 tOH Output Hold Time 0 ns tD Deselect Time 40 ns tR Data In Rise Time 50 ns 2,3 tF Data In Fall Time 50 ns 2,3 tSU Data Setup Time 5 ns tH Data Hold Time 5 ns tHS /HOLD Setup Time 10 ns tHH /HOLD Hold Time 10 ns tHZ /HOLD Low to Hi-Z 20 ns 2 tLZ /HOLD High to Data Active 20 ns 2 Notes 1. tCH + tCL = 1/fCK. 2. This parameter is characterized but not 100% tested. 3. Rise and fall times measured between 10% and 90% of waveform. AC Test Conditions Input Pulse Levels 10% and 90% of V DD Input rise and fall times 3 ns Input and output timing levels 0.5 V DD Output Load Capacitance 30 pF Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CO Output Capacitance (Q) - 8 pF 1 CI Input Capacitance - 6 pF 1 Notes 1. This parameter is characterized and not 100% tested. Data Retention (TA = -40°C to +85°C) Symbol Parameter Min Units Notes TDR Data Retention 10 Years

Rev. 2.2 Sept. 2010 Page 12 of 15 Serial Data Bus Timing /HOLD Timing S C Q HOLD tHS tHH tHZ tLZ tHS tHH Power Cycle Timing Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V) Symbol Parameter Min Max Units Notes tPU Power Up (V DD min) to First Access (/S low) 1 - ms tPD Last Access (/S high) to Power Down (V DD min) 0 - µs tREC Recovery Time from Sleep Mode - 450 µs tVR V DD Rise Time 50 - µs/V 1,2 tVF V DD Fall Time 100 - µs/V 1,2 Notes 1. This parameter is characterized and not 100% tested. 2. Slope measured at any point on VDD waveform.

Rev. 2.2 Sept. 2010 Page 13 of 15 Mechanical Drawing 8-pin TDFN (5.0 mm x 6.0 mm body, 1.27 mm pad pitch) Note: All dimensions in millimeters . This package is footprint compatible with the 8-pin SOIC. The exposed pad should be left floating. Legend: R=Ramtron, G=”green” TDFN package XXXX=base part number LLLL= lot code YY=year, WW=work week Example: “Green” TDFN package, FM25H20, Lot 0012, Year 2010, Work Week 10 RG5H20 0012 1010 RGXXXX LLLL YYWW

Rev. 2.2 Sept. 2010 Page 14 of 15 8-pin EIAJ SOIC Pin 1 5.23 ±0.10 0.05 0.25 1.78 2.00 0.36 0.50 1.27 0.10 mm 0.51 0.76 0.19 0.25 0°- 8° Recommended PCB Footprint 9.30 0.651.27 2.15 5.00 All dimensions in millimeters. Legend: XXXXXX= part number LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week FM25H20, “Green” EIAJ SOIC package, Year 2009, Work Week 40 FM25H20-G B90003G1 RIC 0940 XXXXXXX-G LLLLLLL RIC YYWW

Rev. 2.2 Sept. 2010 Page 15 of 15

Revision History

1.0 8/22/2007 Initial release. 1.1 3/18/2008 Changed endurance limit. Changed I DD, ISB, and I ZZ limits. Changed t REC sleep mode exit timing spec. Added package MSL rating and placeholder for ESD ratings. Changed V OH/VOL specs. 1.2 8/11/2008 Removed Q pin’s ability to drive high/low during wakeup from Sleep mode (pg. 8). The user must wait tREC for the device to be ready for normal operation. 1.3 1/28/2009 Added Tape & Reel ordering information. Modified mechanical drawing and added pcb footprint. 2.0 2/25/2009 Changed status to Pre-Production. Modified mechanical drawing and added pcb footprint. 2.1 9/15/2009 Added EIAJ SOIC package. Added ESD ratings. Changed recommended DFN pcb footprint. Updated lead temperature rating in Abs Max table. 2.2 9/14/2010 Modified DFN mechanical drawing and recommended pcb footprint. Date code of new package starts at 1010.