FM25C160B-G

FM25C160B RAMTRON | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

16K bit Ferroelectric Nonvolatile RAM

• Organized as 2,048 x 8 bits
• High Endurance 1 Trillion (1012) Read/Writes
• 38 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz maximum Bus Frequency
• Direct hardware replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Sophisticated Write Protection Scheme
• Hardware Protection
• Software Protection Low Power Consumption
• 250 µA Active Current (1 MHz)
• 4 µA (typ.) Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin “Green”/RoHS SOIC (-G)

Description

The FM25C160B is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM25C160B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM25C160B is capable of supporting up to 10 12 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM25C160B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25C160B provides substantial benefits to users of serial EEPROM, in a hardware drop-in replacement. The FM25C160B uses the high-speed SPI bus, which enhances the high-speed write capability of F-RAM technology. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration Pin Name Function /CS Chip Select /WP Write Protect /HOLD Hold SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD 5V VSS Ground

Ordering Information

FM25C160B-G “Green” 8-pin SOIC FM25C160B-GTR “Green” 8-pin SOIC, Tape & Reel CS SO WP VSS VDD HOLD SCK SI

Figure 1. Block Diagram the function of /WP is different from the FM25160. level to meet IDD specifications.

• SI may be connected to SO for a single pin data interface.

the falling edge of the serial clock.

• SO may be connected to SI for a single pin data interface.

FM25C160B - 16Kb 5V SPI F-RAM Rev. 1.2 Mar. 2011 Page 3 of 13 Overview The FM25C160B is a serial F-RAM memory. The memory array is logically organized as 2,048 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the F-RAM is similar to serial EEPROMs. The major difference between the FM25C160B and a serial EEPROM with the same pin-out relates to its superior write performance. This makes the FM25C160B a drop-in replacement for most 16Kb SPI EEPROMs that support modes 0 & 3. Memory Architecture When accessing the FM25C160B, the user addresses 2,048 locations each with 8 data bits. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code and a two-byte address. The upper 5 bits of the address range are ‘don’t care’ values. The complete address of 11-bits specifies each byte address uniquely. Most functions of the FM25C160B either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation essentially is zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM25C160B due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note: The FM25C160B contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within data sheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active. Serial Peripheral Interface – SPI Bus The FM25C160B employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 20 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25C160B operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25C160B devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25C160B device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (high) the Hold pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data lines. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25C160B will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25C160B supports modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25C160B on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the part. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS pin must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.

protect inadvertent changes to the block protect bits. register is write protected if WPEN=1 and /WP=0. Table 4. Write Protection

0 X X Protected Protected Protected

any number of sequential writes may be performed. op-code. The next op-code is the WRITE instruction. value. The upper 5-bits of the address are don’t care. code and address are complete, the SI line is ignored. edge of /CS terminates a READ op-code operation. but the SCK pin can toggle during a hold state.

FM25C160B - 16Kb 5V SPI F-RAM Rev. 1.2 Mar. 2011 Page 9 of 13 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +7.0V VIN Voltage on any pin with respect to V SS -1.0V to +7.0V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 260° C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 4kV 1.25kV 300V Package Moisture Sensitivity Level MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 4.5 5.0 5.5 V IDD VDD Supply Current @ SCK = 1.0 MHz @ SCK = 20.0 MHz 0.25 4.0 mA mA ISB Standby Current 4 10 µA 2 ILI Input Leakage Current ±1 µA 3 ILO Output Leakage Current ±1 µA 3 VIL Input Low Voltage -0.3 0.3 V DD V VIH Input High Voltage 0.7 V DD V DD + 0.3 V VOL Output Low Voltage @ IOL = 2 mA 0.4 V VOH Output High Voltage @ IOH = -2 mA VDD – 0.8 V VHYS Input Hysteresis 0.05 V DD V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VIN or VOUT = VSS to VDD. 4. This parameter is characterized but not 100% tested.

FM25C160B - 16Kb 5V SPI F-RAM Rev. 1.2 Mar. 2011 Page 10 of 13 AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes fCK SCK Clock Frequency 0 20 MHz tCH Clock High Time 22 ns 1 tCL Clock Low Time 22 ns 1 tCSU Chip Select Setup 10 ns tCSH Chip Select Hold 10 ns tOD Output Disable 20 ns 2 tODV Output Data Valid 20 ns tOH Output Hold 0 ns tD Deselect Time 60 ns tR Data In Rise Time 50 ns 1,3 tF Data In Fall Time 50 ns 1,3 tSU Data Setup Time 5 ns tH Data Hold Time 5 ns tHS /Hold Setup Time 10 ns tHH /Hold Hold Time 10 ns tHZ /Hold Low to Hi-Z 20 ns 2 tLZ /Hold High to Data Active 20 ns 2 Notes 1. tCH + tCL = 1/fCK. 2. Rise and fall times measured between 10% and 90% of waveform. 3. This parameter is characterized and not 100% tested. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CO Output Capacitance (SO) 8 pF 1 CI Input Capacitance 6 pF 1 Notes 1. This parameter is characterized and not 100% tested. AC Test Conditions Input Pulse Levels 10% and 90% of V DD Input rise and fall times 5 ns Input and output timing levels 0.5 V DD Output Load Capacitance 30 pF Data Retention Symbol Parameter Min Max Units Notes TDR @ +85ºC 10 - Years @ +80ºC 19 - Years @ +75ºC 38 - Years

FM25C160B - 16Kb 5V SPI F-RAM Rev. 1.2 Mar. 2011 Page 11 of 13 Serial Data Bus Timing CS SCK SI SO 1/tCK tCL tCH tCSH tODV tOH tOD tCSU tSU tH tD tRtF /Hold Timing CS SCK SO HOLD tHS tHH tHZ tLZ tHS tHH Power Cycle Timing Power Cycle Timing (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes tPU V DD(min) to First Access Start 10 - ms tPD Last Access Complete to V DD(min) 0 - µs tVR V DD Rise Time 30 - µs/V 1 tVF V DD Fall Time 100 - µs/V 1 Notes 1. Slope measured at any point on VDD waveform.

FM25C160B - 16Kb 5V SPI F-RAM Rev. 1.2 Mar. 2011 Page 12 of 13 Mechanical Drawing (8-pin SOIC – JEDEC MS-012, Variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45° 0.40 1.27 0.19 0.25 0°- 8° Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXXXXX= part number, P= package type (G=SOIC) R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25C160B, “Green” SOIC package, Year 2010, Work Week 51 FM25C160BG A00002G1 RIC1051 XXXXXXXP RLLLLLLL RICYYWW

FM25C160B - 16Kb 5V SPI F-RAM Rev. 1.2 Mar. 2011 Page 13 of 13

Revision History

1.0 11/10/2010 Initial Release 1.1 2/15/2011 Changed t PU and tVF spec limits. 1.2 3/30/2011 Added ESD ratings.