FM25640

FM25640 RAMTRON | Alldatasheet

Document overview

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• PDF pages: 14

Technical content

Features

64K bit Ferroelectric Nonvolatile RAM

• Organized as 8,192 x 8 bits
• High Endurance 1 Trillion (1012) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced high-reliability ferroelectric process Very Fast Serial Peripheral Interface - SPI
• Up to 5 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Sophisticated Write Protection Scheme
• Hardware Protection
• Software Protection Low Power Consumption
• 10 µA Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC

Description

The FM25640 is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM25640 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array mere hundreds of nanoseconds after it has been successfully transferred to the device. The next bus cycle may commence immediately. In addition, the product offers substantial write endurance compared with other nonvolatile memories. The FM25640 is capable of supporting up to 10 12-read/write cycles -- far more than most systems will require from a serial memory. These capabilities make the FM25640 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25640 provides substantial benefits to users of serial EEPROM, in a hardware drop-in replacement. The FM25640 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration Pin Names Function /CS Chip Select /HOLD Hold /WP Write Protect SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD 5V VSS Ground

Ordering Information

Figure 1. Block Diagram frequency may be any value between 0 and 5 MHz and may be interrupted at any time. for another task. Taking the /HOLD signal to a low state pauses the current operation. /WP is different from the FM25040 where it prevents all writes to the part. level to meet IDD specifications.

• SI may be connected to SO for a single pin data interface.

the falling edge of the serial clock.

Rev. 2.1 Aug 2003 3 of 14 Overview The FM25640 is a serial FRAM memory. The memory array is logically organized as 8,192 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25640 and a serial EEPROM with the same pin-out relates to its superior write performance. Memory Architecture When accessing the FM25640, the user addresses 8,192 locations each with 8 data bits. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code and a two-byte address. The upper 3 bits of the address range are ‘don’t care’ values. The complete address of 13-bits specifies each byte address uniquely. Most functions of the FM25640 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation essentially is zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM25640 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25640 contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within data sheet tolerances to prevent incorrect operation. Serial Peripheral Interface – SPI Bus The FM25640 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 5 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25640 operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. It is possible to connect the two data lines together. Figure 2 illustrates a typical system configuration using the FM25640 with a microcontroller that offers an SPI port. Figure 3 shows a similar configuration for a microcontroller that has no hardware support for the SPI bus. Protocol Overview The SPI interface is a synchronous serial interface using clock and data lines. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25640 will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25640 supports modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25640 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the part. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Certain op-codes are commands with no subsequent data transfer. The /CS must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.

protect inadvertent changes to the block protect bits. register is write protected if WPEN=1 and /WP=0. write protection conditions. Table 4. Write Protection

0 X X Protected Protected Protected

any number of sequential writes may be performed. op-code. The next op-code is the WRITE instruction. value. The upper 3-bits of the address are don’t care. code and address are complete, the SI line is ignored. edge of /CS terminates a READ op-code operation. but the SCK pin can toggle during a hold state.

Rev. 2.1 Aug 2003 9 of 14

Applications

The versatility of FRAM technology fits into many diverse applications. Clearly the strength of higher write endurance and faster writes make FRAM superior to EEPROM in all but one-time programmable applications. The advantage is most obvious in data collection environments where writes are frequent and data must be nonvolatile. The attributes of fast writes and high write endurance combine in many innovative ways. A short list of ideas is provided here. 1. Data collection . In applications where data is collected and saved, FRAM provides a superior alternative to other solutions. It is more cost effective than battery backup for SRAM and provides better write attributes than EEPROM. 2. Configuration . Any nonvolatile memory can retain a configuration. However, if the configuration changes and power failure is a possibility, the higher write endurance of FRAM allows changes to be recorded without restriction. Any time the system- state is altered, the change can be written. This avoids writing to memory on power-down when the available time is short and power scarce. 3. High noise environments . Writing to EEPROM in a noisy environment can be challenging. When severe noise or power fluctuations are present, the long write time of EEPROM creates a window of vulnerability during which the write can be corrupted. The fast write of FRAM is complete within a microsecond. This time is typically too short for noise or power fluctuations to disturb it. 4. Time to market . In a complex system, multiple software routines may need to access the nonvolatile memory. In this environment the time delay associated with programming EEPROM adds undue complexity to the software development. Each software routine must wait for complete programming before allowing access to the next routine. When time to market is critical, FRAM can eliminate this simple obstacle. As soon as a write is issued to the FM25640, it is effectively done -- no waiting. 5. RF/ID . In the area of contactless memory, FRAM provides an ideal solution. Since RF/ID memory is powered by an RF field, the long programming time and high current consumption needed to write EEPROM is unattractive. FRAM provides a superior solution. The FM25640 is suitable for multi-chip RF/ID products. 6. Maintenance tracking . In sophisticated systems, the operating history and system-state during a failure is important knowledge. Maintenance can be expedited when this information has been recorded. Due to the high write endurance, FRAM makes an ideal system log. In addition, the convenient interface of the FM25640 allows memory to be distributed throughout the system using minimal additional resources.

Rev. 2.1 Aug 2003 10 of 14 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VIN, VOUT Voltage on Any Pin with Respect to V SS -1.0V to V DD+1V IIN, IOUT DC Current on Any Pin 5 mA TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 4.5 5.0 5.5 V IDD VDD Supply Current @ SCK = 1.0 MHz @ SCK = 2.0 MHz @ SCK = 5.0 MHz 0.9 1.6 3.0 1.2 2.5 4.5 mA ISB Standby Current 1 10 µA 2 ILI Input Leakage Current 10 µA 3 ILO Output Leakage Current 10 µA 3 VIL Input Low Voltage -0.3 0.3 V DD V 4 VIH Input High Voltage 0.7 V DD V DD + 0.5 V 4 VOL Output Low Voltage @ IOL = 2 mA

0.4 V 4

@ IOH = -2 mA VDD - 0.8 V 4 VHYS Input Hysteresis 0.05 V DD V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VIN or VOUT = VSS to VDD 4. Characterized but not 100% tested in production.

Rev. 2.1 Aug 2003 11 of 14 AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes fCK SCK Clock Frequency 0 5.0 MHz tCH Clock High Time 90 ns tCL Clock Low Time 90 ns tCSU Chip Select Setup 90 ns tCSH Chip Select Hold 90 ns tOD Output Disable 100 ns 2 tODV Output Data Valid 60 ns tOH Output Hold 0 ns tD Deselect Time 100 ns tR Data In Rise Time 1 µs 1,2 tF Data In Fall Time 1 µs 1,2 tH Data Hold Time 30 ns tSU Data Setup Time 20 ns tHS /Hold Setup Time 70 ns tHH /Hold Hold Time 40 ns tHZ /Hold Low to Hi-Z 100 ns 2 tLZ /Hold High to Data Active 50 ns 2 Notes 1. Rise and fall times measured between 10% and 90% of waveform. 2. Characterized but not 100% tested in production. Capacitance TA = 25° C, f=1.0 MHz, VDD = 5V Symbol Parameter Max Units Notes CO Output capacitance (SDA) 8 pF 1 CI Input capacitance 6 pF 1 Notes 1. This parameter is periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels 10% and 90% of V DD Input rise and fall times 10 ns Input and output timing levels VDD*0.5 Equivalent AC Load Circuit Data Retention VDD = 4.5V to 5.5V unless otherwise specified Parameter Min Units Notes Data Retention 10 Years

Rev. 2.1 Aug 2003 12 of 14 Serial Data Bus Timing 1/fCK tCL tCH tCSH tODV tOH tOD tCSU tSU tH tD tRtF /Hold Timing

Rev. 2.1 Aug 2003 13 of 14 8-pin SOIC - JEDEC MS-012 Pin 1 Index Area E H D A B e .10 mm .004 in. α h 45 ° L C Selected Dimensions Refer to JEDEC MS-012 for complete dimensions and notes. Controlling dimensions is in millimeters. Conversions to inches are not exact. Symbol Dim Min Nom. Max A mm in. 1.35 .053 1.75 .069 A1 mm in. .10 .004 .25 .010 B mm in. .33 .013 .51 .020 C mm in. .19 .007 .25 .010 D mm in. 4.80 .189 5.00 .197 E mm in. 3.80 .150 4.00 .157 e mm in.

1.27 BSC

.050 BSC H mm in. 5.80 .228 6.20 .244 h mm in. .25 .010 .50 .197 L mm in. .40 .016 1.27 .050 α 0° 8°

Rev. 2.1 Aug 2003 14 of 14

Revision History

1.0 10/23/00 Changed status to Preliminary. 2.0 10/21/02 Changed status to Production. Changed endurance from 10 10 to 10 12 cycles. Extended storage temperature limits. 2.1 8/5/03 Removed DIP packaging option.