FM25640-G

FM25640_05 RAMTRON | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 13

Technical content

Features

64K bit Ferroelectric Nonvolatile RAM

• Organized as 8,192 x 8 bits
• High Endurance 1 Trillion (1012) Read/Writes
• 45 Year Data Retention
• NoDelay™ Writes
• Advanced high-reliability ferroelectric process Very Fast Serial Peripheral Interface - SPI
• Up to 5 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Sophisticated Write Protection Scheme
• Hardware Protection
• Software Protection Low Power Consumption
• 10 µA Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC
• “Green” 8-pin SOIC

Description

The FM25640 is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM25640 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after it has been successfully transferred to the device. The next bus cycle may commence immediately. In addition, the product offers substantial write endurance compared with other nonvolatile memories. The FM25640 is capable of supporting up to 10 12 read/write cycles -- far more than most systems will require from a serial memory. These capabilities make the FM25640 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25640 provides substantial benefits to users of serial EEPROM, in a hardware drop-in replacement. The FM25640 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration Pin Names Function /CS Chip Select /HOLD Hold /WP Write Protect SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD 5V VSS Ground

Ordering Information

FM25640-G “Green” 8-pin SOIC CS SO WP VSS VDD HOLD SCK SI

Figure 1. Block Diagram Z, all other inputs are ignored, and the device remains in a low-power standby mode. frequency may be any value between 0 and 5 MHz and may be interrupted at any time. device ignores SCK and /CS. All transitions on /HOLD must occur while SCK is low. /WP is different from the FM25040 where it prevents all writes to the part.

• SI may be connected to SO for a single pin data interface.

Rev. 3.0 Mar. 2005 3 of 13 Overview The FM25640 is a serial FRAM memory. The memory array is logically organized as 8,192 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25640 and a serial EEPROM with the same pinout relates to its superior write performance. Memory Architecture When accessing the FM25640, the user addresses 8,192 locations of 8 data bits each. These data bits are shifted in and out serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code and a two-byte address. The upper 3 bits of the address range are ignored by the device. The complete address of 13-bits specifies each byte address uniquely. Most functions of the FM25640 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation essentially is zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25640 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25640 contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that V DD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active. Serial Peripheral Interface – SPI Bus The FM25640 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 5 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25640 operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. It is possible to connect the two data lines together. Figure 2 illustrates a typical system configuration using the FM25640 with a microcontroller that offers an SPI port. Figure 3 shows a similar configuration for a microcontroller that has no hardware support for the SPI bus. Protocol Overview The SPI interface is a synchronous serial interface using clock and data lines. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25640 will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock, and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25640 supports modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. In both cases, data is clocked into the FM25640 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The FM25640 is controlled by SPI op-codes. These op-codes specify the commands to the part. After /CS is asserted, the first byte transferred from the bus master is the op-code. Following the op-code, addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.

protect inadvertent changes to the block protect bits. register is write protected if WPEN=1 and /WP=0. Table 4. Write Protection

0 X X Protected Protected Protected

any number of sequential writes may be performed. op-code. The next op-code is the WRITE instruction. edge of /CS terminates a READ op-code operation. but the SCK pin can toggle during a hold state.

Rev. 3.0 Mar. 2005 9 of 13 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +7.0V VIN Voltage on any pin with respect to V SS -1.0V to +7.0V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) 4.5kV 1.25kV Package Moisture Sensitivity Level MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 4.5 5.0 5.5 V IDD V DD Supply Current @ SCK = 1.0 MHz @ SCK = 2.0 MHz @ SCK = 5.0 MHz 0.45 0.9 2.2 0.6 1.2 3.0 mA ISB Standby Current 1 10 µA 2 ILI Input Leakage Current ±1 µA 3 ILO Output Leakage Current ±1 µA 3 VIL Input Low Voltage -0.3 0.3 V DD V VIH Input High Voltage 0.7 V DD V DD + 0.3 V VOL Output Low Voltage @ IOL = 2 mA 0.4 V VOH Output High Voltage @ IOH = -2 mA VDD - 0.8 V VHYS Input Hysteresis 0.05 V DD V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VIN or VOUT = VSS to VDD. 4. This parameter is characterized but not 100% tested.

Rev. 3.0 Mar. 2005 10 of 13 AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes fCK SCK Clock Frequency 0 5.0 MHz tCH Clock High Time 90 ns tCL Clock Low Time 90 ns tCSU Chip Select Setup 90 ns tCSH Chip Select Hold 90 ns tOD Output Disable 100 ns 2 tODV Output Data Valid 60 ns 3 tOH Output Data Hold 0 ns tD Deselect Time 100 ns tR Data In Rise Time 1 µs 1,2 tF Data In Fall Time 1 µs 1,2 tH Data In Hold Time 30 ns tSU Data In Setup Time 20 ns tHS /HOLD Input Setup Time 70 ns tHH /HOLD Input Hold Time 40 ns tHZ /HOLD Low to Data Out Hi-Z 100 ns 2 tLZ /HOLD High to Data Out Lo-Z 50 ns 2 Notes 1. Rise and fall times measured between 10% and 90% of waveform. 2. This parameter is characterized but not 100% tested. 3. For Clock High Time tCH ≤ 100 ns, the parameter tODV is extended such that tCH + tODV ≤ 160 ns. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CO Output Capacitance (SO) 8 pF 1 CI Input Capacitance 6 pF 1 Notes 1. This parameter is characterized and not 100% tested. AC Test Conditions Input Pulse Levels 10% and 90% of V DD Input rise and fall times 10 ns Input and output timing levels 0.5 V DD Output Load Capacitance 100 pF

Rev. 3.0 Mar. 2005 11 of 13 Serial Data Bus Timing 1/fCK tCL tCH tCSH tODV tOH tOD tCSU tSU tH tD tRtF /HOLD Timing Data Retention (VDD = 4.5V to 5.5V, +85°C) Parameter Min Units Notes Data Retention 45 Years

Rev. 3.0 Mar. 2005 12 of 13 Mechanical Drawing (8-pin SOIC - JEDEC MS-012, Variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45° 0.40 1.27 0.19 0.25 0°-8 ° Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXX= part number, P= package type LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25640, Standard SOIC package, Year 2004, Work Week 39 FM25640-S A40003S RIC0439 XXXXXXX-P LLLLLLL RICYYWW

Rev. 3.0 Mar. 2005 13 of 13

Revision History

1.0 10/23/00 Changed status to Preliminary. 2.0 10/21/02 Changed status to Production. Changed endurance from 10 10 to 10 12 cycles. Extended storage temperature limits. 2.1 8/5/03 Removed DIP packaging option. 2.2 11/10/03 Changed I DD limits. Changed Input & Output Leakage limits. Added note to Output Data Valid spec. 2.3 3/17/04 Added “green” package. Updated package drawing. 3.0 3/31/05 Changed Data Retention spec. Added ESD and package MSL ratings. Updated package drawing, added pcb footprint. Added note about powering down with /CS active (pg 3).