FM25256B

FM25256B RAMTRON | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

256K bit Ferroelectric Nonvolatile RAM

• Organized as 32,768 x 8 bits
• Virtually Unlimited Endurance (1014 Cycles)
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz Frequency
• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Write Protection Scheme
• Hardware Protection
• Software Protection Wide Operating Range
• Wide Voltage Operation 4.0V – 5.5V Industry Standard Configurations
• Industrial Temperature -40°C to +85°C
• 8-pin “Green”/RoHS SOIC (-G)

Description

The FM25256B is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM25256B performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. The next bus cycle may start immediately. In addition, the product offers virtually unlimited write endurance. Also, FRAM exhibits much lower power consumption than EEPROM. These capabilities make the FM25256B ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25256B provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25256B uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration Pin Name Function /CS Chip Select /WP Write Protect /HOLD Hold SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD Supply Voltage (4.0 to 5.5V) VSS Ground

Ordering Information

FM25256B-G “Green”/RoHS 8-pin SOIC CS SO WP VSS VDD HOLD SCK SI

Figure 1. Block Diagram /WP Input Write Protect: This active low pin prevents write operations to the status register only. A complete explanation of write protection is provided on pages 6 and 7.

• SI may be connected to SO for a single pin data interface.

the falling edge of the serial clock.

• SO may be connected to SI for a single pin data interface.

Rev. 3.0 July 2007 Page 3 of 13 Overview The FM25256B is a serial FRAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25256B and a serial EEPROM with the same pinout is the FRAM’s superior write performance and power consumption. Memory Architecture When accessing the FM25256B, the user addresses 32K locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two- byte address. The upper bit of the address range is a “don’t care” value. The complete address of 15-bits specifies each byte address uniquely. Most functions of the FM25256B either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25256B due to its fast write cycle and high endurance as compared to EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25256B contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that V DD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active. Serial Peripheral Interface – SPI Bus The FM25256B employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 20 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25256B operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25256B devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25256B device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the Hold pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25256B will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25256B supports only modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25256B on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.

from VDD (min) to the first /CS low. Table 1. Op-code Commands The FM25256B will power up with writes disabled. register and writing the memory. register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. register has no effect on the state of this bit. illustrates the WREN command bus configuration. 6 illustrates the WRDI command bus configuration. Figure 5. WREN Bus Configuration

BP1 and BP0 are memory block write protection bits. protected as shown in the following table. Table 3. Block Memory Write Protection protect inadvertent changes to the block protect bits. Register is write protected if WPEN=1 and /WP=0. write protection conditions. Table 4. Write Protection

0 X X Protected Protected Protected

any number of sequential writes may be performed. op-code. The next op-code is the WRITE instruction. value. The upper bit of the address is a “don’t care”. until the next falling edge of /CS. master issues 8 clocks, with one bit read out for each. edge of /CS terminates a READ op-code operation. A read operation is shown in Figure 10.

Rev. 3.0 July 2007 Page 9 of 13 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +7.0V VIN Voltage on any pin with respect to V SS -1.0V to +7.0V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) 4kV 1kV 200V Package Moisture Sensitivity Level MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40°C to + 85°C, VDD = 4.0V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 4.0 5.0 5.5 V IDD Power Supply Current @ SCK = 1.0 MHz @ SCK = 20.0 MHz 0.75 15.0 mA mA ISB Standby Current - 150 µA 2 ILI Input Leakage Current - ±1 µA 3 ILO Output Leakage Current - ±1 µA 3 VIH Input High Voltage 0.7 V DD V DD + 0.5 V VIL Input Low Voltage -0.3 0.3 V DD V VOH Output High Voltage @ IOH = -2 mA VDD – 0.8 - V VOL Output Low Voltage @ IOL = 2 mA - 0.4 V Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD.

Rev. 3.0 July 2007 Page 10 of 13 AC Parameters (TA = -40°C to + 85°C, VDD = 4.0V to 5.5V, CL = 30pF) Symbol Parameter Min Max Units Notes fCK SCK Clock Frequency 0 20 MHz tCH Clock High Time 28 ns 1 tCL Clock Low Time 28 ns 1 tCSU Chip Select Setup 10 ns tCSH Chip Select Hold 10 ns tOD Output Disable Time 20 ns 2 tODV Output Data Valid Time 24 ns tOH Output Hold Time 0 ns tD Deselect Time 80 ns tR Data In Rise Time 50 ns 2,3 tF Data In Fall Time 50 ns 2,3 tSU Data Setup Time 5 ns tH Data Hold Time 5 ns tHS /Hold Setup Time 10 ns tHH /Hold Hold Time 10 ns tHZ /Hold Low to Hi-Z 25 ns 2 tLZ /Hold High to Data Active 20 ns 2 Notes 1. tCH + tCL = 1/fCK. 2. This parameter is characterized but not 100% tested. 3. Rise and fall times measured between 10% and 90% of waveform. Power Cycle Timing (TA = -40° C to + 85° C, VDD = 4.0V to 5.5V) Symbol Parameter Min Max Units Notes tPU Power Up (V DD min) to First Access (/CS low) 10 - ms tPD Last Access (/CS high) to Power Down (V DD min) 0 - µs tVR V DD Rise Time 50 µs/V 1 tVF V DD Fall Time - For VDD above 2.0V - For VDD below 2.0V µs/V ms/V Notes 1. Slope measured at any point on VDD waveform. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5.0V) Symbol Parameter Min Max Units Notes CO Output Capacitance (SO) - 8 pF 1 CI Input Capacitance - 6 pF 1 Notes 1. This parameter is characterized and not 100% tested. AC Test Conditions Input Pulse Levels 10% and 90% of V DD Input rise and fall times 5 ns Input and output timing levels 0.5 V DD Output Load Capacitance 30 pF

Rev. 3.0 July 2007 Page 11 of 13 Serial Data Bus Timing /HOLD Timing CS SCK SO HOLD tHS tHH tHZ tLZ tHS tHH Power Cycle Timing VDD min tPU VDD CS tVR tPD tVF Data Retention (VDD = 4.0V to 5.5V) Parameter Min Max Units Notes Data Retention 10 - Years

Rev. 3.0 July 2007 Page 12 of 13 Mechanical Drawing 8-pin SOIC (JEDEC MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45° 0.40 1.27 0.19 0.25 0°- 8° Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXXXXX= part number, P= package type LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25256B, “Green” SOIC package, Year 2006, Work Week 39 FM25256B-G B70003G RIC0639 XXXXXXX-P LLLLLLL RICYYWW

Rev. 3.0 July 2007 Page 13 of 13

Revision History

2.0 4/4/07 Initial release. 3.0 7/9/07 Changed to Production status. Added ESD ratings. Updated endurance section.