FM25040C RAMTRON | Alldatasheet
Document overview
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Technical content
Features
4K bit Ferroelectric Nonvolatile RAM Organized as 512 x 8 bits High Endurance 1 Trillion (1012) Read/Writes 36 year Data Retention at +75C NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI Up to 20 MHz maximum Bus Frequency Direct hardware replacement for EEPROM SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Sophisticated Write Protection Scheme Hardware Protection Software Protection Low Power Consumption 250 A Active Current (1 MHz) 4 A (typ.) Standby Current Industry Standard Configuration Industrial Temperature -40 C to +85 C 8-pin “Green”/RoHS SOIC (-G)
Description
The FM 25040C is a 4 -kilobit nonvolatile memory employing an advanced ferroelectric proc ess. A ferroelectric random access memory or F-RAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 36 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM 25040C performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM25 040C is capable of supporting up to 10 12 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM 25040C ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25040C provides substantial benefits to users of serial EEPROM, in a hardware drop -in replacement. The FM25 040C uses the high -speed SPI bus, which enhances the high -speed write capability of F-RAM technology. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration Pin Names Function /CS Chip Select /WP Write Protect /HOLD Hold SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD Supply Voltage 5V VSS Ground
Ordering Information
FM25040C-G “Green” 8-pin SOIC FM25040C-GTR “Green” 8-pin SOIC, Tape & Reel CS SO WP VSS VDD HOLD SCK SI
Figure 1. Block Diagram frequency may be any value between 0 and 20 MHz and may be interrupted at any time. any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low.
- SI may be connected to SO for a single pin data interface.
falling edge of the serial clock.
FM25040C - 4Kb 5V SPI F-RAM Rev. 1.1 July 2011 Page 3 of 13 Overview The FM 25040C is a serial F-RAM memory. The memory array is logically organized as 512 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the F- RAM is similar to serial EEPROMs. The major difference between the FM 25040C and a serial EEPROM with the same pin -out relates to its superior write performance. This makes the FM25040C a drop-in replacement for most 4Kb SPI EEPROMs that support Modes 0 & 3. Memory Architecture When accessing the FM 25040C, the user addresses 512 locations each with 8 data bits. These data bits are shifted se rially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op -code including the upper address bit, and a word address. The word address consists of the lower 8 -address bits. The comp lete address of 9 -bits specifies each byte address uniquely. Most functions of the FM 25040C either are controlled by the SPI interface or are handled automatically by on -board circuitry. The access time for memory operation essentially is zero, beyond th e time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transa ction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section that follows. Users expect several obvious system benefits from the FM 25040C due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast -write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring mil liseconds to write is vulnerable to noise during much of the cycle. Note that the FM 25040C contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that V DD is within datasheet tolerance s to prevent incorrect operation . It is recommended that the part is not powered down with chip enable active. Serial Peripheral Interface – SPI Bus The FM25040C employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 20 MHz. This high -speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25040C operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data -out, and chip select. A typical system configuration uses one or more FM 25040C devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data -in, and data -out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25040C device. For a microcontroller that has no dedicate d SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (high) the /HOLD pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data lines. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM 25040C will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are f our suc h modes, the FM25040C supports Modes 0 and 3. Figure 4 shows the req uired signal relationships for M odes 0 and 3. For both modes, data is clocked into the FM 25040C on the rising edge of SCK and data is expected on the first rising edge after /CS g oes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The SPI protocol is controlled by op -codes. These op-codes specify the commands to the part. After /CS is activated the first byte transferred from the bus master is the op -code. Following the op -code, any addresses and data are then transferred. Note that the WREN and WRDI op -codes are commands with no subsequent data transfer. Important: The /CS must go inactive (high) after an operation is complete and before a new op -code can be issued. There is one valid op -code only per active chip select.
protect inadvertent changes to the block protect bits. summarizes the write protection conditions . Table 4. Write Protection
0 X Protected Protected Protected
any number of sequential writes may be performed. the address of the first byte of the read operation. After the op -code is complete, the SI pin is ignored. edge of /CS terminates a READ op -code operation.. but the SCK pin can toggle during a hold state.
FM25040C - 4Kb 5V SPI F-RAM Rev. 1.1 July 2011 Page 9 of 13 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to VSS -1.0V to +7.0V VIN Voltage on any pin with respect to VSS -1.0V to +7.0V and VIN < VDD+1.0V TSTG Storage Temperature -55C to + 125C TLEAD Lead Temperature (Soldering, 10 seconds) 260 C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 4kV 1.25kV 300V Package Moisture Sensitivity Level MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 4.5 5.0 5.5 V IDD VDD Supply Current @ SCK = 1.0 MHz @ SCK = 20.0 MHz 0.25 4.0 mA mA ISB Standby Current 4 10 A 2 ILI Input Leakage Current 1 A 3 ILO Output Leakage Current 1 A 3 VIH Input High Voltage 0.7 VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.3 VDD V VOH Output High Voltage @ IOH = -1 mA VDD – 0.8 - V VOL Output Low Voltage @ IOL = 2 mA - 0.4 V VHYS Input Hysteresis 0.05 VDD - V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VIN or VOUT = VSS to VDD. 4. This parameter is periodically sampled and not 100% tested. Applies only to /CS and SCK pins.
FM25040C - 4Kb 5V SPI F-RAM Rev. 1.1 July 2011 Page 10 of 13 AC Parameters (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes fCK SCK Clock Frequency 0 20 MHz tCH Clock High Time 22 ns 1 tCL Clock Low Time 22 ns 1 tCSU Chip Select Setup 10 ns tCSH Chip Select Hold 10 ns tOD Output Disable 20 ns 2 tODV Output Data Valid 20 ns tOH Output Hold 0 ns tD Deselect Time 60 ns tR Data In Rise Time 50 ns 1,3 tF Data In Fall Time 50 ns 1,3 tSU Data Setup Time 5 ns tH Data Hold Time 5 ns tHS /Hold Setup Time 10 ns tHH /Hold Hold Time 10 ns tHZ /Hold Low to Hi-Z 20 ns 2 tLZ /Hold High to Data Active 20 ns 2 Notes 1. tCH + tCL = 1/fCK. 2. Rise and fall times measured between 10% and 90% of waveform. 3. This parameter is characterized and not 100% tested. Capacitance (TA = 25C , f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CO Output Capacitance (SO) 8 pF 1 CI Input Capacitance 6 pF 1 Notes 1. This parameter is periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels 10% and 90% of VDD Input Rise and Fall Times 5 ns Input and Output Timing Levels 0.5 VDD Output Load Capacitance 30 pF Data Retention Symbol Parameter Min Max Units Notes TDR @ +85ºC 10 - Years @ +80ºC 18 - Years @ +75ºC 36 - Years
FM25040C - 4Kb 5V SPI F-RAM Rev. 1.1 July 2011 Page 11 of 13 Serial Data Bus Timing CS SCK SI SO 1/tCK tCL tCH tCSH tODV tOH tOD tCSU tSU tH tD tRtF /Hold Timing CS SCK SO HOLD tHS tHH tHZ tLZ tHS tHH Power Cycle Timing VDD min tPU VDD CS tVR tPD tVF Power Cycle Timing (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes tPU VDD(min) to First Access Start 1 - ms tPD Last Access Complete to VDD(min) 0 - s tVR VDD Rise Time 30 - s/V 1 tVF VDD Fall Time 100 - s/V 1 Notes 1. Slope measured at any point on VDD waveform.
FM25040C - 4Kb 5V SPI F-RAM Rev. 1.1 July 2011 Page 12 of 13 Mechanical Drawing (8-pin SOIC - JEDEC Standard MS-012, Variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 0.40 1.27 0.19 0.25 - 8 Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXXXX= part number, P= package type (G=SOIC) R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25040C, “Green” SOIC package, Year 2010, Work Week 51 FM25040C-G A00002G1 RIC1051 XXXXXXX-P RLLLLLLL RICYYWW
FM25040C - 4Kb 5V SPI F-RAM Rev. 1.1 July 2011 Page 13 of 13
Revision History
1.0 3/22/2011 Initial Release 1.1 7/18/2011 Added ESD ratings.