FM25040A

FM25040A RAMTRON | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

4K bit Ferroelectric Nonvolatile RAM

• Organized as 512 x 8 bits
• High Endurance 1 Trillion (1012) Read/Writes
• 45 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz maximum Bus Frequency
• Direct hardware replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Sophisticated Write Protection Scheme
• Hardware Protection
• Software Protection Low Power Consumption
• 10 µA Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC (-S)
• “Green” 8-pin SOIC (-G)

Description

The FM25040A is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM25040A performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. In addition the product offers substantial write endurance compared with other nonvolatile memories. The FM25040A is capable of supporting up to 10 12 read/write cycles -- far more than most systems will require from a serial memory. These capabilities make the FM25040A ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25040A provides substantial benefits to users of serial EEPROM, in a hardware drop-in replacement. The FM25040A uses the high-speed SPI bus which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration Pin Names Function /CS Chip Select /WP Write Protect /HOLD Hold SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD Supply Voltage 5V VSS Ground

Ordering Information

FM25040A-G “Green” 8-pin SOIC CS SO WP VSS VDD HOLD SCK SI

Figure 1. Block Diagram frequency may be any value between 0 and 20 MHz and may be interrupted at any time. any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low.

• SI may be connected to SO for a single pin data interface.

falling edge of the serial clock.

Rev. 3.0 May 2006 Page 3 of 13 Overview The FM25040A is a serial FRAM memory. The memory array is logically organized as 512 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25040A and a serial EEPROM with the same pin-out relates to its superior write performance. The FM25040A differs from Ramtron’s FM25040 by increasing its performance to 20MHz and adding support for SPI Mode 3. This makes the FM25040A a drop-in replacement for most 4Kb SPI EEPROMs that support Modes 0 & 3. Memory Architecture When accessing the FM25040A, the user addresses 512 locations each with 8 data bits. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code including the upper address bit, and a word address. The word address consists of the lower 8-address bits. The complete address of 9-bits specifies each byte address uniquely. Most functions of the FM25040A either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation essentially is zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section that follows. Users expect several obvious system benefits from the FM25040A due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25040A contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that V DD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active. Serial Peripheral Interface – SPI Bus The FM25040A employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 20 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25040A operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25040A devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25040A device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (high) the /HOLD pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data lines. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25040A will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25040A supports Modes 0 and 3. Figure 4 shows the required signal relationships for Modes 0 and 3. For both modes, data is clocked into the FM25040A on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the part. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS must go inactive (high) after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.

protect inadvertent changes to the block protect bits. summarizes the write protection conditions. Table 4. Write Protection

0 X Protected Protected Protected

any number of sequential writes may be performed. the address of the first byte of the read operation. After the op-code is complete, the SI pin is ignored. edge of /CS terminates a READ op-code operation.. but the SCK pin can toggle during a hold state.

Rev. 3.0 May 2006 Page 9 of 13 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +7.0V VIN Voltage on any pin with respect to V SS -1.0V to +7.0V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) 4kV 1kV 400V Package Moisture Sensitivity Level MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 4.5 5.0 5.5 V IDD VDD Supply Current @ SCK = 1.0 MHz @ SCK = 20.0 MHz 0.2 0.4 8.0 mA mA ISB Standby Current - 10 µA 2 ILI Input Leakage Current ±1 µA 3 ILO Output Leakage Current ±1 µA 3 VIH Input High Voltage 0.7 V DD V DD + 0.5 V VIL Input Low Voltage -0.3 0.3 V DD V VOH Output High Voltage @ IOH = -1 mA VDD – 0.8 - V VOL Output Low Voltage @ IOL = 2 mA - 0.4 V VHYS Input Hysteresis 0.05 V DD - V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VIN or VOUT = VSS to VDD. 4. This parameter is periodically sampled and not 100% tested.

Rev. 3.0 May 2006 Page 10 of 13 AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes fCK SCK Clock Frequency 0 20 MHz tCH Clock High Time 22 ns 1 tCL Clock Low Time 22 ns 1 tCSU Chip Select Setup 10 ns tCSH Chip Select Hold 10 ns tOD Output Disable 20 ns 2 tODV Output Data Valid 20 ns tOH Output Hold 0 ns tD Deselect Time 60 ns tR Data In Rise Time 50 ns 1,3 tF Data In Fall Time 50 ns 1,3 tSU Data Setup Time 5 ns tH Data Hold Time 5 ns tHS /Hold Setup Time 10 ns tHH /Hold Hold Time 10 ns tHZ /Hold Low to Hi-Z 20 ns 2 tLZ /Hold High to Data Active 20 ns 2 Notes 1. tCH + tCL = 1/fCK. 2. Rise and fall times measured between 10% and 90% of waveform. 3. This parameter is characterized and not 100% tested. Capacitance (TA = 25°C , f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CO Output Capacitance (SO) 8 pF 1 CI Input Capacitance 6 pF 1 Notes 1. This parameter is periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels 10% and 90% of V DD Input Rise and Fall Times 5 ns Input and Output Timing Levels 0.5 V DD Output Load Capacitance 30 pF

Rev. 3.0 May 2006 Page 11 of 13 Data Retention (VDD = 4.5V to 5.5V, +85°) Parameter Min Units Notes Data Retention 45 Years Serial Data Bus Timing /Hold Timing

Rev. 3.0 May 2006 Page 12 of 13 Mechanical Drawing (8-pin SOIC - JEDEC Standard MS-012, Variation AA) Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXX= part number, P= package type LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25040A, Standard SOIC package, Year 2004, Work Week 50 FM25040A-S A40003S RIC0450 XXXXXXX-P LLLLLLL RICYYWW

Rev. 3.0 May 2006 Page 13 of 13

Revision History

0.1 7/15/04 Initial Release 0.11 12/7/04 Added comment in Overview about differences between A and non-A devices. Rewrote chip select operation in Protocol Overview section (pg. 3). Updated mechanical drawing with pcb footprint. 2.0 4/11/05 Changed to Pre-Production status. Changed Data Retention spec. Added ESD and package MSL ratings. 3.0 5/5/06 Changed to Production status.