FM24CL64B RAMTRON | Alldatasheet
Document overview
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Technical content
Features
64K bit Ferroelectric Nonvolatile RAM Organized as 8192 x 8 bits High Endurance 10 Trillion (1013) Read/Writes NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface Up to 1 MHz maximum bus frequency Direct hardware replacement for EEPROM Supports legacy timing for 100 kHz & 400 kHz Low Power Consumption Low Voltage Operation 3.0-3.6V 6 A Standby Current (+85C) Industry Standard Configuration Automotive Temperature -40C to +125C o Qualified to AEC Q100 Specification 8-pin “Green”/RoHS SOIC Package
Description
The FM 24CL64B is a 64Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory o r F-RAM is nonvolatile and performs reads and writes like a RAM. It provide s reliable data retention for years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM 24CL64B performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. In addition, the product offers write endurance orders of magnitude higher than EEPROM. Also, F-RAM exhibits much lower power during writes than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits. These capabilities make the FM 24CL64B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. The FM 24CL64B provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop -in repla cement. The device is available in industry stan dard 8 -pin SOIC package using a familiar two-wire (I2C) protocol. The device is guaranteed over the automotive temperature range of -40°C to +125°C. Pin Configuration VSS VDD WP SCL SDA Pin Name Function A0-A2 Device Select Address SDA Serial Data/address SCL Serial Clock WP Write Protect VDD Supply Voltage VSS Ground
Ordering Information
FM24CL64B-GA “Green”/RoHS 8 -pin SOIC , Automotive Grade 1 FM24CL64B-GATR “Green”/RoHS 8 -pin SOIC, Automotive Grade 1, Tape & Reel
Figure 1. FM24CL64B Block Diagram address pins are pulled down internally. open-drain and is intended to be wire -OR‟d with other devices on the two-wire bus. also incorporates a Schmitt trigger input for noise immunity.
with higher density devices in the future. zero beyond the time needed for the serial protocol. more detail in the interface section below. vulnerable to noise during much of the cycle. users but is described in this section. device on the bus that is being controlled is a slave. The FM24CL64B always is a slave device. electrical specifications section. Figure 2. Typical System Configuration
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) Rev. 1.1 June 2011 Page 5 of 12 Addressing Overview After the FM 24CL64B (as r eceiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. The address requires two bytes . The first is the MSB. Since the device uses only 13 address bits, the value of the upper three bits are “don‟t care”. Following the MSB is the LSB with the remaining eight address bits. The address value is latched internally. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch -- either a newly written value or the address following the last access. The current address will be held for as long as power remains or until a new value is written. Reads always use the current address. A random read address can be l oaded by beginning a write operation as explained below. After transmission of each data byte, just prior to the acknowledge, the FM24CL64B increments the internal address latch. This allows the next sequential byte to be accessed with no additional addre ssing. After the last address (1FFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Data Transfer After the address information has been transmit ted, data transfer between the bus master and the FM24CL64B can begin. For a read operation the FM24CL64B will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM 24CL64B will transfer the next sequen tial byte. If the acknowledge is not sent, the FM 24CL64B will end the read operation. For a write operation, the FM 24CL64B will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. Memory Operation The FM24CL64B is designed to operate in a manner very similar to other 2 -wire interface memory products. The major differences result from the higher performance write capability of F-RAM technology. These improvements result in some differences between the FM 24CL64B and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. Write Operation All writes begin with a slave address, then a memory address. The bus master indicates a write op eration by setting the LSB of the slave address (R/W bit) to a „0‟. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the a ddress range is reached internally, the address counter will wrap from 1FFFh to 0000h. Unlike other nonvolatile memory technologies, there is no effective write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROM s to determine if a write is complete is unnecessary and will always return a ready condition. Internally, an actual memory write occurs after the 8 th data bit is transferred. It will be complete before the acknowledge is sent. Therefore, if the user des ires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8 th data bit. The FM 24CL64B uses no page buffering. The memory array can be write -protected using the WP pin . Setting the WP pin to a high condition (VDD) will write -protect all addresses. The FM24CL64B will not acknowledge data bytes that are written to protected addresses. In addition, the address counter will not increment if writes are attempted to these addresses. Setting WP to a low state (V SS) will deactivate this feature. WP is pulled down internally. Figures 5 and 6 below illustrate a single -byte and multiple-byte write cycles.
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) Rev. 1.1 June 2011 Page 8 of 12 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to VSS -1.0V to +4.5V VIN Voltage on any pin with respect to VSS -1.0V to +4.5V and VIN < VDD+1.0V * TSTG Storage Temperature -55C to +125C TLEAD Lead Temperature (Soldering, 10 seconds) 260 C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 4kV 1.25kV 300V Package Moisture Sensitivity Level MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 125 C, VDD =3.0V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 3.0 3.3 3.6 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 120 200 340 ISB Standby Current @ +85C @ +125C ILI Input Leakage Current ±1 A 3 ILO Output Leakage Current ±1 A 3 VIL Input Low Voltage -0.3 0.25 VDD V VIH Input High Voltage 0.75 VDD VDD + 0.3 V VOL Output Low Voltage (IOL = 3 mA) 0.4 V RIN Address Input Resistance (WP, A2-A0) For VIN = VIL (max) For VIN = VIH (min) VHYS Input Hysteresis 0.05 VDD V 4 Notes 1. SCL toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V. 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins. 4. This parameter is characterized but not tested. 5. The input pull-down circuit is stronger (40K) when the input voltage is below VIL and weak (1M) when the input voltage is above VIH.
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) Rev. 1.1 June 2011 Page 9 of 12 AC Parameters (TA = -40 C to + 125 C, VDD =3.0V to 3.6V unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz 1 tLOW Clock Low Period 4.7 1.3 0.6 s tHIGH Clock High Period 4.0 0.6 0.4 s tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 s tBUF Bus Free Before New Transmission 4.7 1.3 0.5 s tHD:STA Start Condition Hold Time 4.0 0.6 0.25 s tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 s tHD:DAT Data In Hold 0 0 0 ns tSU:DAT Data In Setup 250 100 100 ns tR Input Rise Time 1000 300 300 ns 2 tF Input Fall Time 300 300 100 ns 2 tSU:STO Stop Condition Setup 4.0 0.6 0.25 s tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes: All SCL specifications as well as start and stop conditions apply to both read and write operations. 1. The speed-related specifications are guaranteed characteristic points along a continuous cur ve of operation from DC to f SCL (max). 2. This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CI/O Input/Output Capacitance (SDA) - 8 pF 1 CIN Input Capacitance - 6 pF 1 Notes 1. This parameter is periodically sampled and not 100% tested. Power Cycle Timing VDD min.VDD SDA,SCL tVR tPDtPU tVF Power Cycle Timing (TA = -40 C to +125 C, VDD = 3.0V to 3.6V) Symbol Parameter Min Max Units Notes tPU Power Up (VDD min) to First Access (Start condition) 10 - ms tPD Last Access (Stop condition) to Power Down (VDD min) 0 - s tVR VDD Rise Time 30 - s/V 1 tVF VDD Fall Time 100 - s/V 1 Notes 1. Slope measured at any point on VDD waveform.
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) Rev. 1.1 June 2011 Page 10 of 12 AC Test Conditions Equivalent AC Test Load Circuit Input Pulse Levels 0.1 VDD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 VDD Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relati onships are illustrated in the relevant datasheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing tSU:SDA Start tR tF Stop Start tBUF tHIGH 1/fSCL tLOW tSP tSP Acknowledge tHD:DAT tSU:DAT tAA tDH SCL SDA Write Bus Timing tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA Data Retention Parameter Min Max Units Notes Data Retention @ TA = +55C @ TA = +105C @ TA = +125C 10,000 1,000 Years Hours Hours Note: Data retention qualification tests are accelerated tests and are performed such that all three conditions have been applied: (1) 17 years at a temperature of +55C, (2) 10,000 hours at +105C, and (3) 1,000 hours at +125C. Typical Grade 1 Operating Profile 200 400 600 800 1000 1200 1400 1600 70 75 80 85 90 95 100 105 110 115 120 125 Temperature (°C) Hours Typical Grade 1 Storage Profile 5000 10000 15000 20000 25000 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Temperature (°C) Hours 3.6V Output
1.8 Kohm
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) Rev. 1.1 June 2011 Page 11 of 12 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 0.40 1.27 0.19 0.25 - 8 Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXXX= part number, P=package type R=rev code, LLLLLLL= lot code RIC=Ramtron Int‟l Corp, YY=year, WW=work week Example: FM24CL64B-GA, “Green” SOIC, Automotive Temperature, Rev A, Lot L3502G1, Year 2011, Work Week 04 24CL64BGA AL3502G1 RIC1104 XXXXXX-P RLLLLLLL RICYYWW
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.) Rev. 1.1 June 2011 Page 12 of 12
Revision History
1.0 2/22/2011 Initial Release 1.1 6/2/2011 Added ESD ratings. Fixed notes 4 and 5 in DC table.