FM24CL16-DG

FM24CL16_05 RAMTRON | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

16K bit Ferroelectric Nonvolatile RAM

• Organized as 2,048 x 8 bits
• Unlimited Read/Write Cycles
• 45 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface
• Up to 1MHz Maximum Bus Frequency
• Direct Hardware Replacement for EEPROM Low Power Operation
• 2.7 - 3.65V Operation
• 75 µA Active Current (100 kHz) @ 3V
• 1 µA Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC and 8-pin TDFN Packages
• TDFN Footprint Conforms to TSSOP-8
• “Green” Packaging Options

Description

The FM24CL16 is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM24CL16 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. In addition, the product offers unlimited write endurance, orders of magnitude more endurance than EEPROM. Also, FRAM exhibits much lower power during writes than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits. These capabilities make the FM24CL16 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where a long write time can cause data loss. The combination of features allows the system to write data more frequently, with less system overhead. The FM24CL16 is available in an industry standard 8-pin SOIC and uses a two-wire protocol. The specifications are guaranteed over the industrial temperature range from -40°C to +85°C. Pin Configuration Pin Names Function SDA Serial Data/Address SCL Serial Clock WP Write Protect VDD Supply Voltage VSS Ground

Ordering Information

FM24CL16-G “Green” 8-pin SOIC FM24CL16-DG “Green” 8-pin TDFN NC NC NC VSS VDD WP SCL SDA Top View 1 VSS SDA SCL NC WP VDD NC NC

Figure 1. Block Diagram output driver includes slope control for falling edges. A pull-up resistor is required. the falling edge and clocked-in on the rising edge. all addresses may be written. This pin is internally pulled down.

Rev 3.3 Nov. 2005 Page 8 of 13 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +5.0V VIN Voltage on any pin with respect to V SS -1.0V to +5.0V and VIN < VDD+1.0V TSTG Storage Temperature -40°C to + 125°C TLEAD Lead temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Machine Model (JEDEC Std JESD22-A115-A) 4kV 300V Package Moisture Sensitivity Level MSL-1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD =2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 2.7 3.65 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 200 450 µA µA µA ISB Standby Current 1 µA 2 ILI Input Leakage Current ±1 µA 3 ILO Output Leakage Current ±1 µA 3 VIH Input High Voltage 0.7 V DD V DD + 0.5 V VIL Input Low Voltage -0.3 0.3 V DD V VOL Output Low Voltage @ IOL = 3.0 mA 0.4 V RIN WP Input Resistance (WP) For VIN = VIL (max) For VIN = VIH (min) KΩ MΩ VHYS Input Hysteresis (Does not apply to WP) 0.05 V DD V 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to pins with pull down resistors. 4. This parameter is characterized but not tested. 5. The input pull-down circuit is strong (50KΩ ) when the input voltage is below VIL and much weaker (1MΩ ) when the input voltage is above VIH.

Rev 3.3 Nov. 2005 Page 9 of 13 AC Parameters (TA = -40° C to + 85° C, VDD =2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz 1 tLOW Clock Low Period 4.7 1.3 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 µs tHD:DAT Data In Hold Time 0 0 0 ns tSU:DAT Data In Setup Time 250 100 100 ns tR Input Rise Time 1000 300 300 ns 2 tF Input Fall Time 300 300 100 ns 2 tSU:STO Stop Condition Setup 4.0 0.6 0.25 µs tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 The speed-related specifications are guaranteed characteristic points from DC to 1 MHz. 2 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3V) Symbol Parameter Max Units Notes CI/O Input/Output Capacitance (SDA) 8 pF 1 CIN Input Capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels 0.1 V DD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 V DD Equivalent AC Load Circuit 3.65V Output 1100 Ω 100 pF

Rev 3.3 Nov. 2005 Page 10 of 13 Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing t SU:STA Start tR tF Stop Start tBUF tHIGH 1/fSCL tLOW tSP t SP Acknowledge tHD:DAT tSU:DAT tAA tDH SCL SDA Write Bus Timing tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA Data Retention (VDD = 2.7V to 3.65V, 85°C) Parameter Min Units Notes Data Retention 45 Years

Rev 3.3 Nov. 2005 Page 11 of 13 Mechanical Drawing 8-pin SOIC (JEDEC MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45° 0.40 1.27 0.19 0.25 0°-8 ° Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Seating Plane Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXX= part number, P= package type LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24CL16, Standard SOIC package, Year 2004, Work Week 39 FM24CL16-S A40003S RIC0439 XXXXXXX-P LLLLLLL RICYYWW

Rev 3.3 Nov. 2005 Page 12 of 13 8-pin TDFN (3.0mm x 6.4mm body, 0.65mm pitch) Pin 1 6.40 ±0.1 3.00 ±0.1 0.75 ±0.05 0.25 ±0.05 0.65 0.20 REF. Pin 1 ID 0.0 - 0.05 Exposed metal pad. Do not connect to anything, except Vss. 6.70 0.300.65 Recommended PCB Footprint 0.40 ±0.1 0.60 3.10 1.10 Note: All dimensions in millimeters. This package is footprint compatible with the 8-pin TSSOP. Legend: RIC=Ramtron Int’l Corp, G=”green” TDFN package XXXX=base part number LLLL= lot code YY=year, WW=work week Example: “Green” TDFN package, FM24CL16, Lot 0003, Year 2004, Work Week 39 RICG 4L16 0003 0439 RICG XXXX LLLL YYWW

Rev 3.3 Nov. 2005 Page 13 of 13

Revision History

1.0 2/15/01 Initial Release. 1.1 9/29/01 Endurance changed to unlimited. 2.0 2/22/02 Changed to Production status. Added clarification to package standard and changed package name to SOIC. 2.1 3/24/03 Added “green” packaging option. 2.2 6/24/04 Changed storage temp range -55 to +125 C. Removed Data Retention note. 3.0 7/14/04 Changed I DD limits. New rev. number to comply with updated scheme. 3.1 11/19/04 Added DFN package ordering option and added mechanical drawing. Added pcb footprint drawings. Increased Idd @ 1MHz to 450uA. 3.2 3/8/05 Changed Data Retention spec. Added ESD and package MSL ratings. Removed “preliminary” from DFN package drawing. 3.3 11/28/05 Changed package name from DFN to TDFN. Fixed formatting of notes in DC table. Removed ref to note 4 on VIH and VIL parameters. Added note to VHYS.